| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hubbub.c | 836 unsigned int bpe,
846 hubbub1_get_blk256_size(&blk256_width, &blk256_height, bpe);
848 swath_bytes_horz_wc = height * blk256_height * bpe;
849 swath_bytes_vert_wc = width * blk256_width * bpe;
869 unsigned int bpe; local in function:hubbub1_get_dcc_compression_cap
878 if (!hubbub1->base.funcs->dcc_support_pixel_format(input->format, &bpe))
881 if (!hubbub1->base.funcs->dcc_support_swizzle(input->swizzle_mode, bpe,
886 bpe, &req128_horz_wc, &req128_vert_wc);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hubbub.c | 197 unsigned int bpe,
205 hubbub2_get_blk256_size(&blk256_width, &blk256_height, bpe);
207 swath_bytes_horz_wc = width * blk256_height * bpe;
208 swath_bytes_vert_wc = height * blk256_width * bpe;
226 unsigned int bpe; local in function:hubbub2_get_dcc_compression_cap
236 &bpe))
239 if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe,
245 bpe, &req128_horz_wc, &req128_vert_wc);
278 if ((bpe == 2) && (input->swizzle_mode == DC_SW_64KB_R_X))
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calcs.c | 328 unsigned int bpe; local in function:pipe_ctx_to_e2e_pipe_params
331 dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0;
975 unsigned int bpe; local in function:dcn_validate_bandwidth
978 pipe->plane_state->format, &bpe) ? dcn_bw_yes : dcn_bw_no;
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_evergreen_cs.c | 192 unsigned bpe; member in struct:eg_surface
203 surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples;
204 surf->base_align = surf->bpe;
217 palign = MAX(64, track->group_size / surf->bpe);
218 surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples;
239 palign = track->group_size / (8 * surf->bpe * surf->nsamples);
241 surf->layer_size = surf->nbx * surf->nby * surf->bpe;
249 track->group_size, surf->bpe, surf->nsamples);
271 tileb = 64 * surf->bpe * surf->nsamples;
311 surf->bpe = r600_fmt_get_blocksize(surf->format)
[all...] |
| radeon_r600_cs.c | 524 u32 nviews, bpe, ntiles, slice_tile_max, tmp; local in function:r600_cs_track_validate_db
540 bpe = 2;
547 bpe = 4;
550 bpe = 8;
562 tmp = (tmp / bpe) >> 6;
565 track->db_depth_size, bpe, track->db_offset,
585 array_check.blocksize = bpe;
625 tmp = ntiles * bpe * 64 * nviews * track->nsamples;
629 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
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