1 /* $NetBSD: ixgbe_type.h,v 1.62 2023/11/15 03:50:22 msaitoh Exp $ */ 2 3 /****************************************************************************** 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Copyright (c) 2001-2020, Intel Corporation 7 All rights reserved. 8 9 Redistribution and use in source and binary forms, with or without 10 modification, are permitted provided that the following conditions are met: 11 12 1. Redistributions of source code must retain the above copyright notice, 13 this list of conditions and the following disclaimer. 14 15 2. Redistributions in binary form must reproduce the above copyright 16 notice, this list of conditions and the following disclaimer in the 17 documentation and/or other materials provided with the distribution. 18 19 3. Neither the name of the Intel Corporation nor the names of its 20 contributors may be used to endorse or promote products derived from 21 this software without specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 27 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 POSSIBILITY OF SUCH DAMAGE. 34 35 ******************************************************************************/ 36 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 331224 2018-03-19 20:55:05Z erj $*/ 37 38 #ifndef _IXGBE_TYPE_H_ 39 #define _IXGBE_TYPE_H_ 40 41 #include <sys/types.h> 42 #include <sys/socket.h> 43 #include <dev/pci/pcidevs.h> 44 #include <net/if.h> 45 #include <net/if_ether.h> 46 47 /* 48 * The following is a brief description of the error categories used by the 49 * ERROR_REPORT* macros. 50 * 51 * - IXGBE_ERROR_INVALID_STATE 52 * This category is for errors which represent a serious failure state that is 53 * unexpected, and could be potentially harmful to device operation. It should 54 * not be used for errors relating to issues that can be worked around or 55 * ignored. 56 * 57 * - IXGBE_ERROR_POLLING 58 * This category is for errors related to polling/timeout issues and should be 59 * used in any case where the timeout occurred, or a failure to obtain a lock, or 60 * failure to receive data within the time limit. 61 * 62 * - IXGBE_ERROR_CAUTION 63 * This category should be used for reporting issues that may be the cause of 64 * other errors, such as temperature warnings. It should indicate an event which 65 * could be serious, but hasn't necessarily caused problems yet. 66 * 67 * - IXGBE_ERROR_SOFTWARE 68 * This category is intended for errors due to software state preventing 69 * something. The category is not intended for errors due to bad arguments, or 70 * due to unsupported features. It should be used when a state occurs which 71 * prevents action but is not a serious issue. 72 * 73 * - IXGBE_ERROR_ARGUMENT 74 * This category is for when a bad or invalid argument is passed. It should be 75 * used whenever a function is called and error checking has detected the 76 * argument is wrong or incorrect. 77 * 78 * - IXGBE_ERROR_UNSUPPORTED 79 * This category is for errors which are due to unsupported circumstances or 80 * configuration issues. It should not be used when the issue is due to an 81 * invalid argument, but for when something has occurred that is unsupported 82 * (Ex: Flow control autonegotiation or an unsupported SFP+ module.) 83 */ 84 85 #include "ixgbe_osdep.h" 86 87 /* Override this by setting IOMEM in your ixgbe_osdep.h header */ 88 #define IOMEM 89 90 /* Vendor ID */ 91 #define IXGBE_INTEL_VENDOR_ID 0x8086 92 93 /* Device IDs */ 94 #define IXGBE_DEV_ID_82598 0x10B6 95 #define IXGBE_DEV_ID_82598_BX 0x1508 96 #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6 97 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 98 #define IXGBE_DEV_ID_82598AT 0x10C8 99 #define IXGBE_DEV_ID_82598AT2 0x150B 100 #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB 101 #define IXGBE_DEV_ID_82598EB_CX4 0x10DD 102 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC 103 #define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1 104 #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1 105 #define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4 106 #define IXGBE_DEV_ID_82599_KX4 PCI_PRODUCT_INTEL_82599_KX4 107 #define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514 108 #define IXGBE_DEV_ID_82599_KR 0x1517 109 #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE PCI_PRODUCT_INTEL_82599_COMBO_BACKPLANE 110 #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C 111 #define IXGBE_DEV_ID_82599_LS 0x154F 112 #define IXGBE_DEV_ID_82599_CX4 PCI_PRODUCT_INTEL_82599_CX4 113 #define IXGBE_DEV_ID_82599_SFP PCI_PRODUCT_INTEL_82599_SFP 114 #define IXGBE_SUBDEV_ID_82599_SFP_WOL0 0x1071 115 #define IXGBE_SUBDEV_ID_82599_SFP 0x11A9 116 #define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72 117 #define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0 118 #define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470 119 #define IXGBE_SUBDEV_ID_82599_SP_560FLR 0x211B 120 #define IXGBE_SUBDEV_ID_82599_LOM_SNAP6 0x2159 121 #define IXGBE_SUBDEV_ID_82599_SFP_1OCP 0x000D 122 #define IXGBE_SUBDEV_ID_82599_SFP_2OCP 0x0008 123 #define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1 0x8976 124 #define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2 0x06EE 125 #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A 126 #define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529 127 #define IXGBE_DEV_ID_82599_SFP_EM 0x1507 128 #define IXGBE_DEV_ID_82599_SFP_SF2 0x154D 129 #define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A 130 #define IXGBE_DEV_ID_82599_QSFP_SF_QP 0x1558 131 #define IXGBE_DEV_ID_82599EN_SFP 0x1557 132 #define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001 133 #define IXGBE_DEV_ID_82599_XAUI_LOM PCI_PRODUCT_INTEL_82599_XAUI_LOM 134 #define IXGBE_DEV_ID_82599_T3_LOM 0x151C 135 #define IXGBE_DEV_ID_82599_VF 0x10ED 136 #define IXGBE_DEV_ID_82599_VF_HV 0x152E 137 #define IXGBE_DEV_ID_82599_BYPASS 0x155D 138 #define IXGBE_DEV_ID_X540T 0x1528 139 #define IXGBE_DEV_ID_X540_VF 0x1515 140 #define IXGBE_DEV_ID_X540_VF_HV 0x1530 141 #define IXGBE_DEV_ID_X540_BYPASS 0x155C 142 #define IXGBE_DEV_ID_X540T1 0x1560 143 #define IXGBE_DEV_ID_X550T 0x1563 144 #define IXGBE_DEV_ID_X550T1 0x15D1 145 #define IXGBE_DEV_ID_X550EM_A_KR 0x15C2 146 #define IXGBE_DEV_ID_X550EM_A_KR_L 0x15C3 147 #define IXGBE_DEV_ID_X550EM_A_SFP_N 0x15C4 148 #define IXGBE_DEV_ID_X550EM_A_SGMII 0x15C6 149 #define IXGBE_DEV_ID_X550EM_A_SGMII_L 0x15C7 150 #define IXGBE_DEV_ID_X550EM_A_10G_T 0x15C8 151 #define IXGBE_DEV_ID_X550EM_A_QSFP 0x15CA 152 #define IXGBE_DEV_ID_X550EM_A_QSFP_N 0x15CC 153 #define IXGBE_DEV_ID_X550EM_A_SFP 0x15CE 154 #define IXGBE_DEV_ID_X550EM_A_1G_T 0x15E4 155 #define IXGBE_DEV_ID_X550EM_A_1G_T_L 0x15E5 156 #define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA 157 #define IXGBE_DEV_ID_X550EM_X_KR 0x15AB 158 #define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC 159 #define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD 160 #define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE 161 #define IXGBE_DEV_ID_X550EM_X_XFI 0x15B0 162 #define IXGBE_DEV_ID_X550_VF_HV 0x1564 163 #define IXGBE_DEV_ID_X550_VF 0x1565 164 #define IXGBE_DEV_ID_X550EM_A_VF 0x15C5 165 #define IXGBE_DEV_ID_X550EM_A_VF_HV 0x15B4 166 #define IXGBE_DEV_ID_X550EM_X_VF 0x15A8 167 #define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9 168 169 #define IXGBE_CAT(r,m) IXGBE_##r##m 170 171 #define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, _IDX)]) 172 173 /* General Registers */ 174 #define IXGBE_CTRL 0x00000 175 #define IXGBE_STATUS 0x00008 176 #define IXGBE_CTRL_EXT 0x00018 177 #define IXGBE_ESDP 0x00020 178 #define IXGBE_EODSDP 0x00028 179 #define IXGBE_I2CCTL_82599 0x00028 180 #define IXGBE_I2CCTL IXGBE_I2CCTL_82599 181 #define IXGBE_I2CCTL_X540 IXGBE_I2CCTL_82599 182 #define IXGBE_I2CCTL_X550 0x15F5C 183 #define IXGBE_I2CCTL_X550EM_x IXGBE_I2CCTL_X550 184 #define IXGBE_I2CCTL_X550EM_a IXGBE_I2CCTL_X550 185 #define IXGBE_I2CCTL_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2CCTL) 186 #define IXGBE_PHY_GPIO 0x00028 187 #define IXGBE_MAC_GPIO 0x00030 188 #define IXGBE_PHYINT_STATUS0 0x00100 189 #define IXGBE_PHYINT_STATUS1 0x00104 190 #define IXGBE_PHYINT_STATUS2 0x00108 191 #define IXGBE_LEDCTL 0x00200 192 #define IXGBE_FRTIMER 0x00048 193 #define IXGBE_TCPTIMER 0x0004C 194 #define IXGBE_CORESPARE 0x00600 195 #define IXGBE_EXVET 0x05078 196 197 /* NVM Registers */ 198 #define IXGBE_EEC 0x10010 199 #define IXGBE_EEC_X540 IXGBE_EEC 200 #define IXGBE_EEC_X550 IXGBE_EEC 201 #define IXGBE_EEC_X550EM_x IXGBE_EEC 202 #define IXGBE_EEC_X550EM_a 0x15FF8 203 #define IXGBE_EEC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EEC) 204 205 #define IXGBE_EERD 0x10014 206 #define IXGBE_EEWR 0x10018 207 208 #define IXGBE_FLA 0x1001C 209 #define IXGBE_FLA_X540 IXGBE_FLA 210 #define IXGBE_FLA_X550 IXGBE_FLA 211 #define IXGBE_FLA_X550EM_x IXGBE_FLA 212 #define IXGBE_FLA_X550EM_a 0x15F68 213 #define IXGBE_FLA_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FLA) 214 #define IXGBE_FLA_FL_SIZE_SHIFT_X540 17 215 #define IXGBE_FLA_FL_SIZE_SHIFT_X550 12 216 #define IXGBE_FLA_FL_SIZE_MASK_X540 (0x7 << IXGBE_FLA_FL_SIZE_SHIFT_X540) 217 #define IXGBE_FLA_FL_SIZE_MASK_X550 (0x7 << IXGBE_FLA_FL_SIZE_SHIFT_X550) 218 219 #define IXGBE_EEMNGCTL 0x10110 220 #define IXGBE_EEMNGDATA 0x10114 221 #define IXGBE_FLMNGCTL 0x10118 222 #define IXGBE_FLMNGDATA 0x1011C 223 #define IXGBE_FLMNGCNT 0x10120 224 #define IXGBE_FLOP 0x1013C 225 226 #define IXGBE_GRC 0x10200 227 #define IXGBE_GRC_X540 IXGBE_GRC 228 #define IXGBE_GRC_X550 IXGBE_GRC 229 #define IXGBE_GRC_X550EM_x IXGBE_GRC 230 #define IXGBE_GRC_X550EM_a 0x15F64 231 #define IXGBE_GRC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), GRC) 232 233 #define IXGBE_SRAMREL 0x10210 234 #define IXGBE_SRAMREL_X540 IXGBE_SRAMREL 235 #define IXGBE_SRAMREL_X550 IXGBE_SRAMREL 236 #define IXGBE_SRAMREL_X550EM_x IXGBE_SRAMREL 237 #define IXGBE_SRAMREL_X550EM_a 0x15F6C 238 #define IXGBE_SRAMREL_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SRAMREL) 239 240 #define IXGBE_PHYDBG 0x10218 241 242 /* General Receive Control */ 243 #define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */ 244 #define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */ 245 246 #define IXGBE_VPDDIAG0 0x10204 247 #define IXGBE_VPDDIAG1 0x10208 248 249 /* I2CCTL Bit Masks */ 250 #define IXGBE_I2C_CLK_IN 0x00000001 251 #define IXGBE_I2C_CLK_IN_X540 IXGBE_I2C_CLK_IN 252 #define IXGBE_I2C_CLK_IN_X550 0x00004000 253 #define IXGBE_I2C_CLK_IN_X550EM_x IXGBE_I2C_CLK_IN_X550 254 #define IXGBE_I2C_CLK_IN_X550EM_a IXGBE_I2C_CLK_IN_X550 255 #define IXGBE_I2C_CLK_IN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_IN) 256 257 #define IXGBE_I2C_CLK_OUT 0x00000002 258 #define IXGBE_I2C_CLK_OUT_X540 IXGBE_I2C_CLK_OUT 259 #define IXGBE_I2C_CLK_OUT_X550 0x00000200 260 #define IXGBE_I2C_CLK_OUT_X550EM_x IXGBE_I2C_CLK_OUT_X550 261 #define IXGBE_I2C_CLK_OUT_X550EM_a IXGBE_I2C_CLK_OUT_X550 262 #define IXGBE_I2C_CLK_OUT_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OUT) 263 264 #define IXGBE_I2C_DATA_IN 0x00000004 265 #define IXGBE_I2C_DATA_IN_X540 IXGBE_I2C_DATA_IN 266 #define IXGBE_I2C_DATA_IN_X550 0x00001000 267 #define IXGBE_I2C_DATA_IN_X550EM_x IXGBE_I2C_DATA_IN_X550 268 #define IXGBE_I2C_DATA_IN_X550EM_a IXGBE_I2C_DATA_IN_X550 269 #define IXGBE_I2C_DATA_IN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_IN) 270 271 #define IXGBE_I2C_DATA_OUT 0x00000008 272 #define IXGBE_I2C_DATA_OUT_X540 IXGBE_I2C_DATA_OUT 273 #define IXGBE_I2C_DATA_OUT_X550 0x00000400 274 #define IXGBE_I2C_DATA_OUT_X550EM_x IXGBE_I2C_DATA_OUT_X550 275 #define IXGBE_I2C_DATA_OUT_X550EM_a IXGBE_I2C_DATA_OUT_X550 276 #define IXGBE_I2C_DATA_OUT_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OUT) 277 278 #define IXGBE_I2C_DATA_OE_N_EN 0 279 #define IXGBE_I2C_DATA_OE_N_EN_X540 IXGBE_I2C_DATA_OE_N_EN 280 #define IXGBE_I2C_DATA_OE_N_EN_X550 0x00000800 281 #define IXGBE_I2C_DATA_OE_N_EN_X550EM_x IXGBE_I2C_DATA_OE_N_EN_X550 282 #define IXGBE_I2C_DATA_OE_N_EN_X550EM_a IXGBE_I2C_DATA_OE_N_EN_X550 283 #define IXGBE_I2C_DATA_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN) 284 285 #define IXGBE_I2C_BB_EN 0 286 #define IXGBE_I2C_BB_EN_X540 IXGBE_I2C_BB_EN 287 #define IXGBE_I2C_BB_EN_X550 0x00000100 288 #define IXGBE_I2C_BB_EN_X550EM_x IXGBE_I2C_BB_EN_X550 289 #define IXGBE_I2C_BB_EN_X550EM_a IXGBE_I2C_BB_EN_X550 290 #define IXGBE_I2C_BB_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_BB_EN) 291 292 #define IXGBE_I2C_CLK_OE_N_EN 0 293 #define IXGBE_I2C_CLK_OE_N_EN_X540 IXGBE_I2C_CLK_OE_N_EN 294 #define IXGBE_I2C_CLK_OE_N_EN_X550 0x00002000 295 #define IXGBE_I2C_CLK_OE_N_EN_X550EM_x IXGBE_I2C_CLK_OE_N_EN_X550 296 #define IXGBE_I2C_CLK_OE_N_EN_X550EM_a IXGBE_I2C_CLK_OE_N_EN_X550 297 #define IXGBE_I2C_CLK_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN) 298 #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500 299 300 301 302 #define NVM_OROM_OFFSET 0x17 303 #define NVM_OROM_BLK_LOW 0x83 304 #define NVM_OROM_BLK_HI 0x84 305 #define NVM_OROM_PATCH_MASK 0xFF 306 #define NVM_OROM_SHIFT 8 307 308 #define NVM_VER_MASK 0x00FF /* version mask */ 309 #define NVM_VER_SHIFT 8 /* version bit shift */ 310 #define NVM_OEM_PROD_VER_PTR 0x1B /* OEM Product version block pointer */ 311 #define NVM_OEM_PROD_VER_CAP_OFF 0x1 /* OEM Product version format offset */ 312 #define NVM_OEM_PROD_VER_OFF_L 0x2 /* OEM Product version offset low */ 313 #define NVM_OEM_PROD_VER_OFF_H 0x3 /* OEM Product version offset high */ 314 #define NVM_OEM_PROD_VER_CAP_MASK 0xF /* OEM Product version cap mask */ 315 #define NVM_OEM_PROD_VER_MOD_LEN 0x3 /* OEM Product version module length */ 316 #define NVM_ETK_OFF_LOW 0x2D /* version low order word */ 317 #define NVM_ETK_OFF_HI 0x2E /* version high order word */ 318 #define NVM_ETK_SHIFT 16 /* high version word shift */ 319 #define NVM_VER_INVALID 0xFFFF 320 #define NVM_ETK_VALID 0x8000 321 #define NVM_INVALID_PTR 0xFFFF 322 #define NVM_VER_SIZE 32 /* version sting size */ 323 324 struct ixgbe_nvm_version { 325 u32 etk_id; 326 u8 nvm_major; 327 u16 nvm_minor; 328 u8 nvm_id; 329 330 bool oem_valid; 331 u8 oem_major; 332 u8 oem_minor; 333 u16 oem_release; 334 335 bool or_valid; 336 u8 or_major; 337 u16 or_build; 338 u8 or_patch; 339 340 }; 341 342 /* Interrupt Registers */ 343 #define IXGBE_EICR 0x00800 344 #define IXGBE_EICS 0x00808 345 #define IXGBE_EIMS 0x00880 346 #define IXGBE_EIMC 0x00888 347 #define IXGBE_EIAC 0x00810 348 #define IXGBE_EIAM 0x00890 349 #define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4) 350 #define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4) 351 #define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4) 352 #define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4) 353 /* 82599 EITR is only 12 bits, with the lower 3 always zero */ 354 /* 355 * 82598 EITR is 16 bits but set the limits based on the max 356 * supported by all ixgbe hardware 357 */ 358 #define IXGBE_MAX_INT_RATE 488281 359 #define IXGBE_MIN_INT_RATE 956 360 /* On 82599 and newer, minimum RSC_DELAY is 4us. ITR interval must be larger 361 * than RSC_DELAY if RSC is used. ITR_INTERVAL is in 2(.048) us units on 10G 362 * and 1G. The minimum EITR is 6us. 363 */ 364 #define IXGBE_MIN_RSC_EITR_10G1G 0x00000018 365 #define IXGBE_MAX_EITR 0x00000FF8 366 #define IXGBE_MIN_EITR 8 367 #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \ 368 (0x012300 + (((_i) - 24) * 4))) 369 #define IXGBE_EITR_ITR_INT_MASK 0x00000FF8 370 #define IXGBE_EITR_LLI_MOD 0x00008000 371 #define IXGBE_EITR_CNT_WDIS 0x80000000 372 #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ 373 #define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */ 374 #define IXGBE_EITRSEL 0x00894 375 #define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */ 376 #define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */ 377 #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4))) 378 #define IXGBE_GPIE 0x00898 379 380 /* Flow Control Registers */ 381 #define IXGBE_FCADBUL 0x03210 382 #define IXGBE_FCADBUH 0x03214 383 #define IXGBE_FCAMACL 0x04328 384 #define IXGBE_FCAMACH 0x0432C 385 #define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */ 386 #define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */ 387 #define IXGBE_PFCTOP 0x03008 388 #define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */ 389 #define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */ 390 #define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */ 391 #define IXGBE_FCRTV 0x032A0 392 #define IXGBE_FCCFG 0x03D00 393 #define IXGBE_TFCS 0x0CE00 394 395 /* Receive DMA Registers */ 396 #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \ 397 (0x0D000 + (((_i) - 64) * 0x40))) 398 #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \ 399 (0x0D004 + (((_i) - 64) * 0x40))) 400 #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \ 401 (0x0D008 + (((_i) - 64) * 0x40))) 402 #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \ 403 (0x0D010 + (((_i) - 64) * 0x40))) 404 #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \ 405 (0x0D018 + (((_i) - 64) * 0x40))) 406 #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \ 407 (0x0D028 + (((_i) - 64) * 0x40))) 408 #define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \ 409 (0x0D02C + (((_i) - 64) * 0x40))) 410 #define IXGBE_RSCDBU 0x03028 411 #define IXGBE_RDDCC 0x02F20 412 #define IXGBE_RXMEMWRAP 0x03190 413 #define IXGBE_STARCTRL 0x03024 414 /* 415 * Split and Replication Receive Control Registers 416 * 00-15 : 0x02100 + n*4 417 * 16-64 : 0x01014 + n*0x40 418 * 64-127: 0x0D014 + (n-64)*0x40 419 */ 420 #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \ 421 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \ 422 (0x0D014 + (((_i) - 64) * 0x40)))) 423 /* 424 * Rx DCA Control Register: 425 * 00-15 : 0x02200 + n*4 426 * 16-64 : 0x0100C + n*0x40 427 * 64-127: 0x0D00C + (n-64)*0x40 428 */ 429 #define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \ 430 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \ 431 (0x0D00C + (((_i) - 64) * 0x40)))) 432 #define IXGBE_RDRXCTL 0x02F00 433 /* 8 of these 0x03C00 - 0x03C1C */ 434 #define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) 435 #define IXGBE_RXCTRL 0x03000 436 #define IXGBE_DROPEN 0x03D04 437 #define IXGBE_RXPBSIZE_SHIFT 10 438 #define IXGBE_RXPBSIZE_MASK 0x000FFC00 439 440 /* Receive Registers */ 441 #define IXGBE_RXCSUM 0x05000 442 #define IXGBE_RFCTL 0x05008 443 #define IXGBE_DRECCCTL 0x02F08 444 #define IXGBE_DRECCCTL_DISABLE 0 445 #define IXGBE_DRECCCTL2 0x02F8C 446 447 /* Multicast Table Array - 128 entries */ 448 #define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) 449 #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ 450 (0x0A200 + ((_i) * 8))) 451 #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ 452 (0x0A204 + ((_i) * 8))) 453 #define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8)) 454 #define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8)) 455 /* Packet split receive type */ 456 #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \ 457 (0x0EA00 + ((_i) * 4))) 458 /* array of 4096 1-bit vlan filters */ 459 #define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) 460 /*array of 4096 4-bit vlan vmdq indices */ 461 #define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4)) 462 #define IXGBE_FCTRL 0x05080 463 #define IXGBE_VLNCTRL 0x05088 464 #define IXGBE_MCSTCTRL 0x05090 465 #define IXGBE_MRQC 0x05818 466 #define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */ 467 #define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */ 468 #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */ 469 #define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */ 470 #define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */ 471 #define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */ 472 #define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */ 473 #define IXGBE_RQTC 0x0EC70 474 #define IXGBE_MTQC 0x08120 475 #define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */ 476 #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */ 477 #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */ 478 #define IXGBE_PFFLPL 0x050B0 479 #define IXGBE_PFFLPH 0x050B4 480 #define IXGBE_VT_CTL 0x051B0 481 #define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */ 482 /* 64 Mailboxes, 16 DW each */ 483 #define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i))) 484 #define IXGBE_PFMBICR_INDEX(_i) ((_i) >> 4) 485 #define IXGBE_PFMBICR_SHIFT(_i) ((_i) % 16) 486 #define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */ 487 #define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i))) /* 4 total */ 488 #define IXGBE_PFVFLRE(_i) ((((_i) & 1) ? 0x001C0 : 0x00600)) 489 #define IXGBE_PFVFLREC(_i) (0x00700 + ((_i) * 4)) 490 #define IXGBE_PFVFLRE_INDEX(_i) ((_i) >> 5) 491 #define IXGBE_PFVFLRE_SHIFT(_i) ((_i) % 32) 492 #define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4)) 493 #define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4)) 494 #define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4)) 495 #define IXGBE_QDE 0x2F04 496 #define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4)) /* 2 total */ 497 #define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */ 498 #define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4)) 499 #define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4)) 500 #define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4)) 501 #define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4)) 502 #define IXGBE_LVMMC_RX 0x2FA8 503 #define IXGBE_LVMMC_TX 0x8108 504 #define IXGBE_LMVM_RX 0x2FA4 505 #define IXGBE_LMVM_TX 0x8124 506 #define IXGBE_WQBR_RX(_i) (0x2FB0 + ((_i) * 4)) /* 4 total */ 507 #define IXGBE_WQBR_TX(_i) (0x8130 + ((_i) * 4)) /* 4 total */ 508 #define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/ 509 #define IXGBE_RXFECCERR0 0x051B8 510 #define IXGBE_LLITHRESH 0x0EC90 511 #define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */ 512 #define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */ 513 #define IXGBE_IMIRVP 0x05AC0 514 #define IXGBE_VMD_CTL 0x0581C 515 #define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */ 516 #define IXGBE_ERETA(_i) (0x0EE80 + ((_i) * 4)) /* 96 of these (0-95) */ 517 #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */ 518 519 /* Registers for setting up RSS on X550 with SRIOV 520 * _p - pool number (0..63) 521 * _i - index (0..10 for PFVFRSSRK, 0..15 for PFVFRETA) 522 */ 523 #define IXGBE_PFVFMRQC(_p) (0x03400 + ((_p) * 4)) 524 #define IXGBE_PFVFRSSRK(_i, _p) (0x018000 + ((_i) * 4) + ((_p) * 0x40)) 525 #define IXGBE_PFVFRETA(_i, _p) (0x019000 + ((_i) * 4) + ((_p) * 0x40)) 526 527 /* Flow Director registers */ 528 #define IXGBE_FDIRCTRL 0x0EE00 529 #define IXGBE_FDIRHKEY 0x0EE68 530 #define IXGBE_FDIRSKEY 0x0EE6C 531 #define IXGBE_FDIRDIP4M 0x0EE3C 532 #define IXGBE_FDIRSIP4M 0x0EE40 533 #define IXGBE_FDIRTCPM 0x0EE44 534 #define IXGBE_FDIRUDPM 0x0EE48 535 #define IXGBE_FDIRSCTPM 0x0EE78 536 #define IXGBE_FDIRIP6M 0x0EE74 537 #define IXGBE_FDIRM 0x0EE70 538 539 /* Flow Director Stats registers */ 540 #define IXGBE_FDIRFREE 0x0EE38 541 #define IXGBE_FDIRLEN 0x0EE4C 542 #define IXGBE_FDIRUSTAT 0x0EE50 543 #define IXGBE_FDIRFSTAT 0x0EE54 544 #define IXGBE_FDIRMATCH 0x0EE58 545 #define IXGBE_FDIRMISS 0x0EE5C 546 547 /* Flow Director Programming registers */ 548 #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */ 549 #define IXGBE_FDIRIPSA 0x0EE18 550 #define IXGBE_FDIRIPDA 0x0EE1C 551 #define IXGBE_FDIRPORT 0x0EE20 552 #define IXGBE_FDIRVLAN 0x0EE24 553 #define IXGBE_FDIRHASH 0x0EE28 554 #define IXGBE_FDIRCMD 0x0EE2C 555 556 /* Transmit DMA registers */ 557 #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of them (0-31)*/ 558 #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) 559 #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40)) 560 #define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40)) 561 #define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40)) 562 #define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40)) 563 #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40)) 564 #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) 565 #define IXGBE_DTXCTL 0x07E00 566 567 #define IXGBE_DMATXCTL 0x04A80 568 #define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */ 569 #define IXGBE_PFDTXGSWC 0x08220 570 #define IXGBE_DTXMXSZRQ 0x08100 571 #define IXGBE_DTXTCPFLGL 0x04A88 572 #define IXGBE_DTXTCPFLGH 0x04A8C 573 #define IXGBE_LBDRPEN 0x0CA00 574 #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */ 575 576 #define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */ 577 #define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */ 578 #define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */ 579 #define IXGBE_DMATXCTL_MDP_EN 0x20 /* Bit 5 */ 580 #define IXGBE_DMATXCTL_MBINTEN 0x40 /* Bit 6 */ 581 #define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */ 582 583 #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */ 584 585 /* Anti-spoofing defines */ 586 #define IXGBE_SPOOF_MACAS_MASK 0xFF 587 #define IXGBE_SPOOF_VLANAS_MASK 0xFF00 588 #define IXGBE_SPOOF_VLANAS_SHIFT 8 589 #define IXGBE_SPOOF_ETHERTYPEAS 0xFF000000 590 #define IXGBE_SPOOF_ETHERTYPEAS_SHIFT 16 591 #define IXGBE_PFVFSPOOF_REG_COUNT 8 592 /* 16 of these (0-15) */ 593 #define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) 594 /* Tx DCA Control register : 128 of these (0-127) */ 595 #define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40)) 596 #define IXGBE_TIPG 0x0CB00 597 #define IXGBE_TIPG_IPGT_MASK 0x000000FF 598 #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */ 599 #define IXGBE_MNGTXMAP 0x0CD10 600 #define IXGBE_TIPG_FIBER_DEFAULT 3 601 #define IXGBE_TXPBSIZE_SHIFT 10 602 603 /* Wake up registers */ 604 #define IXGBE_WUC 0x05800 605 #define IXGBE_WUFC 0x05808 606 #define IXGBE_WUS 0x05810 607 #define IXGBE_IPAV 0x05838 608 #define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */ 609 #define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */ 610 611 #define IXGBE_WUPL 0x05900 612 #define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ 613 #define IXGBE_PROXYS 0x05F60 /* Proxying Status Register */ 614 #define IXGBE_PROXYFC 0x05F64 /* Proxying Filter Control Register */ 615 #define IXGBE_VXLANCTRL 0x0000507C /* Rx filter VXLAN UDPPORT Register */ 616 617 /* masks for accessing VXLAN and GENEVE UDP ports */ 618 #define IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK 0x0000ffff /* VXLAN port */ 619 #define IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK 0xffff0000 /* GENEVE port */ 620 #define IXGBE_VXLANCTRL_ALL_UDPPORT_MASK 0xffffffff /* GENEVE/VXLAN */ 621 #define IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT 16 622 623 #define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */ 624 /* Ext Flexible Host Filter Table */ 625 #define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100)) 626 #define IXGBE_FHFT_EXT_X550(_n) (0x09600 + ((_n) * 0x100)) 627 628 /* Four Flexible Filters are supported */ 629 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4 630 /* Six Flexible Filters are supported */ 631 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_6 6 632 /* Eight Flexible Filters are supported */ 633 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_8 8 634 #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 635 636 /* Each Flexible Filter is at most 128 (0x80) bytes in length */ 637 #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128 638 #define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */ 639 #define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */ 640 641 /* Definitions for power management and wakeup registers */ 642 /* Wake Up Control */ 643 #define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */ 644 #define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */ 645 #define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */ 646 647 /* Wake Up Filter Control */ 648 #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 649 #define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 650 #define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 651 #define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 652 #define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 653 #define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 654 #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 655 #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 656 #define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */ 657 658 #define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ 659 #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 660 #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 661 #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 662 #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 663 #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */ 664 #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */ 665 #define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */ 666 #define IXGBE_WUFC_FLX_FILTERS_6 0x003F0000 /* Mask for 6 flex filters */ 667 #define IXGBE_WUFC_FLX_FILTERS_8 0x00FF0000 /* Mask for 8 flex filters */ 668 #define IXGBE_WUFC_FW_RST_WK 0x80000000 /* Ena wake on FW reset assertion */ 669 /* Mask for Ext. flex filters */ 670 #define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 671 #define IXGBE_WUFC_ALL_FILTERS 0x000F00FF /* Mask all 4 flex filters */ 672 #define IXGBE_WUFC_ALL_FILTERS_6 0x003F00FF /* Mask all 6 flex filters */ 673 #define IXGBE_WUFC_ALL_FILTERS_8 0x00FF00FF /* Mask all 8 flex filters */ 674 #define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 675 676 /* Wake Up Status */ 677 #define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC 678 #define IXGBE_WUS_MAG IXGBE_WUFC_MAG 679 #define IXGBE_WUS_EX IXGBE_WUFC_EX 680 #define IXGBE_WUS_MC IXGBE_WUFC_MC 681 #define IXGBE_WUS_BC IXGBE_WUFC_BC 682 #define IXGBE_WUS_ARP IXGBE_WUFC_ARP 683 #define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4 684 #define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6 685 #define IXGBE_WUS_MNG IXGBE_WUFC_MNG 686 #define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0 687 #define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1 688 #define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2 689 #define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3 690 #define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4 691 #define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5 692 #define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS 693 #define IXGBE_WUS_FW_RST_WK IXGBE_WUFC_FW_RST_WK 694 /* Proxy Status */ 695 #define IXGBE_PROXYS_EX 0x00000004 /* Exact packet received */ 696 #define IXGBE_PROXYS_ARP_DIR 0x00000020 /* ARP w/filter match received */ 697 #define IXGBE_PROXYS_NS 0x00000200 /* IPV6 NS received */ 698 #define IXGBE_PROXYS_NS_DIR 0x00000400 /* IPV6 NS w/DA match received */ 699 #define IXGBE_PROXYS_ARP 0x00000800 /* ARP request packet received */ 700 #define IXGBE_PROXYS_MLD 0x00001000 /* IPv6 MLD packet received */ 701 702 /* Proxying Filter Control */ 703 #define IXGBE_PROXYFC_ENABLE 0x00000001 /* Port Proxying Enable */ 704 #define IXGBE_PROXYFC_EX 0x00000004 /* Directed Exact Proxy Enable */ 705 #define IXGBE_PROXYFC_ARP_DIR 0x00000020 /* Directed ARP Proxy Enable */ 706 #define IXGBE_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */ 707 #define IXGBE_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Enable */ 708 #define IXGBE_PROXYFC_MLD 0x00000800 /* IPv6 MLD Proxy Enable */ 709 #define IXGBE_PROXYFC_NO_TCO 0x00008000 /* Ignore TCO packets */ 710 711 #define IXGBE_WUPL_LENGTH_MASK 0xFFFF 712 713 /* DCB registers */ 714 #define IXGBE_DCB_MAX_TRAFFIC_CLASS 8 715 #define IXGBE_RMCS 0x03D00 716 #define IXGBE_DPMCS 0x07F40 717 #define IXGBE_PDPMCS 0x0CD00 718 #define IXGBE_RUPPBMR 0x050A0 719 #define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */ 720 #define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */ 721 #define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */ 722 #define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */ 723 #define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 724 #define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 725 726 /* Power Management */ 727 /* DMA Coalescing configuration */ 728 struct ixgbe_dmac_config { 729 u16 watchdog_timer; /* usec units */ 730 bool fcoe_en; 731 u32 link_speed; 732 u8 fcoe_tc; 733 u8 num_tcs; 734 }; 735 736 /* 737 * DMA Coalescing threshold Rx PB TC[n] value in Kilobyte by link speed. 738 * DMACRXT = 10Gbps = 10,000 bits / usec = 1250 bytes / usec 70 * 1250 == 739 * 87500 bytes [85KB] 740 */ 741 #define IXGBE_DMACRXT_10G 0x55 742 #define IXGBE_DMACRXT_1G 0x09 743 #define IXGBE_DMACRXT_100M 0x01 744 745 /* DMA Coalescing registers */ 746 #define IXGBE_DMCMNGTH 0x15F20 /* Management Threshold */ 747 #define IXGBE_DMACR 0x02400 /* Control register */ 748 #define IXGBE_DMCTH(_i) (0x03300 + ((_i) * 4)) /* 8 of these */ 749 #define IXGBE_DMCTLX 0x02404 /* Time to Lx request */ 750 /* DMA Coalescing register fields */ 751 #define IXGBE_DMCMNGTH_DMCMNGTH_MASK 0x000FFFF0 /* Mng Threshold mask */ 752 #define IXGBE_DMCMNGTH_DMCMNGTH_SHIFT 4 /* Management Threshold shift */ 753 #define IXGBE_DMACR_DMACWT_MASK 0x0000FFFF /* Watchdog Timer mask */ 754 #define IXGBE_DMACR_HIGH_PRI_TC_MASK 0x00FF0000 755 #define IXGBE_DMACR_HIGH_PRI_TC_SHIFT 16 756 #define IXGBE_DMACR_EN_MNG_IND 0x10000000 /* Enable Mng Indications */ 757 #define IXGBE_DMACR_LX_COAL_IND 0x40000000 /* Lx Coalescing indicate */ 758 #define IXGBE_DMACR_DMAC_EN 0x80000000 /* DMA Coalescing Enable */ 759 #define IXGBE_DMCTH_DMACRXT_MASK 0x000001FF /* Receive Threshold mask */ 760 #define IXGBE_DMCTLX_TTLX_MASK 0x00000FFF /* Time to Lx request mask */ 761 762 /* EEE registers */ 763 #define IXGBE_EEER 0x043A0 /* EEE register */ 764 #define IXGBE_EEE_STAT 0x04398 /* EEE Status */ 765 #define IXGBE_EEE_SU 0x04380 /* EEE Set up */ 766 #define IXGBE_EEE_SU_TEEE_DLY_SHIFT 26 767 #define IXGBE_TLPIC 0x041F4 /* EEE Tx LPI count */ 768 #define IXGBE_RLPIC 0x041F8 /* EEE Rx LPI count */ 769 770 /* EEE register fields */ 771 #define IXGBE_EEER_TX_LPI_EN 0x00010000 /* Enable EEE LPI TX path */ 772 #define IXGBE_EEER_RX_LPI_EN 0x00020000 /* Enable EEE LPI RX path */ 773 #define IXGBE_EEE_STAT_NEG 0x20000000 /* EEE support neg on link */ 774 #define IXGBE_EEE_RX_LPI_STATUS 0x40000000 /* RX Link in LPI status */ 775 #define IXGBE_EEE_TX_LPI_STATUS 0x80000000 /* TX Link in LPI status */ 776 777 /* Security Control Registers */ 778 #define IXGBE_SECTXCTRL 0x08800 779 #define IXGBE_SECTXSTAT 0x08804 780 #define IXGBE_SECTXBUFFAF 0x08808 781 #define IXGBE_SECTXMINIFG 0x08810 782 #define IXGBE_SECRXCTRL 0x08D00 783 #define IXGBE_SECRXSTAT 0x08D04 784 785 /* Security Bit Fields and Masks */ 786 #define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001 787 #define IXGBE_SECTXCTRL_TX_DIS 0x00000002 788 #define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004 789 790 #define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001 791 #define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002 792 793 #define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001 794 #define IXGBE_SECRXCTRL_RX_DIS 0x00000002 795 796 #define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001 797 #define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002 798 799 /* LinkSec (MacSec) Registers */ 800 #define IXGBE_LSECTXCAP 0x08A00 801 #define IXGBE_LSECRXCAP 0x08F00 802 #define IXGBE_LSECTXCTRL 0x08A04 803 #define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */ 804 #define IXGBE_LSECTXSCH 0x08A0C /* SCI High */ 805 #define IXGBE_LSECTXSA 0x08A10 806 #define IXGBE_LSECTXPN0 0x08A14 807 #define IXGBE_LSECTXPN1 0x08A18 808 #define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */ 809 #define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */ 810 #define IXGBE_LSECRXCTRL 0x08F04 811 #define IXGBE_LSECRXSCL 0x08F08 812 #define IXGBE_LSECRXSCH 0x08F0C 813 #define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */ 814 #define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */ 815 #define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m)))) 816 #define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */ 817 #define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */ 818 #define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */ 819 #define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */ 820 #define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */ 821 #define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */ 822 #define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */ 823 #define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */ 824 #define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */ 825 #define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */ 826 #define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */ 827 #define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */ 828 #define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */ 829 #define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */ 830 #define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */ 831 #define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */ 832 #define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */ 833 #define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */ 834 #define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */ 835 836 /* LinkSec (MacSec) Bit Fields and Masks */ 837 #define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000 838 #define IXGBE_LSECTXCAP_SUM_SHIFT 16 839 #define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000 840 #define IXGBE_LSECRXCAP_SUM_SHIFT 16 841 842 #define IXGBE_LSECTXCTRL_EN_MASK 0x00000003 843 #define IXGBE_LSECTXCTRL_DISABLE 0x0 844 #define IXGBE_LSECTXCTRL_AUTH 0x1 845 #define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2 846 #define IXGBE_LSECTXCTRL_AISCI 0x00000020 847 #define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 848 #define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8 849 850 #define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C 851 #define IXGBE_LSECRXCTRL_EN_SHIFT 2 852 #define IXGBE_LSECRXCTRL_DISABLE 0x0 853 #define IXGBE_LSECRXCTRL_CHECK 0x1 854 #define IXGBE_LSECRXCTRL_STRICT 0x2 855 #define IXGBE_LSECRXCTRL_DROP 0x3 856 #define IXGBE_LSECRXCTRL_PLSH 0x00000040 857 #define IXGBE_LSECRXCTRL_RP 0x00000080 858 #define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33 859 860 /* IpSec Registers */ 861 #define IXGBE_IPSTXIDX 0x08900 862 #define IXGBE_IPSTXSALT 0x08904 863 #define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */ 864 #define IXGBE_IPSRXIDX 0x08E00 865 #define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */ 866 #define IXGBE_IPSRXSPI 0x08E14 867 #define IXGBE_IPSRXIPIDX 0x08E18 868 #define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */ 869 #define IXGBE_IPSRXSALT 0x08E2C 870 #define IXGBE_IPSRXMOD 0x08E30 871 872 #define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4 873 874 /* DCB registers */ 875 #define IXGBE_RTRPCS 0x02430 876 #define IXGBE_RTTDCS 0x04900 877 #define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */ 878 #define IXGBE_RTTPCS 0x0CD00 879 #define IXGBE_RTRUP2TC 0x03020 880 #define IXGBE_RTTUP2TC 0x0C800 881 #define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */ 882 #define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */ 883 #define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */ 884 #define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */ 885 #define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */ 886 #define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 887 #define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 888 #define IXGBE_RTTDQSEL 0x04904 889 #define IXGBE_RTTDT1C 0x04908 890 #define IXGBE_RTTDT1S 0x0490C 891 #define IXGBE_RTTQCNCR 0x08B00 892 #define IXGBE_RTTQCNTG 0x04A90 893 #define IXGBE_RTTBCNRD 0x0498C 894 #define IXGBE_RTTQCNRR 0x0498C 895 #define IXGBE_RTTDTECC 0x04990 896 #define IXGBE_RTTDTECC_NO_BCN 0x00000100 897 898 #define IXGBE_RTTBCNRC 0x04984 899 #define IXGBE_RTTBCNRC_RS_ENA 0x80000000 900 #define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF 901 #define IXGBE_RTTBCNRC_RF_INT_SHIFT 14 902 #define IXGBE_RTTBCNRC_RF_INT_MASK \ 903 (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT) 904 #define IXGBE_RTTBCNRM 0x04980 905 #define IXGBE_RTTQCNRM 0x04980 906 907 /* BCN (for DCB) Registers */ 908 #define IXGBE_RTTBCNRS 0x04988 909 #define IXGBE_RTTBCNCR 0x08B00 910 #define IXGBE_RTTBCNACH 0x08B04 911 #define IXGBE_RTTBCNACL 0x08B08 912 #define IXGBE_RTTBCNTG 0x04A90 913 #define IXGBE_RTTBCNIDX 0x08B0C 914 #define IXGBE_RTTBCNCP 0x08B10 915 #define IXGBE_RTFRTIMER 0x08B14 916 #define IXGBE_RTTBCNRTT 0x05150 917 #define IXGBE_RTTBCNRD 0x0498C 918 919 /* FCoE DMA Context Registers */ 920 /* FCoE Direct DMA Context */ 921 #define IXGBE_FCDDC(_i, _j) (0x20000 + ((_i) * 0x4) + ((_j) * 0x10)) 922 #define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */ 923 #define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */ 924 #define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */ 925 #define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */ 926 #define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */ 927 #define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */ 928 #define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */ 929 #define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */ 930 #define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */ 931 #define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3 932 #define IXGBE_FCBUFF_BUFFCNT_SHIFT 8 933 #define IXGBE_FCBUFF_OFFSET_SHIFT 16 934 #define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */ 935 #define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */ 936 #define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */ 937 #define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */ 938 #define IXGBE_FCDMARW_LASTSIZE_SHIFT 16 939 /* FCoE SOF/EOF */ 940 #define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */ 941 #define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */ 942 #define IXGBE_REOFF 0x05158 /* Rx FC EOF */ 943 #define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */ 944 /* FCoE Filter Context Registers */ 945 #define IXGBE_FCD_ID 0x05114 /* FCoE D_ID */ 946 #define IXGBE_FCSMAC 0x0510C /* FCoE Source MAC */ 947 #define IXGBE_FCFLTRW_SMAC_HIGH_SHIFT 16 948 /* FCoE Direct Filter Context */ 949 #define IXGBE_FCDFC(_i, _j) (0x28000 + ((_i) * 0x4) + ((_j) * 0x10)) 950 #define IXGBE_FCDFCD(_i) (0x30000 + ((_i) * 0x4)) 951 #define IXGBE_FCFLT 0x05108 /* FC FLT Context */ 952 #define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */ 953 #define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */ 954 #define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */ 955 #define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */ 956 #define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */ 957 #define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */ 958 #define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */ 959 #define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */ 960 #define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */ 961 /* FCoE Receive Control */ 962 #define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */ 963 #define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */ 964 #define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */ 965 #define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */ 966 #define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */ 967 #define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */ 968 #define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */ 969 #define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */ 970 #define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */ 971 #define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */ 972 #define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8 973 /* FCoE Redirection */ 974 #define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */ 975 #define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */ 976 #define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */ 977 #define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */ 978 #define IXGBE_FCRETASEL_ENA 0x2 /* FCoE FCRETASEL bit */ 979 #define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */ 980 #define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */ 981 #define IXGBE_FCRETA_SIZE_X550 32 /* Max entries in FCRETA */ 982 /* Higher 7 bits for the queue index */ 983 #define IXGBE_FCRETA_ENTRY_HIGH_MASK 0x007F0000 984 #define IXGBE_FCRETA_ENTRY_HIGH_SHIFT 16 985 986 /* Stats registers */ 987 #define IXGBE_CRCERRS 0x04000 988 #define IXGBE_ILLERRC 0x04004 989 #define IXGBE_ERRBC 0x04008 990 #define IXGBE_MSPDC 0x04010 991 #define IXGBE_MBSDC 0x04018 /* Bad SFD Count */ 992 #define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/ 993 #define IXGBE_MLFC 0x04034 994 #define IXGBE_MRFC 0x04038 995 #define IXGBE_LINK_DN_CNT 0x0403c /* LINK Down Counter */ 996 #define IXGBE_RLEC 0x04040 997 #define IXGBE_LXONTXC 0x03F60 998 #define IXGBE_LXONRXC 0x0CF60 999 #define IXGBE_LXOFFTXC 0x03F68 1000 #define IXGBE_LXOFFRXC 0x0CF68 1001 #define IXGBE_LXONRXCNT 0x041A4 1002 #define IXGBE_LXOFFRXCNT 0x041A8 1003 #define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */ 1004 #define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */ 1005 #define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */ 1006 #define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/ 1007 #define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/ 1008 #define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/ 1009 #define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/ 1010 #define IXGBE_PRC64 0x0405C 1011 #define IXGBE_PRC127 0x04060 1012 #define IXGBE_PRC255 0x04064 1013 #define IXGBE_PRC511 0x04068 1014 #define IXGBE_PRC1023 0x0406C 1015 #define IXGBE_PRC1522 0x04070 1016 #define IXGBE_GPRC 0x04074 1017 #define IXGBE_BPRC 0x04078 1018 #define IXGBE_MPRC 0x0407C 1019 #define IXGBE_GPTC 0x04080 1020 #define IXGBE_GORCL 0x04088 1021 #define IXGBE_GORCH 0x0408C 1022 #define IXGBE_GOTCL 0x04090 1023 #define IXGBE_GOTCH 0x04094 1024 #define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/ 1025 #define IXGBE_RUC 0x040A4 1026 #define IXGBE_RFC 0x040A8 1027 #define IXGBE_ROC 0x040AC 1028 #define IXGBE_RJC 0x040B0 1029 #define IXGBE_MNGPRC 0x040B4 1030 #define IXGBE_MNGPDC 0x040B8 1031 #define IXGBE_MNGPTC 0x0CF90 1032 #define IXGBE_TORL 0x040C0 1033 #define IXGBE_TORH 0x040C4 1034 #define IXGBE_TPR 0x040D0 1035 #define IXGBE_TPT 0x040D4 1036 #define IXGBE_PTC64 0x040D8 1037 #define IXGBE_PTC127 0x040DC 1038 #define IXGBE_PTC255 0x040E0 1039 #define IXGBE_PTC511 0x040E4 1040 #define IXGBE_PTC1023 0x040E8 1041 #define IXGBE_PTC1522 0x040EC 1042 #define IXGBE_MPTC 0x040F0 1043 #define IXGBE_BPTC 0x040F4 1044 #define IXGBE_XEC 0x04120 1045 #define IXGBE_SSVPC 0x08780 1046 1047 #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) 1048 #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \ 1049 (0x08600 + ((_i) * 4))) 1050 #define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4)) 1051 1052 #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */ 1053 #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */ 1054 #define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 1055 #define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */ 1056 #define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 1057 #define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */ 1058 #define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */ 1059 #define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */ 1060 #define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */ 1061 #define IXGBE_FCCRC 0x05118 /* Num of Good Eth CRC w/ Bad FC CRC */ 1062 #define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */ 1063 #define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */ 1064 #define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */ 1065 #define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */ 1066 #define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */ 1067 #define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */ 1068 #define IXGBE_FCCRC_CNT_MASK 0x0000FFFF /* CRC_CNT: bit 0 - 15 */ 1069 #define IXGBE_FCLAST_CNT_MASK 0x0000FFFF /* Last_CNT: bit 0 - 15 */ 1070 #define IXGBE_O2BGPTC 0x041C4 1071 #define IXGBE_O2BSPC 0x087B0 1072 #define IXGBE_B2OSPC 0x041C0 1073 #define IXGBE_B2OGPRC 0x02F90 1074 #define IXGBE_BUPRC 0x04180 1075 #define IXGBE_BMPRC 0x04184 1076 #define IXGBE_BBPRC 0x04188 1077 #define IXGBE_BUPTC 0x0418C 1078 #define IXGBE_BMPTC 0x04190 1079 #define IXGBE_BBPTC 0x04194 1080 #define IXGBE_BCRCERRS 0x04198 1081 #define IXGBE_BXONRXC 0x0419C 1082 #define IXGBE_BXOFFRXC 0x041E0 1083 #define IXGBE_BXONTXC 0x041E4 1084 #define IXGBE_BXOFFTXC 0x041E8 1085 1086 /* Management */ 1087 #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */ 1088 #define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */ 1089 #define IXGBE_MANC 0x05820 1090 #define IXGBE_MFVAL 0x05824 1091 #define IXGBE_MANC2H 0x05860 1092 #define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */ 1093 #define IXGBE_MIPAF 0x058B0 1094 #define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */ 1095 #define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */ 1096 #define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */ 1097 #define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */ 1098 #define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */ 1099 #define IXGBE_LSWFW 0x15F14 1100 #define IXGBE_BMCIP(_i) (0x05050 + ((_i) * 4)) /* 0x5050-0x505C */ 1101 #define IXGBE_BMCIPVAL 0x05060 1102 #define IXGBE_BMCIP_IPADDR_TYPE 0x00000001 1103 #define IXGBE_BMCIP_IPADDR_VALID 0x00000002 1104 1105 /* Management Bit Fields and Masks */ 1106 #define IXGBE_MANC_MPROXYE 0x40000000 /* Management Proxy Enable */ 1107 #define IXGBE_MANC_RCV_TCO_EN 0x00020000 /* Rcv TCO packet enable */ 1108 #define IXGBE_MANC_EN_BMC2OS 0x10000000 /* Ena BMC2OS and OS2BMC traffic */ 1109 #define IXGBE_MANC_EN_BMC2OS_SHIFT 28 1110 1111 /* Firmware Semaphore Register */ 1112 #define IXGBE_FWSM_MODE_MASK 0xE 1113 #define IXGBE_FWSM_TS_ENABLED 0x1 1114 #define IXGBE_FWSM_FW_MODE_PT 0x4 1115 #define IXGBE_FWSM_FW_NVM_RECOVERY_MODE (1 << 5) 1116 #define IXGBE_FWSM_EXT_ERR_IND_MASK 0x01F80000 1117 #define IXGBE_FWSM_FW_VAL_BIT (1 << 15) 1118 1119 /* ARC Subsystem registers */ 1120 #define IXGBE_HICR 0x15F00 1121 #define IXGBE_FWSTS 0x15F0C 1122 #define IXGBE_HSMC0R 0x15F04 1123 #define IXGBE_HSMC1R 0x15F08 1124 #define IXGBE_SWSR 0x15F10 1125 #define IXGBE_FWRESETCNT 0x15F40 1126 #define IXGBE_HFDR 0x15FE8 1127 #define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */ 1128 #define IXGBE_FLEX_MNG_PTR(_i) (IXGBE_FLEX_MNG + ((_i) * 4)) 1129 1130 #define IXGBE_HICR_EN 0x01 /* Enable bit - RO */ 1131 /* Driver sets this bit when done to put command in RAM */ 1132 #define IXGBE_HICR_C 0x02 1133 #define IXGBE_HICR_SV 0x04 /* Status Validity */ 1134 #define IXGBE_HICR_FW_RESET_ENABLE 0x40 1135 #define IXGBE_HICR_FW_RESET 0x80 1136 1137 /* PCI-E registers */ 1138 #define IXGBE_GCR 0x11000 1139 #define IXGBE_GTV 0x11004 1140 #define IXGBE_FUNCTAG 0x11008 1141 #define IXGBE_GLT 0x1100C 1142 #define IXGBE_PCIEPIPEADR 0x11004 1143 #define IXGBE_PCIEPIPEDAT 0x11008 1144 #define IXGBE_GSCL_1 0x11010 1145 #define IXGBE_GSCL_2 0x11014 1146 #define IXGBE_GSCL_1_X540 IXGBE_GSCL_1 1147 #define IXGBE_GSCL_2_X540 IXGBE_GSCL_2 1148 #define IXGBE_GSCL_3 0x11018 1149 #define IXGBE_GSCL_4 0x1101C 1150 #define IXGBE_GSCN_0 0x11020 1151 #define IXGBE_GSCN_1 0x11024 1152 #define IXGBE_GSCN_2 0x11028 1153 #define IXGBE_GSCN_3 0x1102C 1154 #define IXGBE_GSCN_0_X540 IXGBE_GSCN_0 1155 #define IXGBE_GSCN_1_X540 IXGBE_GSCN_1 1156 #define IXGBE_GSCN_2_X540 IXGBE_GSCN_2 1157 #define IXGBE_GSCN_3_X540 IXGBE_GSCN_3 1158 #define IXGBE_FACTPS 0x10150 1159 1160 /* X550 */ 1161 #define IXGBE_PCI_ICAUSE 0x11520 1162 #define IXGBE_PCI_IENA 0x11528 1163 #define IXGBE_PCI_VMINDEX 0x11530 1164 #define IXGBE_PCI_VMPEND 0x11538 1165 #define IXGBE_PCI_DREVID 0x11540 1166 #define IXGBE_PCI_BYTCTH 0x11544 1167 #define IXGBE_PCI_BYTCTL 0x11548 1168 #define IXGBE_PCI_LATCT 0x11720 /* Denverton */ 1169 #define IXGBE_PCI_LCBDATA 0x11734 1170 #define IXGBE_PCI_PKTCT 0x11740 /* Denverton */ 1171 #define IXGBE_PCI_LCBADD 0x11788 1172 #define IXGBE_GSCL_1_X550 0x11800 1173 #define IXGBE_GSCL_2_X550 0x11804 1174 #define IXGBE_PCI_GSCL(_i) (0x011810 + ((_i) * 4)) 1175 #define IXGBE_PCI_GSCN(_i) (0x011820 + ((_i) * 4)) 1176 1177 #define IXGBE_FACTPS_X540 IXGBE_FACTPS 1178 #define IXGBE_GSCL_1_X550 0x11800 1179 #define IXGBE_GSCL_2_X550 0x11804 1180 #define IXGBE_GSCL_1_X550EM_x IXGBE_GSCL_1_X550 1181 #define IXGBE_GSCL_2_X550EM_x IXGBE_GSCL_2_X550 1182 #define IXGBE_GSCN_0_X550 0x11820 1183 #define IXGBE_GSCN_1_X550 0x11824 1184 #define IXGBE_GSCN_2_X550 0x11828 1185 #define IXGBE_GSCN_3_X550 0x1182C 1186 #define IXGBE_GSCN_0_X550EM_x IXGBE_GSCN_0_X550 1187 #define IXGBE_GSCN_1_X550EM_x IXGBE_GSCN_1_X550 1188 #define IXGBE_GSCN_2_X550EM_x IXGBE_GSCN_2_X550 1189 #define IXGBE_GSCN_3_X550EM_x IXGBE_GSCN_3_X550 1190 #define IXGBE_FACTPS_X550 IXGBE_FACTPS 1191 #define IXGBE_FACTPS_X550EM_x IXGBE_FACTPS 1192 #define IXGBE_GSCL_1_X550EM_a IXGBE_GSCL_1_X550 1193 #define IXGBE_GSCL_2_X550EM_a IXGBE_GSCL_2_X550 1194 #define IXGBE_GSCN_0_X550EM_a IXGBE_GSCN_0_X550 1195 #define IXGBE_GSCN_1_X550EM_a IXGBE_GSCN_1_X550 1196 #define IXGBE_GSCN_2_X550EM_a IXGBE_GSCN_2_X550 1197 #define IXGBE_GSCN_3_X550EM_a IXGBE_GSCN_3_X550 1198 #define IXGBE_FACTPS_X550EM_a 0x15FEC 1199 #define IXGBE_FACTPS_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FACTPS) 1200 1201 #define IXGBE_PCIEANACTL 0x11040 1202 #define IXGBE_SWSM 0x10140 1203 #define IXGBE_SWSM_X540 IXGBE_SWSM 1204 #define IXGBE_SWSM_X550 IXGBE_SWSM 1205 #define IXGBE_SWSM_X550EM_x IXGBE_SWSM 1206 #define IXGBE_SWSM_X550EM_a 0x15F70 1207 #define IXGBE_SWSM_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SWSM) 1208 1209 #define IXGBE_FWSM 0x10148 1210 #define IXGBE_FWSM_X540 IXGBE_FWSM 1211 #define IXGBE_FWSM_X550 IXGBE_FWSM 1212 #define IXGBE_FWSM_X550EM_x IXGBE_FWSM 1213 #define IXGBE_FWSM_X550EM_a 0x15F74 1214 #define IXGBE_FWSM_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FWSM) 1215 1216 #define IXGBE_SWFW_SYNC IXGBE_GSSR 1217 #define IXGBE_SWFW_SYNC_X540 IXGBE_SWFW_SYNC 1218 #define IXGBE_SWFW_SYNC_X550 IXGBE_SWFW_SYNC 1219 #define IXGBE_SWFW_SYNC_X550EM_x IXGBE_SWFW_SYNC 1220 #define IXGBE_SWFW_SYNC_X550EM_a 0x15F78 1221 #define IXGBE_SWFW_SYNC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SWFW_SYNC) 1222 1223 #define IXGBE_GSSR 0x10160 1224 #define IXGBE_MREVID 0x11064 1225 #define IXGBE_DCA_ID 0x11070 1226 #define IXGBE_DCA_CTRL 0x11074 1227 1228 /* PCI-E registers 82599-Specific */ 1229 #define IXGBE_GCR_EXT 0x11050 1230 #define IXGBE_GSCL_5_82599 0x11030 1231 #define IXGBE_GSCL_6_82599 0x11034 1232 #define IXGBE_GSCL_7_82599 0x11038 1233 #define IXGBE_GSCL_8_82599 0x1103C 1234 #define IXGBE_GSCL_5_X540 IXGBE_GSCL_5_82599 1235 #define IXGBE_GSCL_6_X540 IXGBE_GSCL_6_82599 1236 #define IXGBE_GSCL_7_X540 IXGBE_GSCL_7_82599 1237 #define IXGBE_GSCL_8_X540 IXGBE_GSCL_8_82599 1238 #define IXGBE_PHYADR_82599 0x11040 1239 #define IXGBE_PHYDAT_82599 0x11044 1240 #define IXGBE_PHYCTL_82599 0x11048 1241 #define IXGBE_PBACLR_82599 0x11068 1242 #define IXGBE_CIAA 0x11088 1243 #define IXGBE_CIAD 0x1108C 1244 #define IXGBE_CIAA_82599 IXGBE_CIAA 1245 #define IXGBE_CIAD_82599 IXGBE_CIAD 1246 #define IXGBE_CIAA_X540 IXGBE_CIAA 1247 #define IXGBE_CIAD_X540 IXGBE_CIAD 1248 #define IXGBE_GSCL_5_X550 0x11810 1249 #define IXGBE_GSCL_6_X550 0x11814 1250 #define IXGBE_GSCL_7_X550 0x11818 1251 #define IXGBE_GSCL_8_X550 0x1181C 1252 #define IXGBE_GSCL_5_X550EM_x IXGBE_GSCL_5_X550 1253 #define IXGBE_GSCL_6_X550EM_x IXGBE_GSCL_6_X550 1254 #define IXGBE_GSCL_7_X550EM_x IXGBE_GSCL_7_X550 1255 #define IXGBE_GSCL_8_X550EM_x IXGBE_GSCL_8_X550 1256 #define IXGBE_CIAA_X550 0x11508 1257 #define IXGBE_CIAD_X550 0x11510 1258 #define IXGBE_CIAA_X550EM_x IXGBE_CIAA_X550 1259 #define IXGBE_CIAD_X550EM_x IXGBE_CIAD_X550 1260 #define IXGBE_GSCL_5_X550EM_a IXGBE_GSCL_5_X550 1261 #define IXGBE_GSCL_6_X550EM_a IXGBE_GSCL_6_X550 1262 #define IXGBE_GSCL_7_X550EM_a IXGBE_GSCL_7_X550 1263 #define IXGBE_GSCL_8_X550EM_a IXGBE_GSCL_8_X550 1264 #define IXGBE_CIAA_X550EM_a IXGBE_CIAA_X550 1265 #define IXGBE_CIAD_X550EM_a IXGBE_CIAD_X550 1266 #define IXGBE_CIAA_BY_MAC(_hw) IXGBE_BY_MAC((_hw), CIAA) 1267 #define IXGBE_CIAD_BY_MAC(_hw) IXGBE_BY_MAC((_hw), CIAD) 1268 #define IXGBE_PICAUSE 0x110B0 1269 #define IXGBE_PIENA 0x110B8 1270 #define IXGBE_CDQ_MBR_82599 0x110B4 1271 #define IXGBE_PCIESPARE 0x110BC 1272 #define IXGBE_MISC_REG_82599 0x110F0 1273 #define IXGBE_ECC_CTRL_0_82599 0x11100 1274 #define IXGBE_ECC_CTRL_1_82599 0x11104 1275 #define IXGBE_ECC_STATUS_82599 0x110E0 1276 #define IXGBE_BAR_CTRL_82599 0x110F4 1277 1278 /* PCI Express Control */ 1279 #define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000 1280 #define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000 1281 #define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000 1282 #define IXGBE_GCR_CAP_VER2 0x00040000 1283 1284 #define IXGBE_GCR_EXT_MSIX_EN 0x80000000 1285 #define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000 1286 #define IXGBE_GCR_EXT_VT_MODE_16 0x00000001 1287 #define IXGBE_GCR_EXT_VT_MODE_32 0x00000002 1288 #define IXGBE_GCR_EXT_VT_MODE_64 0x00000003 1289 #define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \ 1290 IXGBE_GCR_EXT_VT_MODE_64) 1291 #define IXGBE_GCR_EXT_VT_MODE_MASK 0x00000003 1292 /* Time Sync Registers */ 1293 #define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */ 1294 #define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */ 1295 #define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */ 1296 #define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */ 1297 #define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */ 1298 #define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */ 1299 #define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */ 1300 #define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */ 1301 #define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */ 1302 #define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */ 1303 #define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */ 1304 #define IXGBE_SYSTIMR 0x08C58 /* System time register Residue - RO */ 1305 #define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */ 1306 #define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */ 1307 #define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */ 1308 #define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */ 1309 #define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */ 1310 #define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */ 1311 #define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */ 1312 #define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */ 1313 #define IXGBE_CLKTIML 0x08C34 /* Clock Out Time Register Low - RW */ 1314 #define IXGBE_CLKTIMH 0x08C38 /* Clock Out Time Register High - RW */ 1315 #define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */ 1316 #define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */ 1317 #define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */ 1318 #define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */ 1319 #define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */ 1320 #define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */ 1321 #define IXGBE_TSIM 0x08C68 /* TimeSync Interrupt Mask Register - RW */ 1322 #define IXGBE_TSICR 0x08C60 /* TimeSync Interrupt Cause Register - WO */ 1323 #define IXGBE_TSSDP 0x0003C /* TimeSync SDP Configuration Register - RW */ 1324 1325 /* Diagnostic Registers */ 1326 #define IXGBE_RDSTATCTL 0x02C20 1327 #define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */ 1328 #define IXGBE_RDHMPN 0x02F08 1329 #define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4)) 1330 #define IXGBE_RDPROBE 0x02F20 1331 #define IXGBE_RDMAM 0x02F30 1332 #define IXGBE_RDMAD 0x02F34 1333 #define IXGBE_TDHMPN 0x07F08 1334 #define IXGBE_TDHMPN2 0x082FC 1335 #define IXGBE_TXDESCIC 0x082CC 1336 #define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4)) 1337 #define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4)) 1338 #define IXGBE_TDPROBE 0x07F20 1339 #define IXGBE_TXBUFCTRL 0x0C600 1340 #define IXGBE_TXBUFDATA0 0x0C610 1341 #define IXGBE_TXBUFDATA1 0x0C614 1342 #define IXGBE_TXBUFDATA2 0x0C618 1343 #define IXGBE_TXBUFDATA3 0x0C61C 1344 #define IXGBE_RXBUFCTRL 0x03600 1345 #define IXGBE_RXBUFDATA0 0x03610 1346 #define IXGBE_RXBUFDATA1 0x03614 1347 #define IXGBE_RXBUFDATA2 0x03618 1348 #define IXGBE_RXBUFDATA3 0x0361C 1349 #define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */ 1350 #define IXGBE_RFVAL 0x050A4 1351 #define IXGBE_MDFTC1 0x042B8 1352 #define IXGBE_MDFTC2 0x042C0 1353 #define IXGBE_MDFTFIFO1 0x042C4 1354 #define IXGBE_MDFTFIFO2 0x042C8 1355 #define IXGBE_MDFTS 0x042CC 1356 #define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/ 1357 #define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/ 1358 #define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/ 1359 #define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/ 1360 #define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/ 1361 #define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/ 1362 #define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/ 1363 #define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/ 1364 #define IXGBE_PCIEECCCTL 0x1106C 1365 #define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/ 1366 #define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/ 1367 #define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/ 1368 #define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/ 1369 #define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/ 1370 #define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/ 1371 #define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/ 1372 #define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/ 1373 #define IXGBE_PCIEECCCTL0 0x11100 1374 #define IXGBE_PCIEECCCTL1 0x11104 1375 #define IXGBE_RXDBUECC 0x03F70 1376 #define IXGBE_TXDBUECC 0x0CF70 1377 #define IXGBE_RXDBUEST 0x03F74 1378 #define IXGBE_TXDBUEST 0x0CF74 1379 #define IXGBE_PBTXECC 0x0C300 1380 #define IXGBE_PBRXECC 0x03300 1381 #define IXGBE_GHECCR 0x110B0 1382 1383 /* MAC Registers */ 1384 #define IXGBE_PCS1GCFIG 0x04200 1385 #define IXGBE_PCS1GLCTL 0x04208 1386 #define IXGBE_PCS1GLSTA 0x0420C 1387 #define IXGBE_PCS1GDBG0 0x04210 1388 #define IXGBE_PCS1GDBG1 0x04214 1389 #define IXGBE_PCS1GANA 0x04218 1390 #define IXGBE_PCS1GANLP 0x0421C 1391 #define IXGBE_PCS1GANNP 0x04220 1392 #define IXGBE_PCS1GANLPNP 0x04224 1393 #define IXGBE_HLREG0 0x04240 1394 #define IXGBE_HLREG1 0x04244 1395 #define IXGBE_PAP 0x04248 1396 #define IXGBE_MACA 0x0424C 1397 #define IXGBE_APAE 0x04250 1398 #define IXGBE_ARD 0x04254 1399 #define IXGBE_AIS 0x04258 1400 #define IXGBE_MSCA 0x0425C 1401 #define IXGBE_MSRWD 0x04260 1402 #define IXGBE_MLADD 0x04264 1403 #define IXGBE_MHADD 0x04268 1404 #define IXGBE_MAXFRS 0x04268 1405 #define IXGBE_TREG 0x0426C 1406 #define IXGBE_PCSS1 0x04288 1407 #define IXGBE_PCSS2 0x0428C 1408 #define IXGBE_XPCSS 0x04290 1409 #define IXGBE_MFLCN 0x04294 1410 #define IXGBE_SERDESC 0x04298 1411 #define IXGBE_MAC_SGMII_BUSY 0x04298 1412 #define IXGBE_MACS 0x0429C 1413 #define IXGBE_AUTOC 0x042A0 1414 #define IXGBE_LINKS 0x042A4 1415 #define IXGBE_LINKS2 0x04324 1416 #define IXGBE_AUTOC2 0x042A8 1417 #define IXGBE_AUTOC3 0x042AC 1418 #define IXGBE_ANLP1 0x042B0 1419 #define IXGBE_ANLP2 0x042B4 1420 #define IXGBE_MACC 0x04330 1421 #define IXGBE_ATLASCTL 0x04800 1422 #define IXGBE_MMNGC 0x042D0 1423 #define IXGBE_ANLPNP1 0x042D4 1424 #define IXGBE_ANLPNP2 0x042D8 1425 #define IXGBE_KRPCSFC 0x042E0 1426 #define IXGBE_KRPCSS 0x042E4 1427 #define IXGBE_FECS1 0x042E8 1428 #define IXGBE_FECS2 0x042EC 1429 #define IXGBE_SMADARCTL 0x14F10 1430 #define IXGBE_MPVC 0x04318 1431 #define IXGBE_SGMIIC 0x04314 1432 1433 /* Statistics Registers */ 1434 #define IXGBE_RXNFGPC 0x041B0 1435 #define IXGBE_RXNFGBCL 0x041B4 1436 #define IXGBE_RXNFGBCH 0x041B8 1437 #define IXGBE_RXDGPC 0x02F50 1438 #define IXGBE_RXDGBCL 0x02F54 1439 #define IXGBE_RXDGBCH 0x02F58 1440 #define IXGBE_RXDDGPC 0x02F5C 1441 #define IXGBE_RXDDGBCL 0x02F60 1442 #define IXGBE_RXDDGBCH 0x02F64 1443 #define IXGBE_RXLPBKGPC 0x02F68 1444 #define IXGBE_RXLPBKGBCL 0x02F6C 1445 #define IXGBE_RXLPBKGBCH 0x02F70 1446 #define IXGBE_RXDLPBKGPC 0x02F74 1447 #define IXGBE_RXDLPBKGBCL 0x02F78 1448 #define IXGBE_RXDLPBKGBCH 0x02F7C 1449 #define IXGBE_TXDGPC 0x087A0 1450 #define IXGBE_TXDGBCL 0x087A4 1451 #define IXGBE_TXDGBCH 0x087A8 1452 1453 #define IXGBE_RXDSTATCTRL 0x02F40 1454 1455 /* Copper Pond 2 link timeout */ 1456 #define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50 1457 1458 /* Omer CORECTL */ 1459 #define IXGBE_CORECTL 0x014F00 1460 /* BARCTRL */ 1461 #define IXGBE_BARCTRL 0x110F4 1462 #define IXGBE_BARCTRL_FLSIZE 0x0700 1463 #define IXGBE_BARCTRL_FLSIZE_SHIFT 8 1464 #define IXGBE_BARCTRL_CSRSIZE 0x2000 1465 #define IXGBE_BARCTRL_CSRSIZE_SHIFT 13 1466 1467 /* RSCCTL Bit Masks */ 1468 #define IXGBE_RSCCTL_RSCEN 0x01 1469 #define IXGBE_RSCCTL_MAXDESC_1 0x00 1470 #define IXGBE_RSCCTL_MAXDESC_4 0x04 1471 #define IXGBE_RSCCTL_MAXDESC_8 0x08 1472 #define IXGBE_RSCCTL_MAXDESC_16 0x0C 1473 #define IXGBE_RSCCTL_TS_DIS 0x02 1474 1475 /* RSCDBU Bit Masks */ 1476 #define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F 1477 #define IXGBE_RSCDBU_RSCACKDIS 0x00000080 1478 1479 /* RDRXCTL Bit Masks */ 1480 #define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min THLD Size */ 1481 #define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */ 1482 #define IXGBE_RDRXCTL_PSP 0x00000004 /* Pad Small Packet */ 1483 #define IXGBE_RDRXCTL_MVMEN 0x00000020 1484 #define IXGBE_RDRXCTL_RSC_PUSH_DIS 0x00000020 1485 #define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */ 1486 #define IXGBE_RDRXCTL_RSC_PUSH 0x00000080 1487 #define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */ 1488 #define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */ 1489 #define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI*/ 1490 #define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC ena */ 1491 #define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC ena */ 1492 #define IXGBE_RDRXCTL_MBINTEN 0x10000000 1493 #define IXGBE_RDRXCTL_MDP_EN 0x20000000 1494 1495 /* RQTC Bit Masks and Shifts */ 1496 #define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4) 1497 #define IXGBE_RQTC_TC0_MASK (0x7 << 0) 1498 #define IXGBE_RQTC_TC1_MASK (0x7 << 4) 1499 #define IXGBE_RQTC_TC2_MASK (0x7 << 8) 1500 #define IXGBE_RQTC_TC3_MASK (0x7 << 12) 1501 #define IXGBE_RQTC_TC4_MASK (0x7 << 16) 1502 #define IXGBE_RQTC_TC5_MASK (0x7 << 20) 1503 #define IXGBE_RQTC_TC6_MASK (0x7 << 24) 1504 #define IXGBE_RQTC_TC7_MASK (0x7 << 28) 1505 1506 /* PSRTYPE.RQPL Bit masks and shift */ 1507 #define IXGBE_PSRTYPE_RQPL_MASK 0x7 1508 #define IXGBE_PSRTYPE_RQPL_SHIFT 29 1509 1510 /* CTRL Bit Masks */ 1511 #define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Primary Disable bit */ 1512 #define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */ 1513 #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ 1514 #define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST) 1515 1516 /* FACTPS */ 1517 #define IXGBE_FACTPS_MNGCG 0x20000000 /* Managebility Clock Gated */ 1518 #define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */ 1519 1520 /* MHADD Bit Masks */ 1521 #define IXGBE_MHADD_MFS_MASK 0xFFFF0000 1522 #define IXGBE_MHADD_MFS_SHIFT 16 1523 1524 /* Extended Device Control */ 1525 #define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */ 1526 #define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */ 1527 #define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 1528 #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 1529 1530 /* Direct Cache Access (DCA) definitions */ 1531 #define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 1532 #define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 1533 1534 #define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 1535 #define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 1536 1537 #define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 1538 #define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */ 1539 #define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */ 1540 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* Rx Desc enable */ 1541 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* Rx Desc header ena */ 1542 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* Rx Desc payload ena */ 1543 #define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* Rx rd Desc Relax Order */ 1544 #define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */ 1545 #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */ 1546 1547 #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 1548 #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */ 1549 #define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */ 1550 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 1551 #define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */ 1552 #define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */ 1553 #define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */ 1554 #define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */ 1555 1556 /* MSCA Bit Masks */ 1557 #define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Addr (new prot) */ 1558 #define IXGBE_MSCA_NP_ADDR_SHIFT 0 1559 #define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Dev Type (new prot) */ 1560 #define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old prot */ 1561 #define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */ 1562 #define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/ 1563 #define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */ 1564 #define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */ 1565 #define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */ 1566 #define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (wr) */ 1567 #define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (rd) */ 1568 #define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (rd auto inc)*/ 1569 #define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */ 1570 #define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */ 1571 #define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new prot) */ 1572 #define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old prot) */ 1573 #define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */ 1574 #define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress ena */ 1575 1576 /* MSRWD bit masks */ 1577 #define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF 1578 #define IXGBE_MSRWD_WRITE_DATA_SHIFT 0 1579 #define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000 1580 #define IXGBE_MSRWD_READ_DATA_SHIFT 16 1581 1582 /* Atlas registers */ 1583 #define IXGBE_ATLAS_PDN_LPBK 0x24 1584 #define IXGBE_ATLAS_PDN_10G 0xB 1585 #define IXGBE_ATLAS_PDN_1G 0xC 1586 #define IXGBE_ATLAS_PDN_AN 0xD 1587 1588 /* Atlas bit masks */ 1589 #define IXGBE_ATLASCTL_WRITE_CMD 0x00010000 1590 #define IXGBE_ATLAS_PDN_TX_REG_EN 0x10 1591 #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0 1592 #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0 1593 #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0 1594 1595 /* Omer bit masks */ 1596 #define IXGBE_CORECTL_WRITE_CMD 0x00010000 1597 1598 /* Device Type definitions for new protocol MDIO commands */ 1599 #define IXGBE_MDIO_ZERO_DEV_TYPE 0x0 1600 #define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1 1601 #define IXGBE_MDIO_PCS_DEV_TYPE 0x3 1602 #define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4 1603 #define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7 1604 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */ 1605 #define IXGBE_TWINAX_DEV 1 1606 1607 #define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */ 1608 1609 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Ctrl Reg */ 1610 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */ 1611 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */ 1612 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0-10G, 1-1G */ 1613 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018 1614 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010 1615 1616 #define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */ 1617 #define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */ 1618 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT 0xC800 /* AUTO_NEG Vendor Status Reg */ 1619 #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM 0xCC00 /* AUTO_NEG Vendor TX Reg */ 1620 #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2 0xCC01 /* AUTO_NEG Vendor Tx Reg */ 1621 #define IXGBE_MDIO_AUTO_NEG_VEN_LSC 0x1 /* AUTO_NEG Vendor Tx LSC */ 1622 #define IXGBE_MDIO_AUTO_NEG_ADVT 0x10 /* AUTO_NEG Advt Reg */ 1623 #define IXGBE_MDIO_AUTO_NEG_LP 0x13 /* AUTO_NEG LP Status Reg */ 1624 #define IXGBE_MDIO_AUTO_NEG_EEE_ADVT 0x3C /* AUTO_NEG EEE Advt Reg */ 1625 #define IXGBE_AUTO_NEG_10GBASE_EEE_ADVT 0x8 /* AUTO NEG EEE 10GBaseT Advt */ 1626 #define IXGBE_AUTO_NEG_1000BASE_EEE_ADVT 0x4 /* AUTO NEG EEE 1000BaseT Advt */ 1627 #define IXGBE_AUTO_NEG_100BASE_EEE_ADVT 0x2 /* AUTO NEG EEE 100BaseT Advt */ 1628 #define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */ 1629 #define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */ 1630 #define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/ 1631 #define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/ 1632 #define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */ 1633 #define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */ 1634 #define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */ 1635 #define IXGBE_MDIO_PHY_SPEED_100M 0x0020 /* 100M capable */ 1636 #define IXGBE_MDIO_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */ 1637 #define IXGBE_MDIO_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */ 1638 #define IXGBE_MDIO_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */ 1639 #define IXGBE_MDIO_PHY_100BASETX_ABILITY 0x0080 /* 100BaseTX capable */ 1640 #define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE 0x0800 /* Set low power mode */ 1641 #define IXGBE_AUTO_NEG_LP_STATUS 0xE820 /* AUTO NEG Rx LP Status Reg */ 1642 #define IXGBE_AUTO_NEG_LP_1000BASE_CAP 0x8000 /* AUTO NEG Rx LP 1000BaseT Cap */ 1643 #define IXGBE_AUTO_NEG_LP_10GBASE_CAP 0x0800 /* AUTO NEG Rx LP 10GBaseT Cap */ 1644 #define IXGBE_AUTO_NEG_10GBASET_STAT 0x0021 /* AUTO NEG 10G BaseT Stat */ 1645 1646 #define IXGBE_MDIO_TX_VENDOR_ALARMS_3 0xCC02 /* Vendor Alarms 3 Reg */ 1647 #define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK 0x3 /* PHY Reset Complete Mask */ 1648 #define IXGBE_MDIO_GLOBAL_RES_PR_10 0xC479 /* Global Resv Provisioning 10 Reg */ 1649 #define IXGBE_MDIO_POWER_UP_STALL 0x8000 /* Power Up Stall */ 1650 #define IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK 0xFF00 /* int std mask */ 1651 #define IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG 0xFC00 /* chip std int flag */ 1652 #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK 0xFF01 /* int chip-wide mask */ 1653 #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG 0xFC01 /* int chip-wide mask */ 1654 #define IXGBE_MDIO_GLOBAL_ALARM_1 0xCC00 /* Global alarm 1 */ 1655 #define IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT 0x0010 /* device fault */ 1656 #define IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL 0x4000 /* high temp failure */ 1657 #define IXGBE_MDIO_GLOBAL_FAULT_MSG 0xC850 /* Global Fault Message */ 1658 #define IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP 0x8007 /* high temp failure */ 1659 #define IXGBE_MDIO_GLOBAL_INT_MASK 0xD400 /* Global int mask */ 1660 #define IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN 0x1000 /* autoneg vendor alarm int enable */ 1661 #define IXGBE_MDIO_GLOBAL_ALARM_1_INT 0x4 /* int in Global alarm 1 */ 1662 #define IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN 0x1 /* vendor alarm int enable */ 1663 #define IXGBE_MDIO_GLOBAL_STD_ALM2_INT 0x200 /* vendor alarm2 int mask */ 1664 #define IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN 0x4000 /* int high temp enable */ 1665 #define IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN 0x0010 /* int dev fault enable */ 1666 #define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR 0x0000 /* PMA/PMD Control Reg */ 1667 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */ 1668 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */ 1669 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */ 1670 #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK 0xD401 /* PHY TX Vendor LASI */ 1671 #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN 0x1 /* PHY TX Vendor LASI enable */ 1672 #define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR 0x9 /* Standard Transmit Dis Reg */ 1673 #define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE 0x0001 /* PMD Global Transmit Dis */ 1674 1675 #define IXGBE_PCRC8ECL 0x0E810 /* PCR CRC-8 Error Count Lo */ 1676 #define IXGBE_PCRC8ECH 0x0E811 /* PCR CRC-8 Error Count Hi */ 1677 #define IXGBE_PCRC8ECH_MASK 0x1F 1678 #define IXGBE_LDPCECL 0x0E820 /* PCR Uncorrected Error Count Lo */ 1679 #define IXGBE_LDPCECH 0x0E821 /* PCR Uncorrected Error Count Hi */ 1680 1681 /* MII clause 22/28 definitions */ 1682 #define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800 1683 1684 #define IXGBE_MDIO_XENPAK_LASI_STATUS 0x9005 /* XENPAK LASI Status register*/ 1685 #define IXGBE_XENPAK_LASI_LINK_STATUS_ALARM 0x1 /* Link Status Alarm change */ 1686 1687 #define IXGBE_MDIO_AUTO_NEG_LINK_STATUS 0x4 /* Indicates if link is up */ 1688 1689 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK 0x7 /* Speed/Duplex Mask */ 1690 #define IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK 0x6 /* Speed Mask */ 1691 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF 0x0 /* 10Mb/s Half Duplex */ 1692 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL 0x1 /* 10Mb/s Full Duplex */ 1693 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF 0x2 /* 100Mb/s Half Duplex */ 1694 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_FULL 0x3 /* 100Mb/s Full Duplex */ 1695 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_HALF 0x4 /* 1Gb/s Half Duplex */ 1696 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL 0x5 /* 1Gb/s Full Duplex */ 1697 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF 0x6 /* 10Gb/s Half Duplex */ 1698 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL 0x7 /* 10Gb/s Full Duplex */ 1699 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB 0x4 /* 1Gb/s */ 1700 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB 0x6 /* 10Gb/s */ 1701 1702 #define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG 0x20 /* 10G Control Reg */ 1703 #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */ 1704 #define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */ 1705 #define IXGBE_MII_AUTONEG_ADVERTISE_REG 0x10 /* 100M Advertisement */ 1706 #define IXGBE_MII_10GBASE_T_ADVERTISE 0x1000 /* full duplex, bit:12*/ 1707 #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/ 1708 #define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/ 1709 #define IXGBE_MII_2_5GBASE_T_ADVERTISE 0x0400 1710 #define IXGBE_MII_5GBASE_T_ADVERTISE 0x0800 1711 #define IXGBE_MII_100BASE_T_ADVERTISE 0x0100 /* full duplex, bit:8 */ 1712 #define IXGBE_MII_100BASE_T_ADVERTISE_HALF 0x0080 /* half duplex, bit:7 */ 1713 #define IXGBE_MII_RESTART 0x200 1714 #define IXGBE_MII_AUTONEG_COMPLETE 0x20 1715 #define IXGBE_MII_AUTONEG_LINK_UP 0x04 1716 #define IXGBE_MII_AUTONEG_REG 0x0 1717 1718 #define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 1719 #define IXGBE_MAX_PHY_ADDR 32 1720 1721 /* PHY IDs*/ 1722 #define TN1010_PHY_ID 0x00A19410 1723 #define TNX_FW_REV 0xB 1724 #define X540_PHY_ID 0x01540200 1725 #define X550_PHY_ID 0x01540220 1726 #define X550_PHY_ID2 0x01540223 1727 #define X550_PHY_ID3 0x01540221 1728 #define X557_PHY_ID 0x01540240 1729 #define X557_PHY_ID2 0x01540250 1730 #define AQ_FW_REV 0x20 1731 #define QT2022_PHY_ID 0x0043A400 1732 #define ATH_PHY_ID 0x03429050 1733 1734 /* PHY Types */ 1735 #define IXGBE_M88E1500_E_PHY_ID 0x01410DD0 1736 #define IXGBE_M88E1543_E_PHY_ID 0x01410EA0 1737 1738 /* Special PHY Init Routine */ 1739 #define IXGBE_PHY_INIT_OFFSET_NL 0x002B 1740 #define IXGBE_PHY_INIT_END_NL 0xFFFF 1741 #define IXGBE_CONTROL_MASK_NL 0xF000 1742 #define IXGBE_DATA_MASK_NL 0x0FFF 1743 #define IXGBE_CONTROL_SHIFT_NL 12 1744 #define IXGBE_DELAY_NL 0 1745 #define IXGBE_DATA_NL 1 1746 #define IXGBE_CONTROL_NL 0x000F 1747 #define IXGBE_CONTROL_EOL_NL 0x0FFF 1748 #define IXGBE_CONTROL_SOL_NL 0x0000 1749 1750 /* General purpose Interrupt Enable */ 1751 #define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */ 1752 #define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */ 1753 #define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */ 1754 #define IXGBE_SDP0_GPIEN_X540 0x00000002 /* SDP0 on X540 and X550 */ 1755 #define IXGBE_SDP1_GPIEN_X540 0x00000004 /* SDP1 on X540 and X550 */ 1756 #define IXGBE_SDP2_GPIEN_X540 0x00000008 /* SDP2 on X540 and X550 */ 1757 #define IXGBE_SDP0_GPIEN_X550 IXGBE_SDP0_GPIEN_X540 1758 #define IXGBE_SDP1_GPIEN_X550 IXGBE_SDP1_GPIEN_X540 1759 #define IXGBE_SDP2_GPIEN_X550 IXGBE_SDP2_GPIEN_X540 1760 #define IXGBE_SDP0_GPIEN_X550EM_x IXGBE_SDP0_GPIEN_X540 1761 #define IXGBE_SDP1_GPIEN_X550EM_x IXGBE_SDP1_GPIEN_X540 1762 #define IXGBE_SDP2_GPIEN_X550EM_x IXGBE_SDP2_GPIEN_X540 1763 #define IXGBE_SDP0_GPIEN_X550EM_a IXGBE_SDP0_GPIEN_X540 1764 #define IXGBE_SDP1_GPIEN_X550EM_a IXGBE_SDP1_GPIEN_X540 1765 #define IXGBE_SDP2_GPIEN_X550EM_a IXGBE_SDP2_GPIEN_X540 1766 #define IXGBE_SDP0_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP0_GPIEN) 1767 #define IXGBE_SDP1_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP1_GPIEN) 1768 #define IXGBE_SDP2_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP2_GPIEN) 1769 1770 #define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */ 1771 #define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */ 1772 #define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */ 1773 #define IXGBE_GPIE_EIAME 0x40000000 1774 #define IXGBE_GPIE_PBA_SUPPORT 0x80000000 1775 #define IXGBE_GPIE_RSC_DELAY_SHIFT 11 1776 #define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */ 1777 #define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */ 1778 #define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */ 1779 #define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */ 1780 1781 /* Packet Buffer Initialization */ 1782 #define IXGBE_MAX_PACKET_BUFFERS 8 1783 1784 #define IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */ 1785 #define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */ 1786 #define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */ 1787 #define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */ 1788 #define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */ 1789 #define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */ 1790 #define IXGBE_RXPBSIZE_MAX 0x00080000 /* 512KB Packet Buffer */ 1791 #define IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB Packet Buffer */ 1792 1793 #define IXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */ 1794 #define IXGBE_MAX_PB 8 1795 1796 /* Packet buffer allocation strategies */ 1797 enum { 1798 PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */ 1799 #define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL 1800 PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */ 1801 #define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED 1802 }; 1803 1804 /* Transmit Flow Control status */ 1805 #define IXGBE_TFCS_TXOFF 0x00000001 1806 #define IXGBE_TFCS_TXOFF0 0x00000100 1807 #define IXGBE_TFCS_TXOFF1 0x00000200 1808 #define IXGBE_TFCS_TXOFF2 0x00000400 1809 #define IXGBE_TFCS_TXOFF3 0x00000800 1810 #define IXGBE_TFCS_TXOFF4 0x00001000 1811 #define IXGBE_TFCS_TXOFF5 0x00002000 1812 #define IXGBE_TFCS_TXOFF6 0x00004000 1813 #define IXGBE_TFCS_TXOFF7 0x00008000 1814 1815 /* TCP Timer */ 1816 #define IXGBE_TCPTIMER_KS 0x00000100 1817 #define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200 1818 #define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400 1819 #define IXGBE_TCPTIMER_LOOP 0x00000800 1820 #define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF 1821 1822 /* HLREG0 Bit Masks */ 1823 #define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */ 1824 #define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */ 1825 #define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */ 1826 #define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */ 1827 #define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */ 1828 #define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */ 1829 #define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */ 1830 #define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */ 1831 #define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */ 1832 #define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */ 1833 #define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */ 1834 #define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */ 1835 #define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */ 1836 #define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */ 1837 #define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */ 1838 1839 /* VMD_CTL bitmasks */ 1840 #define IXGBE_VMD_CTL_VMDQ_EN 0x00000001 1841 #define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002 1842 1843 /* VT_CTL bitmasks */ 1844 #define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */ 1845 #define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */ 1846 #define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */ 1847 #define IXGBE_VT_CTL_POOL_SHIFT 7 1848 #define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT) 1849 1850 /* VMOLR bitmasks */ 1851 #define IXGBE_VMOLR_UPE 0x00400000 /* unicast promiscuous */ 1852 #define IXGBE_VMOLR_VPE 0x00800000 /* VLAN promiscuous */ 1853 #define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */ 1854 #define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */ 1855 #define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */ 1856 #define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */ 1857 #define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */ 1858 1859 /* VFRE bitmask */ 1860 #define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF 1861 1862 #define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 1863 1864 /* RDHMPN and TDHMPN bitmasks */ 1865 #define IXGBE_RDHMPN_RDICADDR 0x007FF800 1866 #define IXGBE_RDHMPN_RDICRDREQ 0x00800000 1867 #define IXGBE_RDHMPN_RDICADDR_SHIFT 11 1868 #define IXGBE_TDHMPN_TDICADDR 0x003FF800 1869 #define IXGBE_TDHMPN_TDICRDREQ 0x00800000 1870 #define IXGBE_TDHMPN_TDICADDR_SHIFT 11 1871 1872 #define IXGBE_RDMAM_MEM_SEL_SHIFT 13 1873 #define IXGBE_RDMAM_DWORD_SHIFT 9 1874 #define IXGBE_RDMAM_DESC_COMP_FIFO 1 1875 #define IXGBE_RDMAM_DFC_CMD_FIFO 2 1876 #define IXGBE_RDMAM_RSC_HEADER_ADDR 3 1877 #define IXGBE_RDMAM_TCN_STATUS_RAM 4 1878 #define IXGBE_RDMAM_WB_COLL_FIFO 5 1879 #define IXGBE_RDMAM_QSC_CNT_RAM 6 1880 #define IXGBE_RDMAM_QSC_FCOE_RAM 7 1881 #define IXGBE_RDMAM_QSC_QUEUE_CNT 8 1882 #define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA 1883 #define IXGBE_RDMAM_QSC_RSC_RAM 0xB 1884 #define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135 1885 #define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4 1886 #define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48 1887 #define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7 1888 #define IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE 32 1889 #define IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT 4 1890 #define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256 1891 #define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9 1892 #define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8 1893 #define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4 1894 #define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64 1895 #define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4 1896 #define IXGBE_RDMAM_QSC_FCOE_RAM_RANGE 512 1897 #define IXGBE_RDMAM_QSC_FCOE_RAM_COUNT 5 1898 #define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32 1899 #define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4 1900 #define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128 1901 #define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8 1902 #define IXGBE_RDMAM_QSC_RSC_RAM_RANGE 32 1903 #define IXGBE_RDMAM_QSC_RSC_RAM_COUNT 8 1904 1905 #define IXGBE_TXDESCIC_READY 0x80000000 1906 1907 /* Receive Checksum Control */ 1908 #define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 1909 #define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 1910 1911 /* FCRTL Bit Masks */ 1912 #define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */ 1913 #define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */ 1914 1915 /* PAP bit masks*/ 1916 #define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */ 1917 #define IXGBE_PAP_PACE_MASK 0x000F0000 /* Pace bit mask */ 1918 1919 /* RMCS Bit Masks */ 1920 #define IXGBE_RMCS_RRM 0x00000002 /* Rx Recycle Mode enable */ 1921 /* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 1922 #define IXGBE_RMCS_RAC 0x00000004 1923 /* Deficit Fixed Prio ena */ 1924 #define IXGBE_RMCS_DFP IXGBE_RMCS_RAC 1925 #define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */ 1926 #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */ 1927 #define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 1928 1929 /* FCCFG Bit Masks */ 1930 #define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */ 1931 #define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */ 1932 1933 /* Interrupt register bitmasks */ 1934 1935 /* Extended Interrupt Cause Read */ 1936 #define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */ 1937 #define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */ 1938 #define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */ 1939 #define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */ 1940 #define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */ 1941 #define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */ 1942 #define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */ 1943 #define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */ 1944 #define IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */ 1945 #define IXGBE_EICR_TIMESYNC 0x01000000 /* Timesync Event */ 1946 #define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */ 1947 #define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */ 1948 #define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */ 1949 #define IXGBE_EICR_ECC 0x10000000 /* ECC Error */ 1950 #define IXGBE_EICR_GPI_SDP0_X540 0x02000000 /* Gen Purpose Interrupt on SDP0 */ 1951 #define IXGBE_EICR_GPI_SDP1_X540 0x04000000 /* Gen Purpose Interrupt on SDP1 */ 1952 #define IXGBE_EICR_GPI_SDP2_X540 0x08000000 /* Gen Purpose Interrupt on SDP2 */ 1953 #define IXGBE_EICR_GPI_SDP0_X550 IXGBE_EICR_GPI_SDP0_X540 1954 #define IXGBE_EICR_GPI_SDP1_X550 IXGBE_EICR_GPI_SDP1_X540 1955 #define IXGBE_EICR_GPI_SDP2_X550 IXGBE_EICR_GPI_SDP2_X540 1956 #define IXGBE_EICR_GPI_SDP0_X550EM_x IXGBE_EICR_GPI_SDP0_X540 1957 #define IXGBE_EICR_GPI_SDP1_X550EM_x IXGBE_EICR_GPI_SDP1_X540 1958 #define IXGBE_EICR_GPI_SDP2_X550EM_x IXGBE_EICR_GPI_SDP2_X540 1959 #define IXGBE_EICR_GPI_SDP0_X550EM_a IXGBE_EICR_GPI_SDP0_X540 1960 #define IXGBE_EICR_GPI_SDP1_X550EM_a IXGBE_EICR_GPI_SDP1_X540 1961 #define IXGBE_EICR_GPI_SDP2_X550EM_a IXGBE_EICR_GPI_SDP2_X540 1962 #define IXGBE_EICR_GPI_SDP0_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP0) 1963 #define IXGBE_EICR_GPI_SDP1_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP1) 1964 #define IXGBE_EICR_GPI_SDP2_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP2) 1965 1966 #define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */ 1967 #define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */ 1968 #define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 1969 #define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 1970 1971 /* Extended Interrupt Cause Set */ 1972 #define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1973 #define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1974 #define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */ 1975 #define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */ 1976 #define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1977 #define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */ 1978 #define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1979 #define IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 1980 #define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1981 #define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1982 #define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1983 #define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */ 1984 #define IXGBE_EICS_GPI_SDP0_BY_MAC(_hw) IXGBE_EICR_GPI_SDP0_BY_MAC(_hw) 1985 #define IXGBE_EICS_GPI_SDP1_BY_MAC(_hw) IXGBE_EICR_GPI_SDP1_BY_MAC(_hw) 1986 #define IXGBE_EICS_GPI_SDP2_BY_MAC(_hw) IXGBE_EICR_GPI_SDP2_BY_MAC(_hw) 1987 #define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1988 #define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */ 1989 #define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1990 #define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1991 1992 /* Extended Interrupt Mask Set */ 1993 #define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1994 #define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1995 #define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ 1996 #define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */ 1997 #define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1998 #define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */ 1999 #define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 2000 #define IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermal Sensor Event */ 2001 #define IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 2002 #define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 2003 #define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 2004 #define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 2005 #define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */ 2006 #define IXGBE_EIMS_GPI_SDP0_BY_MAC(_hw) IXGBE_EICR_GPI_SDP0_BY_MAC(_hw) 2007 #define IXGBE_EIMS_GPI_SDP1_BY_MAC(_hw) IXGBE_EICR_GPI_SDP1_BY_MAC(_hw) 2008 #define IXGBE_EIMS_GPI_SDP2_BY_MAC(_hw) IXGBE_EICR_GPI_SDP2_BY_MAC(_hw) 2009 #define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 2010 #define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */ 2011 #define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 2012 /* 2013 * EIMS_OTHER is R/W on 82598 though the document says it's reserved. 2014 * It MUST be required to set this bit to get OTHER interrupt. 2015 * 2016 * On other chips, it's read only. It's set if any bits of 29..16 is not zero. 2017 * Bit 30 (TCP_TIMER) doesn't affect to EIMS_OTHER. 2018 */ 2019 #define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 2020 2021 /* Extended Interrupt Mask Clear */ 2022 #define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 2023 #define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 2024 #define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ 2025 #define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */ 2026 #define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 2027 #define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */ 2028 #define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 2029 #define IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 2030 #define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 2031 #define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 2032 #define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 2033 #define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */ 2034 #define IXGBE_EIMC_GPI_SDP0_BY_MAC(_hw) IXGBE_EICR_GPI_SDP0_BY_MAC(_hw) 2035 #define IXGBE_EIMC_GPI_SDP1_BY_MAC(_hw) IXGBE_EICR_GPI_SDP1_BY_MAC(_hw) 2036 #define IXGBE_EIMC_GPI_SDP2_BY_MAC(_hw) IXGBE_EICR_GPI_SDP2_BY_MAC(_hw) 2037 #define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 2038 #define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */ 2039 #define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 2040 /* EIMC_OTHER works only on 82598. See EIMS_OTHER's comment */ 2041 #define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 2042 2043 #define IXGBE_EIMS_ENABLE_MASK ( \ 2044 IXGBE_EIMS_RTX_QUEUE | \ 2045 IXGBE_EIMS_LSC | \ 2046 IXGBE_EIMS_TCP_TIMER | \ 2047 IXGBE_EIMS_OTHER) 2048 2049 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 2050 #define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ 2051 #define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ 2052 #define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 2053 #define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ 2054 #define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ 2055 #define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ 2056 #define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ 2057 #define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 2058 #define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 2059 #define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */ 2060 #define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */ 2061 #define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */ 2062 #define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */ 2063 #define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */ 2064 #define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */ 2065 #define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */ 2066 #define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */ 2067 #define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass chk of ctrl bits */ 2068 #define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */ 2069 #define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */ 2070 #define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */ 2071 #define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */ 2072 #define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */ 2073 2074 #define IXGBE_MAX_FTQF_FILTERS 128 2075 #define IXGBE_FTQF_PROTOCOL_MASK 0x00000003 2076 #define IXGBE_FTQF_PROTOCOL_TCP 0x00000000 2077 #define IXGBE_FTQF_PROTOCOL_UDP 0x00000001 2078 #define IXGBE_FTQF_PROTOCOL_SCTP 2 2079 #define IXGBE_FTQF_PRIORITY_MASK 0x00000007 2080 #define IXGBE_FTQF_PRIORITY_SHIFT 2 2081 #define IXGBE_FTQF_POOL_MASK 0x0000003F 2082 #define IXGBE_FTQF_POOL_SHIFT 8 2083 #define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F 2084 #define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25 2085 #define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E 2086 #define IXGBE_FTQF_DEST_ADDR_MASK 0x1D 2087 #define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B 2088 #define IXGBE_FTQF_DEST_PORT_MASK 0x17 2089 #define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F 2090 #define IXGBE_FTQF_POOL_MASK_EN 0x40000000 2091 #define IXGBE_FTQF_QUEUE_ENABLE 0x80000000 2092 2093 /* Interrupt clear mask */ 2094 #define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF 2095 #define IXGBE_MSIX_OTHER_CLEAR_MASK 0xFFFF0000 2096 2097 /* Interrupt Vector Allocation Registers */ 2098 #define IXGBE_IVAR_REG_NUM 25 2099 #define IXGBE_IVAR_REG_NUM_82599 64 2100 #define IXGBE_IVAR_TXRX_ENTRY 96 2101 #define IXGBE_IVAR_RX_ENTRY 64 2102 #define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i)) 2103 #define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i)) 2104 #define IXGBE_IVAR_TX_ENTRY 32 2105 2106 #define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */ 2107 #define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */ 2108 2109 #define IXGBE_MSIX_VECTOR(_i) (0 + (_i)) 2110 2111 #define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 2112 2113 /* ETYPE Queue Filter/Select Bit Masks */ 2114 #define IXGBE_MAX_ETQF_FILTERS 8 2115 #define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */ 2116 #define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */ 2117 #define IXGBE_ETQF_TX_ANTISPOOF 0x20000000 /* bit 29 */ 2118 #define IXGBE_ETQF_1588 0x40000000 /* bit 30 */ 2119 #define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */ 2120 #define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */ 2121 #define IXGBE_ETQF_POOL_SHIFT 20 2122 2123 #define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */ 2124 #define IXGBE_ETQS_RX_QUEUE_SHIFT 16 2125 #define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */ 2126 #define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */ 2127 2128 /* 2129 * ETQF filter list: one static filter per filter consumer. This is 2130 * to avoid filter collisions later. Add new filters 2131 * here!! 2132 * 2133 * Current filters: 2134 * EAPOL 802.1x (0x888e): Filter 0 2135 * FCoE (0x8906): Filter 2 2136 * 1588 (0x88f7): Filter 3 2137 * FIP (0x8914): Filter 4 2138 * LLDP (0x88CC): Filter 5 2139 * LACP (0x8809): Filter 6 2140 * FC (0x8808): Filter 7 2141 */ 2142 #define IXGBE_ETQF_FILTER_EAPOL 0 2143 #define IXGBE_ETQF_FILTER_FCOE 2 2144 #define IXGBE_ETQF_FILTER_1588 3 2145 #define IXGBE_ETQF_FILTER_FIP 4 2146 #define IXGBE_ETQF_FILTER_LLDP 5 2147 #define IXGBE_ETQF_FILTER_LACP 6 2148 #define IXGBE_ETQF_FILTER_FC 7 2149 /* VLAN Control Bit Masks */ 2150 #define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */ 2151 #define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */ 2152 #define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */ 2153 #define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */ 2154 #define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */ 2155 2156 /* VLAN pool filtering masks */ 2157 #define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */ 2158 #define IXGBE_VLVF_ENTRIES 64 2159 #define IXGBE_VLVF_VLANID_MASK 0x00000FFF 2160 /* Per VF Port VLAN insertion rules */ 2161 #define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ 2162 #define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ 2163 2164 #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */ 2165 2166 /* STATUS Bit Masks */ 2167 #define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ 2168 #define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/ 2169 #define IXGBE_STATUS_GIO 0x00080000 /* GIO Primary Ena Status */ 2170 2171 #define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */ 2172 #define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */ 2173 2174 /* ESDP Bit Masks */ 2175 #define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */ 2176 #define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */ 2177 #define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */ 2178 #define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */ 2179 #define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */ 2180 #define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */ 2181 #define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */ 2182 #define IXGBE_ESDP_SDP7 0x00000080 /* SDP7 Data Value */ 2183 #define IXGBE_ESDP_SDP0_DIR 0x00000100 /* SDP0 IO direction */ 2184 #define IXGBE_ESDP_SDP1_DIR 0x00000200 /* SDP1 IO direction */ 2185 #define IXGBE_ESDP_SDP2_DIR 0x00000400 /* SDP1 IO direction */ 2186 #define IXGBE_ESDP_SDP3_DIR 0x00000800 /* SDP3 IO direction */ 2187 #define IXGBE_ESDP_SDP4_DIR 0x00001000 /* SDP4 IO direction */ 2188 #define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */ 2189 #define IXGBE_ESDP_SDP6_DIR 0x00004000 /* SDP6 IO direction */ 2190 #define IXGBE_ESDP_SDP7_DIR 0x00008000 /* SDP7 IO direction */ 2191 #define IXGBE_ESDP_SDP0_NATIVE 0x00010000 /* SDP0 IO mode */ 2192 #define IXGBE_ESDP_SDP1_NATIVE 0x00020000 /* SDP1 IO mode */ 2193 2194 2195 /* LEDCTL Bit Masks */ 2196 #define IXGBE_LED_IVRT_BASE 0x00000040 2197 #define IXGBE_LED_BLINK_BASE 0x00000080 2198 #define IXGBE_LED_MODE_MASK_BASE 0x0000000F 2199 #define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i))) 2200 #define IXGBE_LED_MODE_SHIFT(_i) (8*(_i)) 2201 #define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i) 2202 #define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i) 2203 #define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i) 2204 #define IXGBE_X557_LED_MANUAL_SET_MASK (1 << 8) 2205 #define IXGBE_X557_MAX_LED_INDEX 3 2206 #define IXGBE_X557_LED_PROVISIONING 0xC430 2207 2208 /* LED modes */ 2209 #define IXGBE_LED_LINK_UP 0x0 2210 #define IXGBE_LED_LINK_10G 0x1 2211 #define IXGBE_LED_MAC 0x2 2212 #define IXGBE_LED_FILTER 0x3 2213 #define IXGBE_LED_LINK_ACTIVE 0x4 2214 #define IXGBE_LED_LINK_1G 0x5 2215 #define IXGBE_LED_ON 0xE 2216 #define IXGBE_LED_OFF 0xF 2217 2218 /* AUTOC Bit Masks */ 2219 #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000 2220 #define IXGBE_AUTOC_KX4_SUPP 0x80000000 2221 #define IXGBE_AUTOC_KX_SUPP 0x40000000 2222 #define IXGBE_AUTOC_PAUSE 0x30000000 2223 #define IXGBE_AUTOC_ASM_PAUSE 0x20000000 2224 #define IXGBE_AUTOC_SYM_PAUSE 0x10000000 2225 #define IXGBE_AUTOC_RF 0x08000000 2226 #define IXGBE_AUTOC_PD_TMR 0x06000000 2227 #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 2228 #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000 2229 #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000 2230 #define IXGBE_AUTOC_FECA 0x00040000 2231 #define IXGBE_AUTOC_FECR 0x00020000 2232 #define IXGBE_AUTOC_KR_SUPP 0x00010000 2233 #define IXGBE_AUTOC_AN_RESTART 0x00001000 2234 #define IXGBE_AUTOC_FLU 0x00000001 2235 #define IXGBE_AUTOC_LMS_SHIFT 13 2236 #define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT) 2237 #define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT) 2238 #define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT) 2239 #define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 2240 #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT) 2241 #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT) 2242 #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT) 2243 #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT) 2244 #define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT) 2245 #define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT) 2246 #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 2247 #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 2248 2249 #define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200 2250 #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 2251 #define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180 2252 #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 2253 #define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 2254 #define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 2255 #define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 2256 #define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 2257 #define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 2258 #define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 2259 #define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 2260 2261 #define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000 2262 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000 2263 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16 2264 #define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 2265 #define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 2266 #define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 2267 #define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK 0x50000000 2268 #define IXGBE_AUTOC2_LINK_DISABLE_MASK 0x70000000 2269 2270 #define IXGBE_MACC_FLU 0x00000001 2271 #define IXGBE_MACC_FSV_10G 0x00030000 2272 #define IXGBE_MACC_FS 0x00040000 2273 #define IXGBE_MAC_RX2TX_LPBK 0x00000002 2274 2275 /* Veto Bit definition */ 2276 #define IXGBE_MMNGC_MNG_VETO 0x00000001 2277 2278 /* LINKS Bit Masks */ 2279 #define IXGBE_LINKS_KX_AN_COMP 0x80000000 2280 #define IXGBE_LINKS_UP 0x40000000 2281 #define IXGBE_LINKS_SPEED 0x20000000 2282 #define IXGBE_LINKS_MODE 0x18000000 2283 #define IXGBE_LINKS_RX_MODE 0x06000000 2284 #define IXGBE_LINKS_TX_MODE 0x01800000 2285 #define IXGBE_LINKS_XGXS_EN 0x00400000 2286 #define IXGBE_LINKS_SGMII_EN 0x02000000 2287 #define IXGBE_LINKS_PCS_1G_EN 0x00200000 2288 #define IXGBE_LINKS_1G_AN_EN 0x00100000 2289 #define IXGBE_LINKS_KX_AN_IDLE 0x00080000 2290 #define IXGBE_LINKS_1G_SYNC 0x00040000 2291 #define IXGBE_LINKS_10G_ALIGN 0x00020000 2292 #define IXGBE_LINKS_10G_LANE_SYNC 0x00017000 2293 #define IXGBE_LINKS_TL_FAULT 0x00001000 2294 #define IXGBE_LINKS_SIGNAL 0x00000F00 2295 2296 #define IXGBE_LINKS_SPEED_NON_STD 0x08000000 2297 #define IXGBE_LINKS_SPEED_82599 0x30000000 2298 #define IXGBE_LINKS_SPEED_10G_82599 0x30000000 2299 #define IXGBE_LINKS_SPEED_1G_82599 0x20000000 2300 #define IXGBE_LINKS_SPEED_100_82599 0x10000000 2301 #define IXGBE_LINKS_SPEED_10_X550EM_A 0x00000000 2302 #define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ 2303 #define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 2304 2305 #define IXGBE_LINKS2_AN_SUPPORTED 0x00000040 2306 2307 /* PCS1GLSTA Bit Masks */ 2308 #define IXGBE_PCS1GLSTA_LINK_OK 1 2309 #define IXGBE_PCS1GLSTA_SYNK_OK 0x10 2310 #define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000 2311 #define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000 2312 #define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000 2313 #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000 2314 #define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000 2315 2316 #define IXGBE_PCS1GANA_SYM_PAUSE 0x80 2317 #define IXGBE_PCS1GANA_ASM_PAUSE 0x100 2318 2319 /* PCS1GLCTL Bit Masks */ 2320 #define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */ 2321 #define IXGBE_PCS1GLCTL_FLV_LINK_UP 1 2322 #define IXGBE_PCS1GLCTL_FORCE_LINK 0x20 2323 #define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40 2324 #define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000 2325 #define IXGBE_PCS1GLCTL_AN_RESTART 0x20000 2326 2327 /* ANLP1 Bit Masks */ 2328 #define IXGBE_ANLP1_PAUSE 0x0C00 2329 #define IXGBE_ANLP1_SYM_PAUSE 0x0400 2330 #define IXGBE_ANLP1_ASM_PAUSE 0x0800 2331 #define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000 2332 2333 /* SW Semaphore Register bitmasks */ 2334 #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 2335 #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 2336 #define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 2337 #define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */ 2338 2339 /* SW_FW_SYNC/GSSR definitions */ 2340 #define IXGBE_GSSR_EEP_SM 0x0001 2341 #define IXGBE_GSSR_PHY0_SM 0x0002 2342 #define IXGBE_GSSR_PHY1_SM 0x0004 2343 #define IXGBE_GSSR_MAC_CSR_SM 0x0008 2344 #define IXGBE_GSSR_FLASH_SM 0x0010 2345 #define IXGBE_GSSR_NVM_UPDATE_SM 0x0200 2346 #define IXGBE_GSSR_SW_MNG_SM 0x0400 2347 #define IXGBE_GSSR_TOKEN_SM 0x40000000 /* SW bit for shared access */ 2348 #define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys and both I2Cs */ 2349 #define IXGBE_GSSR_I2C_MASK 0x1800 2350 #define IXGBE_GSSR_NVM_PHY_MASK 0xF 2351 2352 /* FW Status register bitmask */ 2353 #define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */ 2354 2355 /* EEC Register */ 2356 #define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */ 2357 #define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */ 2358 #define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */ 2359 #define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */ 2360 #define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */ 2361 #define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */ 2362 #define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */ 2363 #define IXGBE_EEC_FWE_SHIFT 4 2364 #define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */ 2365 #define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */ 2366 #define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */ 2367 #define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */ 2368 #define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */ 2369 #define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */ 2370 #define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */ 2371 /* EEPROM Addressing bits based on type (0-small, 1-large) */ 2372 #define IXGBE_EEC_ADDR_SIZE 0x00000400 2373 #define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */ 2374 #define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD allows 14 bits for addr. */ 2375 2376 #define IXGBE_EEC_SIZE_SHIFT 11 2377 #define IXGBE_EEPROM_WORD_SIZE_SHIFT 6 2378 #define IXGBE_EEPROM_OPCODE_BITS 8 2379 2380 /* FLA Register */ 2381 #define IXGBE_FLA_LOCKED 0x00000040 2382 2383 /* Part Number String Length */ 2384 #define IXGBE_PBANUM_LENGTH 11 2385 2386 /* Checksum and EEPROM pointers */ 2387 #define IXGBE_PBANUM_PTR_GUARD 0xFAFA 2388 #define IXGBE_EEPROM_CHECKSUM 0x3F 2389 #define IXGBE_EEPROM_SUM 0xBABA 2390 #define IXGBE_EEPROM_CTRL_4 0x45 2391 #define IXGBE_EE_CTRL_4_INST_ID 0x10 2392 #define IXGBE_EE_CTRL_4_INST_ID_SHIFT 4 2393 #define IXGBE_PCIE_ANALOG_PTR 0x03 2394 #define IXGBE_ATLAS0_CONFIG_PTR 0x04 2395 #define IXGBE_PHY_PTR 0x04 2396 #define IXGBE_ATLAS1_CONFIG_PTR 0x05 2397 #define IXGBE_OPTION_ROM_PTR 0x05 2398 #define IXGBE_PCIE_GENERAL_PTR 0x06 2399 #define IXGBE_PCIE_CONFIG0_PTR 0x07 2400 #define IXGBE_PCIE_CONFIG1_PTR 0x08 2401 #define IXGBE_CORE0_PTR 0x09 2402 #define IXGBE_CORE1_PTR 0x0A 2403 #define IXGBE_MAC0_PTR 0x0B 2404 #define IXGBE_MAC1_PTR 0x0C 2405 #define IXGBE_CSR0_CONFIG_PTR 0x0D 2406 #define IXGBE_CSR1_CONFIG_PTR 0x0E 2407 #define IXGBE_PCIE_ANALOG_PTR_X550 0x02 2408 #define IXGBE_SHADOW_RAM_SIZE_X550 0x4000 2409 #define IXGBE_IXGBE_PCIE_GENERAL_SIZE 0x24 2410 #define IXGBE_PCIE_CONFIG_SIZE 0x08 2411 #define IXGBE_EEPROM_LAST_WORD 0x41 2412 #define IXGBE_FW_PTR 0x0F 2413 #define IXGBE_PBANUM0_PTR 0x15 2414 #define IXGBE_PBANUM1_PTR 0x16 2415 #define IXGBE_NVM_IMAGE_VER 0x18 2416 #define IXGBE_PHYFW_REV 0x19 2417 #define IXGBE_ALT_MAC_ADDR_PTR 0x37 2418 #define IXGBE_FREE_SPACE_PTR 0X3E 2419 2420 #if defined(PREBOOT_SUPPORT) || defined(QV_RELEASE) 2421 /* Minimum Rollback Revision offsets */ 2422 #define IXGBE_MINRREV_PHY_ANALOG_LO 0x46 2423 #define IXGBE_MINRREV_PHY_ANALOG_HI 0x47 2424 #define IXGBE_MINRREV_OROM_LO 0x48 2425 #define IXGBE_MINRREV_OROM_HI 0x49 2426 #define IXGBE_MINRREV_FW_LO 0x4A 2427 #define IXGBE_MINRREV_FW_HI 0x4B 2428 #endif /* PREBOOT_SUPPORT || QV_RELEASE*/ 2429 2430 2431 2432 #define IXGBE_SAN_MAC_ADDR_PTR 0x28 2433 #define IXGBE_NVM_MAP_VER 0x29 2434 #define IXGBE_OEM_NVM_IMAGE_VER 0x2A 2435 #define IXGBE_DEVICE_CAPS 0x2C 2436 #define IXGBE_ETRACKID_L 0x2D 2437 #define IXGBE_ETRACKID_H 0x2E 2438 #define IXGBE_82599_SERIAL_NUMBER_MAC_ADDR 0x11 2439 #define IXGBE_X550_SERIAL_NUMBER_MAC_ADDR 0x04 2440 2441 #define IXGBE_PCIE_MSIX_82599_CAPS 0x72 2442 #define IXGBE_MAX_MSIX_VECTORS_82599 0x40 2443 #define IXGBE_PCIE_MSIX_82598_CAPS 0x62 2444 #define IXGBE_MAX_MSIX_VECTORS_82598 0x13 2445 2446 /* MSI-X capability fields masks */ 2447 #define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF 2448 2449 /* Legacy EEPROM word offsets */ 2450 #define IXGBE_ISCSI_BOOT_CAPS 0x0033 2451 #define IXGBE_ISCSI_SETUP_PORT_0 0x0030 2452 #define IXGBE_ISCSI_SETUP_PORT_1 0x0034 2453 2454 /* EEPROM Commands - SPI */ 2455 #define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */ 2456 #define IXGBE_EEPROM_STATUS_RDY_SPI 0x01 2457 #define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 2458 #define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 2459 #define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */ 2460 #define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */ 2461 /* EEPROM reset Write Enable latch */ 2462 #define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04 2463 #define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */ 2464 #define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */ 2465 #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ 2466 #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ 2467 #define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 2468 2469 /* EEPROM Read Register */ 2470 #define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */ 2471 #define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */ 2472 #define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */ 2473 #define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 2474 #define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for wr complete */ 2475 #define IXGBE_NVM_POLL_READ 0 /* Flag for polling for rd complete */ 2476 2477 #define NVM_INIT_CTRL_3 0x38 2478 #define NVM_INIT_CTRL_3_LPLU 0x8 2479 #define NVM_INIT_CTRL_3_D10GMP_PORT0 0x40 2480 #define NVM_INIT_CTRL_3_D10GMP_PORT1 0x100 2481 2482 #define IXGBE_ETH_LENGTH_OF_ADDRESS ETHER_ADDR_LEN 2483 2484 #define IXGBE_EEPROM_PAGE_SIZE_MAX 128 2485 #define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 256 /* words rd in burst */ 2486 #define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* words wr in burst */ 2487 #define IXGBE_EEPROM_CTRL_2 1 /* EEPROM CTRL word 2 */ 2488 #define IXGBE_EEPROM_CCD_BIT 2 2489 2490 #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS 2491 #define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM attempts to gain grant */ 2492 #endif 2493 2494 /* Number of 5 microseconds we wait for EERD read and 2495 * EERW write to complete */ 2496 #define IXGBE_EERD_EEWR_ATTEMPTS 100000 2497 2498 /* # attempts we wait for flush update to complete */ 2499 #define IXGBE_FLUDONE_ATTEMPTS 20000 2500 2501 #define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */ 2502 #define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */ 2503 #define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */ 2504 #define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */ 2505 2506 #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0 2507 #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3 2508 #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1 2509 #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2 2510 #define IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR (1 << 7) 2511 #define IXGBE_FW_LESM_PARAMETERS_PTR 0x2 2512 #define IXGBE_FW_LESM_STATE_1 0x1 2513 #define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */ 2514 #define IXGBE_FW_LESM_2_STATES_ENABLED_MASK 0x1F 2515 #define IXGBE_FW_LESM_2_STATES_ENABLED 0x12 2516 #define IXGBE_FW_LESM_STATE0_10G_ENABLED 0x6FFF 2517 #define IXGBE_FW_LESM_STATE1_10G_ENABLED 0x4FFF 2518 #define IXGBE_FW_LESM_STATE0_10G_DISABLED 0x0FFF 2519 #define IXGBE_FW_LESM_STATE1_10G_DISABLED 0x2FFF 2520 #define IXGBE_FW_LESM_PORT0_STATE0_OFFSET 0x2 2521 #define IXGBE_FW_LESM_PORT0_STATE1_OFFSET 0x3 2522 #define IXGBE_FW_LESM_PORT1_STATE0_OFFSET 0x6 2523 #define IXGBE_FW_LESM_PORT1_STATE1_OFFSET 0x7 2524 #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4 2525 #define IXGBE_FW_PATCH_VERSION_4 0x7 2526 #define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */ 2527 #define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */ 2528 #define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */ 2529 #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */ 2530 #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */ 2531 #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */ 2532 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt SAN MAC capability */ 2533 #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt SAN MAC 0 offset */ 2534 #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt SAN MAC 1 offset */ 2535 #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt WWNN prefix offset */ 2536 #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt WWPN prefix offset */ 2537 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt SAN MAC exists */ 2538 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt WWN base exists */ 2539 2540 /* FW header offset */ 2541 #define IXGBE_X540_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4 2542 #define IXGBE_X540_FW_MODULE_MASK 0x7FFF 2543 /* 4KB multiplier */ 2544 #define IXGBE_X540_FW_MODULE_LENGTH 0x1000 2545 /* version word 2 (month & day) */ 2546 #define IXGBE_X540_FW_PATCH_VERSION_2 0x5 2547 /* version word 3 (silicon compatibility & year) */ 2548 #define IXGBE_X540_FW_PATCH_VERSION_3 0x6 2549 /* version word 4 (major & minor numbers) */ 2550 #define IXGBE_X540_FW_PATCH_VERSION_4 0x7 2551 2552 #define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4 /* WoL supported on ports 0 & 1 */ 2553 #define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8 /* WoL supported on port 0 */ 2554 #define IXGBE_DEVICE_CAPS_WOL_MASK 0xC /* Mask for WoL capabilities */ 2555 2556 #define IXGBE_DEVICE_CAPS_FLAGS "\20" \ 2557 "\1ALLOW_ANY_SFP" "\2FCOE_OFFLOAD" "\3WOL_PORT0_1" "\4WOL_PORT0" \ 2558 "\10NO_CROSSTALK_WR" 2559 2560 /* PCI Bus Info */ 2561 #define IXGBE_PCI_DEVICE_STATUS 0xAA 2562 #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020 2563 #define IXGBE_PCI_LINK_STATUS 0xB2 2564 #define IXGBE_PCI_DEVICE_CONTROL2 0xC8 2565 #define IXGBE_PCI_LINK_WIDTH 0x3F0 2566 #define IXGBE_PCI_LINK_WIDTH_1 0x10 2567 #define IXGBE_PCI_LINK_WIDTH_2 0x20 2568 #define IXGBE_PCI_LINK_WIDTH_4 0x40 2569 #define IXGBE_PCI_LINK_WIDTH_8 0x80 2570 #define IXGBE_PCI_LINK_SPEED 0xF 2571 #define IXGBE_PCI_LINK_SPEED_2500 0x1 2572 #define IXGBE_PCI_LINK_SPEED_5000 0x2 2573 #define IXGBE_PCI_LINK_SPEED_8000 0x3 2574 #define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E 2575 #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80 2576 #define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005 2577 2578 #define IXGBE_PCIDEVCTRL2_TIMEO_MASK 0xf 2579 #define IXGBE_PCIDEVCTRL2_16_32ms_def 0x0 2580 #define IXGBE_PCIDEVCTRL2_50_100us 0x1 2581 #define IXGBE_PCIDEVCTRL2_1_2ms 0x2 2582 #define IXGBE_PCIDEVCTRL2_16_32ms 0x5 2583 #define IXGBE_PCIDEVCTRL2_65_130ms 0x6 2584 #define IXGBE_PCIDEVCTRL2_260_520ms 0x9 2585 #define IXGBE_PCIDEVCTRL2_1_2s 0xa 2586 #define IXGBE_PCIDEVCTRL2_4_8s 0xd 2587 #define IXGBE_PCIDEVCTRL2_17_34s 0xe 2588 2589 /* Number of 100 microseconds we wait for PCI Express primary disable */ 2590 #define IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT 800 2591 2592 /* Check whether address is multicast. This is little-endian specific check.*/ 2593 #define IXGBE_IS_MULTICAST(Address) \ 2594 (bool)(((u8 *)(Address))[0] & ((u8)0x01)) 2595 2596 /* Check whether an address is broadcast. */ 2597 #define IXGBE_IS_BROADCAST(Address) \ 2598 ((((u8 *)(Address))[0] == ((u8)0xff)) && \ 2599 (((u8 *)(Address))[1] == ((u8)0xff))) 2600 2601 /* RAH */ 2602 #define IXGBE_RAH_VIND_MASK 0x003C0000 2603 #define IXGBE_RAH_VIND_SHIFT 18 2604 #define IXGBE_RAH_AV 0x80000000 2605 #define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF 2606 2607 /* Header split receive */ 2608 #define IXGBE_RFCTL_ISCSI_DIS 0x00000001 2609 #define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E 2610 #define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1 2611 #define IXGBE_RFCTL_RSC_DIS 0x00000020 2612 #define IXGBE_RFCTL_NFSW_DIS 0x00000040 2613 #define IXGBE_RFCTL_NFSR_DIS 0x00000080 2614 #define IXGBE_RFCTL_NFS_VER_MASK 0x00000300 2615 #define IXGBE_RFCTL_NFS_VER_SHIFT 8 2616 #define IXGBE_RFCTL_NFS_VER_2 0 2617 #define IXGBE_RFCTL_NFS_VER_3 1 2618 #define IXGBE_RFCTL_NFS_VER_4 2 2619 #define IXGBE_RFCTL_IPV6_DIS 0x00000400 2620 #define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800 2621 #define IXGBE_RFCTL_IPFRSP_DIS 0x00004000 2622 #define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000 2623 #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 2624 2625 /* Transmit Config masks */ 2626 #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Ena specific Tx Queue */ 2627 #define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wr-bk flushing */ 2628 #define IXGBE_TXDCTL_WTHRESH_MASK 0x007f0000 2629 #define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ 2630 /* Enable short packet padding to 64 bytes */ 2631 #define IXGBE_TX_PAD_ENABLE 0x00000400 2632 #define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */ 2633 /* This allows for 16K packets + 4k for vlan */ 2634 #define IXGBE_MAX_FRAME_SZ 0x40040000 2635 2636 #define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */ 2637 #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */ 2638 2639 /* Receive Config masks */ 2640 #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ 2641 #define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Desc Monitor Bypass */ 2642 #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Ena specific Rx Queue */ 2643 #define IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc wr-bk flushing */ 2644 #define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* X540 supported only */ 2645 #define IXGBE_RXDCTL_RLPML_EN 0x00008000 2646 #define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */ 2647 2648 #define IXGBE_TSAUXC_EN_CLK 0x00000004 2649 #define IXGBE_TSAUXC_SYNCLK 0x00000008 2650 #define IXGBE_TSAUXC_SDP0_INT 0x00000040 2651 #define IXGBE_TSAUXC_EN_TT0 0x00000001 2652 #define IXGBE_TSAUXC_EN_TT1 0x00000002 2653 #define IXGBE_TSAUXC_ST0 0x00000010 2654 #define IXGBE_TSAUXC_DISABLE_SYSTIME 0x80000000 2655 2656 #define IXGBE_TSSDP_TS_SDP0_SEL_MASK 0x000000C0 2657 #define IXGBE_TSSDP_TS_SDP0_CLK0 0x00000080 2658 #define IXGBE_TSSDP_TS_SDP0_EN 0x00000100 2659 2660 #define IXGBE_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 2661 #define IXGBE_TSYNCTXCTL_ENABLED 0x00000010 /* Tx timestamping enabled */ 2662 2663 #define IXGBE_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 2664 #define IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 2665 #define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00 2666 #define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02 2667 #define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 2668 #define IXGBE_TSYNCRXCTL_TYPE_ALL 0x08 2669 #define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 2670 #define IXGBE_TSYNCRXCTL_ENABLED 0x00000010 /* Rx Timestamping enabled */ 2671 #define IXGBE_TSYNCRXCTL_TSIP_UT_EN 0x00800000 /* Rx Timestamp in Packet */ 2672 #define IXGBE_TSYNCRXCTL_TSIP_UP_MASK 0xFF000000 /* Rx Timestamp UP Mask */ 2673 2674 #define IXGBE_TSIM_SYS_WRAP 0x00000001 2675 #define IXGBE_TSIM_TXTS 0x00000002 2676 #define IXGBE_TSIM_TADJ 0x00000080 2677 2678 #define IXGBE_TSICR_SYS_WRAP IXGBE_TSIM_SYS_WRAP 2679 #define IXGBE_TSICR_TXTS IXGBE_TSIM_TXTS 2680 #define IXGBE_TSICR_TADJ IXGBE_TSIM_TADJ 2681 2682 #define IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF 2683 #define IXGBE_RXMTRL_V1_SYNC_MSG 0x00 2684 #define IXGBE_RXMTRL_V1_DELAY_REQ_MSG 0x01 2685 #define IXGBE_RXMTRL_V1_FOLLOWUP_MSG 0x02 2686 #define IXGBE_RXMTRL_V1_DELAY_RESP_MSG 0x03 2687 #define IXGBE_RXMTRL_V1_MGMT_MSG 0x04 2688 2689 #define IXGBE_RXMTRL_V2_MSGID_MASK 0x0000FF00 2690 #define IXGBE_RXMTRL_V2_SYNC_MSG 0x0000 2691 #define IXGBE_RXMTRL_V2_DELAY_REQ_MSG 0x0100 2692 #define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG 0x0200 2693 #define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300 2694 #define IXGBE_RXMTRL_V2_FOLLOWUP_MSG 0x0800 2695 #define IXGBE_RXMTRL_V2_DELAY_RESP_MSG 0x0900 2696 #define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00 2697 #define IXGBE_RXMTRL_V2_ANNOUNCE_MSG 0x0B00 2698 #define IXGBE_RXMTRL_V2_SIGNALLING_MSG 0x0C00 2699 #define IXGBE_RXMTRL_V2_MGMT_MSG 0x0D00 2700 2701 #define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */ 2702 #define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/ 2703 #define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */ 2704 #define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */ 2705 #define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */ 2706 #define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */ 2707 /* Receive Priority Flow Control Enable */ 2708 #define IXGBE_FCTRL_RPFCE 0x00004000 2709 #define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */ 2710 #define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */ 2711 #define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */ 2712 #define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */ 2713 #define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */ 2714 #define IXGBE_MFLCN_RPFCE_MASK 0x00000FF4 /* Rx Priority FC bitmap mask */ 2715 #define IXGBE_MFLCN_RPFCE_SHIFT 4 /* Rx Priority FC bitmap shift */ 2716 2717 /* Multiple Receive Queue Control */ 2718 #define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */ 2719 #define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */ 2720 #define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */ 2721 #define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */ 2722 #define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */ 2723 #define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */ 2724 #define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */ 2725 #define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */ 2726 #define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */ 2727 #define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */ 2728 #define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */ 2729 #define IXGBE_MRQC_L3L4TXSWEN 0x00008000 /* Enable L3/L4 Tx switch */ 2730 #define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000 2731 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 2732 #define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000 2733 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000 2734 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000 2735 #define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000 2736 #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 2737 #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 2738 #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 2739 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000 2740 #define IXGBE_MRQC_MULTIPLE_RSS 0x00002000 2741 #define IXGBE_MRQC_L3L4TXSWEN 0x00008000 2742 2743 /* Queue Drop Enable */ 2744 #define IXGBE_QDE_ENABLE 0x00000001 2745 #define IXGBE_QDE_HIDE_VLAN 0x00000002 2746 #define IXGBE_QDE_IDX_MASK 0x00007F00 2747 #define IXGBE_QDE_IDX_SHIFT 8 2748 #define IXGBE_QDE_WRITE 0x00010000 2749 #define IXGBE_QDE_READ 0x00020000 2750 2751 #define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 2752 #define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 2753 #define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ 2754 #define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 2755 #define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 2756 #define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ 2757 #define IXGBE_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ 2758 #define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 2759 #define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 2760 2761 #define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000 2762 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000 2763 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 2764 #define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000 2765 #define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000 2766 /* Multiple Transmit Queue Command Register */ 2767 #define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */ 2768 #define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */ 2769 #define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */ 2770 #define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */ 2771 #define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */ 2772 #define IXGBE_MTQC_4TC_4TQ 0x8 /* 4 TC if RT_ENA and VT_ENA */ 2773 #define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */ 2774 2775 /* Receive Descriptor bit definitions */ 2776 #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ 2777 #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ 2778 #define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */ 2779 #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 2780 #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */ 2781 #define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004 2782 #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 2783 #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ 2784 #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 2785 #define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 2786 #define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 2787 #define IXGBE_RXD_STAT_OUTERIPCS 0x100 /* Cloud IP xsum calculated */ 2788 #define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ 2789 #define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 2790 #define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 2791 #define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */ 2792 #define IXGBE_RXD_STAT_TSIP 0x08000 /* Time Stamp in packet buffer */ 2793 #define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */ 2794 #define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */ 2795 #define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */ 2796 #define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 2797 #define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ 2798 #define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ 2799 #define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ 2800 #define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ 2801 #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ 2802 #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ 2803 #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ 2804 #define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */ 2805 #define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */ 2806 #define IXGBE_RXDADV_ERR_OUTERIPER 0x04000000 /* CRC IP Header error */ 2807 #define IXGBE_RXDADV_ERR_RXE 0x20000000 /* Any MAC Error */ 2808 #define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCEOFe/IPE */ 2809 #define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */ 2810 #define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */ 2811 #define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */ 2812 #define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */ 2813 #define IXGBE_RXDADV_ERR_HBO 0x00800000 /* Header Buffer Overflow */ 2814 #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ 2815 #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ 2816 #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ 2817 #define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ 2818 #define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ 2819 #define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ 2820 #define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ 2821 #define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 2822 #define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 2823 #define IXGBE_RXD_PRI_SHIFT 13 2824 #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ 2825 #define IXGBE_RXD_CFI_SHIFT 12 2826 2827 #define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */ 2828 #define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */ 2829 #define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */ 2830 #define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */ 2831 #define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */ 2832 #define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */ 2833 #define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */ 2834 #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */ 2835 #define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */ 2836 #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */ 2837 #define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */ 2838 #define IXGBE_RXDADV_STAT_TS 0x00010000 /* IEEE1588 Time Stamp */ 2839 #define IXGBE_RXDADV_STAT_TSIP 0x00008000 /* Time Stamp in packet buffer */ 2840 2841 /* PSRTYPE bit definitions */ 2842 #define IXGBE_PSRTYPE_TCPHDR 0x00000010 2843 #define IXGBE_PSRTYPE_UDPHDR 0x00000020 2844 #define IXGBE_PSRTYPE_IPV4HDR 0x00000100 2845 #define IXGBE_PSRTYPE_IPV6HDR 0x00000200 2846 #define IXGBE_PSRTYPE_L2HDR 0x00001000 2847 2848 /* SRRCTL bit definitions */ 2849 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ 2850 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* 64byte resolution (>> 6) 2851 * + at bit 8 offset (<< 8) 2852 * = (<< 2) 2853 */ 2854 #define IXGBE_SRRCTL_RDMTS_SHIFT 22 2855 #define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000 2856 #define IXGBE_SRRCTL_DROP_EN 0x10000000 2857 #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F 2858 #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 2859 #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 2860 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 2861 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 2862 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 2863 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 2864 #define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000 2865 2866 #define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000 2867 #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 2868 2869 #define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F 2870 #define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 2871 #define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0 2872 #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 2873 #define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000 2874 #define IXGBE_RXDADV_RSCCNT_SHIFT 17 2875 #define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 2876 #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 2877 #define IXGBE_RXDADV_SPH 0x8000 2878 2879 /* RSS Hash results */ 2880 #define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000 2881 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 2882 #define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002 2883 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 2884 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004 2885 #define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005 2886 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 2887 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 2888 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 2889 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 2890 2891 /* RSS Packet Types as indicated in the receive descriptor. */ 2892 #define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000 2893 #define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */ 2894 #define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */ 2895 #define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */ 2896 #define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */ 2897 #define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 2898 #define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 2899 #define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 2900 #define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 2901 #define IXGBE_RXDADV_PKTTYPE_GENEVE 0x00000800 /* GENEVE hdr present */ 2902 #define IXGBE_RXDADV_PKTTYPE_VXLAN 0x00000800 /* VXLAN hdr present */ 2903 #define IXGBE_RXDADV_PKTTYPE_TUNNEL 0x00010000 /* Tunnel type */ 2904 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 2905 #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 2906 #define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ 2907 #define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ 2908 #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ 2909 #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ 2910 2911 /* Security Processing bit Indication */ 2912 #define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000 2913 #define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000 2914 #define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000 2915 #define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000 2916 #define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000 2917 2918 /* Masks to determine if packets should be dropped due to frame errors */ 2919 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ 2920 IXGBE_RXD_ERR_CE | \ 2921 IXGBE_RXD_ERR_LE | \ 2922 IXGBE_RXD_ERR_PE | \ 2923 IXGBE_RXD_ERR_OSE | \ 2924 IXGBE_RXD_ERR_USE) 2925 2926 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ 2927 IXGBE_RXDADV_ERR_CE | \ 2928 IXGBE_RXDADV_ERR_LE | \ 2929 IXGBE_RXDADV_ERR_PE | \ 2930 IXGBE_RXDADV_ERR_OSE | \ 2931 IXGBE_RXDADV_ERR_USE) 2932 2933 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK_82599 IXGBE_RXDADV_ERR_RXE 2934 2935 /* Multicast bit mask */ 2936 #define IXGBE_MCSTCTRL_MFE 0x4 2937 2938 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 2939 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 2940 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 2941 #define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 2942 2943 /* Vlan-specific macros */ 2944 #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */ 2945 #define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */ 2946 #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */ 2947 #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 2948 /* Translated register #defines */ 2949 #define IXGBE_PVFCTRL(P) (0x00300 + (4 * (P))) 2950 #define IXGBE_PVFSTATUS(P) (0x00008 + (0 * (P))) 2951 #define IXGBE_PVFLINKS(P) (0x042A4 + (0 * (P))) 2952 #define IXGBE_PVFRTIMER(P) (0x00048 + (0 * (P))) 2953 #define IXGBE_PVFMAILBOX(P) (0x04C00 + (4 * (P))) 2954 #define IXGBE_PVFRXMEMWRAP(P) (0x03190 + (0 * (P))) 2955 #define IXGBE_PVTEICR(P) (0x00B00 + (4 * (P))) 2956 #define IXGBE_PVTEICS(P) (0x00C00 + (4 * (P))) 2957 #define IXGBE_PVTEIMS(P) (0x00D00 + (4 * (P))) 2958 #define IXGBE_PVTEIMC(P) (0x00E00 + (4 * (P))) 2959 #define IXGBE_PVTEIAC(P) (0x00F00 + (4 * (P))) 2960 #define IXGBE_PVTEIAM(P) (0x04D00 + (4 * (P))) 2961 #define IXGBE_PVTEITR(P) (((P) < 24) ? (0x00820 + ((P) * 4)) : \ 2962 (0x012300 + (((P) - 24) * 4))) 2963 #define IXGBE_PVTIVAR(P) (0x12500 + (4 * (P))) 2964 #define IXGBE_PVTIVAR_MISC(P) (0x04E00 + (4 * (P))) 2965 #define IXGBE_PVTRSCINT(P) (0x12000 + (4 * (P))) 2966 #define IXGBE_VFPBACL(P) (0x110C8 + (4 * (P))) 2967 #define IXGBE_PVFRDBAL(P) ((P < 64) ? (0x01000 + (0x40 * (P))) \ 2968 : (0x0D000 + (0x40 * ((P) - 64)))) 2969 #define IXGBE_PVFRDBAH(P) ((P < 64) ? (0x01004 + (0x40 * (P))) \ 2970 : (0x0D004 + (0x40 * ((P) - 64)))) 2971 #define IXGBE_PVFRDLEN(P) ((P < 64) ? (0x01008 + (0x40 * (P))) \ 2972 : (0x0D008 + (0x40 * ((P) - 64)))) 2973 #define IXGBE_PVFRDH(P) ((P < 64) ? (0x01010 + (0x40 * (P))) \ 2974 : (0x0D010 + (0x40 * ((P) - 64)))) 2975 #define IXGBE_PVFRDT(P) ((P < 64) ? (0x01018 + (0x40 * (P))) \ 2976 : (0x0D018 + (0x40 * ((P) - 64)))) 2977 #define IXGBE_PVFRXDCTL(P) ((P < 64) ? (0x01028 + (0x40 * (P))) \ 2978 : (0x0D028 + (0x40 * ((P) - 64)))) 2979 #define IXGBE_PVFSRRCTL(P) ((P < 64) ? (0x01014 + (0x40 * (P))) \ 2980 : (0x0D014 + (0x40 * ((P) - 64)))) 2981 #define IXGBE_PVFPSRTYPE(P) (0x0EA00 + (4 * (P))) 2982 #define IXGBE_PVFTDBAL(P) (0x06000 + (0x40 * (P))) 2983 #define IXGBE_PVFTDBAH(P) (0x06004 + (0x40 * (P))) 2984 #define IXGBE_PVFTDLEN(P) (0x06008 + (0x40 * (P))) 2985 #define IXGBE_PVFTDH(P) (0x06010 + (0x40 * (P))) 2986 #define IXGBE_PVFTDT(P) (0x06018 + (0x40 * (P))) 2987 #define IXGBE_PVFTXDCTL(P) (0x06028 + (0x40 * (P))) 2988 #define IXGBE_PVFTDWBAL(P) (0x06038 + (0x40 * (P))) 2989 #define IXGBE_PVFTDWBAH(P) (0x0603C + (0x40 * (P))) 2990 #define IXGBE_PVFDCA_RXCTRL(P) (((P) < 64) ? (0x0100C + (0x40 * (P))) \ 2991 : (0x0D00C + (0x40 * ((P) - 64)))) 2992 #define IXGBE_PVFDCA_TXCTRL(P) (0x0600C + (0x40 * (P))) 2993 #define IXGBE_PVFGPRC(x) (0x0101C + (0x40 * (x))) 2994 #define IXGBE_PVFGPTC(x) (0x08300 + (0x04 * (x))) 2995 #define IXGBE_PVFGORC_LSB(x) (0x01020 + (0x40 * (x))) 2996 #define IXGBE_PVFGORC_MSB(x) (0x0D020 + (0x40 * (x))) 2997 #define IXGBE_PVFGOTC_LSB(x) (0x08400 + (0x08 * (x))) 2998 #define IXGBE_PVFGOTC_MSB(x) (0x08404 + (0x08 * (x))) 2999 #define IXGBE_PVFMPRC(x) (0x0D01C + (0x40 * (x))) 3000 3001 #define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \ 3002 (IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index))) 3003 #define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \ 3004 (IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index))) 3005 3006 #define IXGBE_PVFTDHn(q_per_pool, vf_number, vf_q_index) \ 3007 (IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index))) 3008 #define IXGBE_PVFTDTn(q_per_pool, vf_number, vf_q_index) \ 3009 (IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index))) 3010 3011 /* Little Endian defines */ 3012 #ifndef __le16 3013 #define __le16 u16 3014 #endif 3015 #ifndef __le32 3016 #define __le32 u32 3017 #endif 3018 #ifndef __le64 3019 #define __le64 u64 3020 3021 #endif 3022 #ifndef __be16 3023 /* Big Endian defines */ 3024 #define __be16 u16 3025 #define __be32 u32 3026 #define __be64 u64 3027 3028 #endif 3029 enum ixgbe_fdir_pballoc_type { 3030 IXGBE_FDIR_PBALLOC_NONE = 0, 3031 IXGBE_FDIR_PBALLOC_64K = 1, 3032 IXGBE_FDIR_PBALLOC_128K = 2, 3033 IXGBE_FDIR_PBALLOC_256K = 3, 3034 }; 3035 3036 /* Flow Director register values */ 3037 #define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001 3038 #define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002 3039 #define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003 3040 #define IXGBE_FDIRCTRL_INIT_DONE 0x00000008 3041 #define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010 3042 #define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020 3043 #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080 3044 #define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8 3045 #define IXGBE_FDIRCTRL_DROP_Q_MASK 0x00007F00 3046 #define IXGBE_FDIRCTRL_FLEX_SHIFT 16 3047 #define IXGBE_FDIRCTRL_DROP_NO_MATCH 0x00008000 3048 #define IXGBE_FDIRCTRL_FILTERMODE_SHIFT 21 3049 #define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN 0x0001 /* bit 23:21, 001b */ 3050 #define IXGBE_FDIRCTRL_FILTERMODE_CLOUD 0x0002 /* bit 23:21, 010b */ 3051 #define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000 3052 #define IXGBE_FDIRCTRL_FILTERMODE_MASK 0x00E00000 3053 #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24 3054 #define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000 3055 #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28 3056 3057 #define IXGBE_FDIRTCPM_DPORTM_SHIFT 16 3058 #define IXGBE_FDIRUDPM_DPORTM_SHIFT 16 3059 #define IXGBE_FDIRIP6M_DIPM_SHIFT 16 3060 #define IXGBE_FDIRM_VLANID 0x00000001 3061 #define IXGBE_FDIRM_VLANP 0x00000002 3062 #define IXGBE_FDIRM_POOL 0x00000004 3063 #define IXGBE_FDIRM_L4P 0x00000008 3064 #define IXGBE_FDIRM_FLEX 0x00000010 3065 #define IXGBE_FDIRM_DIPv6 0x00000020 3066 #define IXGBE_FDIRM_L3P 0x00000040 3067 3068 #define IXGBE_FDIRIP6M_INNER_MAC 0x03F0 /* bit 9:4 */ 3069 #define IXGBE_FDIRIP6M_TUNNEL_TYPE 0x0800 /* bit 11 */ 3070 #define IXGBE_FDIRIP6M_TNI_VNI 0xF000 /* bit 15:12 */ 3071 #define IXGBE_FDIRIP6M_TNI_VNI_24 0x1000 /* bit 12 */ 3072 #define IXGBE_FDIRIP6M_ALWAYS_MASK 0x040F /* bit 10, 3:0 */ 3073 3074 #define IXGBE_FDIRFREE_FREE_MASK 0xFFFF 3075 #define IXGBE_FDIRFREE_FREE_SHIFT 0 3076 #define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000 3077 #define IXGBE_FDIRFREE_COLL_SHIFT 16 3078 #define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F 3079 #define IXGBE_FDIRLEN_MAXLEN_SHIFT 0 3080 #define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000 3081 #define IXGBE_FDIRLEN_MAXHASH_SHIFT 16 3082 #define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF 3083 #define IXGBE_FDIRUSTAT_ADD_SHIFT 0 3084 #define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000 3085 #define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16 3086 #define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF 3087 #define IXGBE_FDIRFSTAT_FADD_SHIFT 0 3088 #define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00 3089 #define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8 3090 #define IXGBE_FDIRPORT_DESTINATION_SHIFT 16 3091 #define IXGBE_FDIRVLAN_FLEX_SHIFT 16 3092 #define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15 3093 #define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16 3094 3095 #define IXGBE_FDIRCMD_CMD_MASK 0x00000003 3096 #define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001 3097 #define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002 3098 #define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003 3099 #define IXGBE_FDIRCMD_FILTER_VALID 0x00000004 3100 #define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008 3101 #define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010 3102 #define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020 3103 #define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040 3104 #define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060 3105 #define IXGBE_FDIRCMD_IPV6 0x00000080 3106 #define IXGBE_FDIRCMD_CLEARHT 0x00000100 3107 #define IXGBE_FDIRCMD_DROP 0x00000200 3108 #define IXGBE_FDIRCMD_INT 0x00000400 3109 #define IXGBE_FDIRCMD_LAST 0x00000800 3110 #define IXGBE_FDIRCMD_COLLISION 0x00001000 3111 #define IXGBE_FDIRCMD_QUEUE_EN 0x00008000 3112 #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5 3113 #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16 3114 #define IXGBE_FDIRCMD_TUNNEL_FILTER_SHIFT 23 3115 #define IXGBE_FDIRCMD_VT_POOL_SHIFT 24 3116 #define IXGBE_FDIR_INIT_DONE_POLL 10 3117 #define IXGBE_FDIRCMD_CMD_POLL 10 3118 #define IXGBE_FDIRCMD_TUNNEL_FILTER 0x00800000 3119 #define IXGBE_FDIR_DROP_QUEUE 127 3120 3121 3122 /* Manageablility Host Interface defines */ 3123 #define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */ 3124 #define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */ 3125 #define IXGBE_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */ 3126 #define IXGBE_HI_FLASH_ERASE_TIMEOUT 1000 /* Process Erase command limit */ 3127 #define IXGBE_HI_FLASH_UPDATE_TIMEOUT 5000 /* Process Update command limit */ 3128 #define IXGBE_HI_FLASH_APPLY_TIMEOUT 0 /* Process Apply command limit */ 3129 #define IXGBE_HI_PHY_MGMT_REQ_TIMEOUT 2000 /* Wait up to 2 seconds */ 3130 3131 /* CEM Support */ 3132 #define FW_CEM_HDR_LEN 0x4 3133 #define FW_CEM_CMD_DRIVER_INFO 0xDD 3134 #define FW_CEM_CMD_DRIVER_INFO_LEN 0x5 3135 #define FW_CEM_CMD_RESERVED 0X0 3136 #define FW_CEM_UNUSED_VER 0x0 3137 #define FW_CEM_MAX_RETRIES 3 3138 #define FW_CEM_RESP_STATUS_SUCCESS 0x1 3139 #define FW_CEM_DRIVER_VERSION_SIZE 39 /* +9 would send 48 bytes to fw */ 3140 #define FW_READ_SHADOW_RAM_CMD 0x31 3141 #define FW_READ_SHADOW_RAM_LEN 0x6 3142 #define FW_WRITE_SHADOW_RAM_CMD 0x33 3143 #define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */ 3144 #define FW_SHADOW_RAM_DUMP_CMD 0x36 3145 #define FW_SHADOW_RAM_DUMP_LEN 0 3146 #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ 3147 #define FW_NVM_DATA_OFFSET 3 3148 #define FW_MAX_READ_BUFFER_SIZE 1024 3149 #define FW_DISABLE_RXEN_CMD 0xDE 3150 #define FW_DISABLE_RXEN_LEN 0x1 3151 #define FW_PHY_MGMT_REQ_CMD 0x20 3152 #define FW_PHY_TOKEN_REQ_CMD 0xA 3153 #define FW_PHY_TOKEN_REQ_LEN 2 3154 #define FW_PHY_TOKEN_REQ 0 3155 #define FW_PHY_TOKEN_REL 1 3156 #define FW_PHY_TOKEN_OK 1 3157 #define FW_PHY_TOKEN_RETRY 0x80 3158 #define FW_PHY_TOKEN_DELAY 5 /* milliseconds */ 3159 #define FW_PHY_TOKEN_WAIT 5 /* seconds */ 3160 #define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY) 3161 #define FW_INT_PHY_REQ_CMD 0xB 3162 #define FW_INT_PHY_REQ_LEN 10 3163 #define FW_INT_PHY_REQ_READ 0 3164 #define FW_INT_PHY_REQ_WRITE 1 3165 #define FW_PHY_ACT_REQ_CMD 5 3166 #define FW_PHY_ACT_DATA_COUNT 4 3167 #define FW_PHY_ACT_REQ_LEN (4 + 4 * FW_PHY_ACT_DATA_COUNT) 3168 #define FW_PHY_ACT_INIT_PHY 1 3169 #define FW_PHY_ACT_SETUP_LINK 2 3170 #define FW_PHY_ACT_LINK_SPEED_10 (1u << 0) 3171 #define FW_PHY_ACT_LINK_SPEED_100 (1u << 1) 3172 #define FW_PHY_ACT_LINK_SPEED_1G (1u << 2) 3173 #define FW_PHY_ACT_LINK_SPEED_2_5G (1u << 3) 3174 #define FW_PHY_ACT_LINK_SPEED_5G (1u << 4) 3175 #define FW_PHY_ACT_LINK_SPEED_10G (1u << 5) 3176 #define FW_PHY_ACT_LINK_SPEED_20G (1u << 6) 3177 #define FW_PHY_ACT_LINK_SPEED_25G (1u << 7) 3178 #define FW_PHY_ACT_LINK_SPEED_40G (1u << 8) 3179 #define FW_PHY_ACT_LINK_SPEED_50G (1u << 9) 3180 #define FW_PHY_ACT_LINK_SPEED_100G (1u << 10) 3181 #define FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT 16 3182 #define FW_PHY_ACT_SETUP_LINK_PAUSE_MASK (3u << \ 3183 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT) 3184 #define FW_PHY_ACT_SETUP_LINK_PAUSE_NONE 0u 3185 #define FW_PHY_ACT_SETUP_LINK_PAUSE_TX 1u 3186 #define FW_PHY_ACT_SETUP_LINK_PAUSE_RX 2u 3187 #define FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX 3u 3188 #define FW_PHY_ACT_SETUP_LINK_LP (1u << 18) 3189 #define FW_PHY_ACT_SETUP_LINK_HP (1u << 19) 3190 #define FW_PHY_ACT_SETUP_LINK_EEE (1u << 20) 3191 #define FW_PHY_ACT_SETUP_LINK_AN (1u << 22) 3192 #define FW_PHY_ACT_SETUP_LINK_RSP_DOWN (1u << 0) 3193 #define FW_PHY_ACT_GET_LINK_INFO 3 3194 #define FW_PHY_ACT_GET_LINK_INFO_EEE (1u << 19) 3195 #define FW_PHY_ACT_GET_LINK_INFO_FC_TX (1u << 20) 3196 #define FW_PHY_ACT_GET_LINK_INFO_FC_RX (1u << 21) 3197 #define FW_PHY_ACT_GET_LINK_INFO_POWER (1u << 22) 3198 #define FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE (1u << 24) 3199 #define FW_PHY_ACT_GET_LINK_INFO_TEMP (1u << 25) 3200 #define FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX (1u << 28) 3201 #define FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX (1u << 29) 3202 #define FW_PHY_ACT_FORCE_LINK_DOWN 4 3203 #define FW_PHY_ACT_FORCE_LINK_DOWN_OFF (1u << 0) 3204 #define FW_PHY_ACT_PHY_SW_RESET 5 3205 #define FW_PHY_ACT_PHY_HW_RESET 6 3206 #define FW_PHY_ACT_GET_PHY_INFO 7 3207 #define FW_PHY_ACT_UD_2 0x1002 3208 #define FW_PHY_ACT_UD_2_10G_KR_EEE (1u << 6) 3209 #define FW_PHY_ACT_UD_2_10G_KX4_EEE (1u << 5) 3210 #define FW_PHY_ACT_UD_2_1G_KX_EEE (1u << 4) 3211 #define FW_PHY_ACT_UD_2_10G_T_EEE (1u << 3) 3212 #define FW_PHY_ACT_UD_2_1G_T_EEE (1u << 2) 3213 #define FW_PHY_ACT_UD_2_100M_TX_EEE (1u << 1) 3214 #define FW_PHY_ACT_RETRIES 50 3215 #define FW_PHY_INFO_SPEED_MASK 0xFFFu 3216 #define FW_PHY_INFO_ID_HI_MASK 0xFFFF0000u 3217 #define FW_PHY_INFO_ID_LO_MASK 0x0000FFFFu 3218 3219 /* Host Interface Command Structures */ 3220 3221 #pragma pack(push, 1) 3222 3223 struct ixgbe_hic_hdr { 3224 u8 cmd; 3225 u8 buf_len; 3226 union { 3227 u8 cmd_resv; 3228 u8 ret_status; 3229 } cmd_or_resp; 3230 u8 checksum; 3231 }; 3232 3233 struct ixgbe_hic_hdr2_req { 3234 u8 cmd; 3235 u8 buf_lenh; 3236 u8 buf_lenl; 3237 u8 checksum; 3238 }; 3239 3240 struct ixgbe_hic_hdr2_rsp { 3241 u8 cmd; 3242 u8 buf_lenl; 3243 u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */ 3244 u8 checksum; 3245 }; 3246 3247 union ixgbe_hic_hdr2 { 3248 struct ixgbe_hic_hdr2_req req; 3249 struct ixgbe_hic_hdr2_rsp rsp; 3250 }; 3251 3252 struct ixgbe_hic_drv_info { 3253 struct ixgbe_hic_hdr hdr; 3254 u8 port_num; 3255 u8 ver_sub; 3256 u8 ver_build; 3257 u8 ver_min; 3258 u8 ver_maj; 3259 u8 pad; /* end spacing to ensure length is mult. of dword */ 3260 u16 pad2; /* end spacing to ensure length is mult. of dword2 */ 3261 }; 3262 3263 struct ixgbe_hic_drv_info2 { 3264 struct ixgbe_hic_hdr hdr; 3265 u8 port_num; 3266 u8 ver_sub; 3267 u8 ver_build; 3268 u8 ver_min; 3269 u8 ver_maj; 3270 char driver_string[FW_CEM_DRIVER_VERSION_SIZE]; 3271 }; 3272 3273 /* These need to be dword aligned */ 3274 struct ixgbe_hic_read_shadow_ram { 3275 union ixgbe_hic_hdr2 hdr; 3276 u32 address; 3277 u16 length; 3278 u16 pad2; 3279 u16 data; 3280 u16 pad3; 3281 }; 3282 3283 struct ixgbe_hic_write_shadow_ram { 3284 union ixgbe_hic_hdr2 hdr; 3285 u32 address; 3286 u16 length; 3287 u16 pad2; 3288 u16 data; 3289 u16 pad3; 3290 }; 3291 3292 struct ixgbe_hic_disable_rxen { 3293 struct ixgbe_hic_hdr hdr; 3294 u8 port_number; 3295 u8 pad2; 3296 u16 pad3; 3297 }; 3298 3299 struct ixgbe_hic_phy_token_req { 3300 struct ixgbe_hic_hdr hdr; 3301 u8 port_number; 3302 u8 command_type; 3303 u16 pad; 3304 }; 3305 3306 struct ixgbe_hic_internal_phy_req { 3307 struct ixgbe_hic_hdr hdr; 3308 u8 port_number; 3309 u8 command_type; 3310 __be16 address; 3311 u16 rsv1; 3312 __be32 write_data; 3313 u16 pad; 3314 }; 3315 3316 struct ixgbe_hic_internal_phy_resp { 3317 struct ixgbe_hic_hdr hdr; 3318 __be32 read_data; 3319 }; 3320 3321 struct ixgbe_hic_phy_activity_req { 3322 struct ixgbe_hic_hdr hdr; 3323 u8 port_number; 3324 u8 pad; 3325 __le16 activity_id; 3326 __be32 data[FW_PHY_ACT_DATA_COUNT]; 3327 }; 3328 3329 struct ixgbe_hic_phy_activity_resp { 3330 struct ixgbe_hic_hdr hdr; 3331 __be32 data[FW_PHY_ACT_DATA_COUNT]; 3332 }; 3333 3334 #pragma pack(pop) 3335 3336 /* Transmit Descriptor - Legacy */ 3337 struct ixgbe_legacy_tx_desc { 3338 u64 buffer_addr; /* Address of the descriptor's data buffer */ 3339 union { 3340 __le32 data; 3341 struct { 3342 __le16 length; /* Data buffer length */ 3343 u8 cso; /* Checksum offset */ 3344 u8 cmd; /* Descriptor control */ 3345 } flags; 3346 } lower; 3347 union { 3348 __le32 data; 3349 struct { 3350 u8 status; /* Descriptor status */ 3351 u8 css; /* Checksum start */ 3352 __le16 vlan; 3353 } fields; 3354 } upper; 3355 }; 3356 3357 /* Transmit Descriptor - Advanced */ 3358 union ixgbe_adv_tx_desc { 3359 struct { 3360 __le64 buffer_addr; /* Address of descriptor's data buf */ 3361 __le32 cmd_type_len; 3362 __le32 olinfo_status; 3363 } read; 3364 struct { 3365 __le64 rsvd; /* Reserved */ 3366 __le32 nxtseq_seed; 3367 __le32 status; 3368 } wb; 3369 }; 3370 3371 /* Receive Descriptor - Legacy */ 3372 struct ixgbe_legacy_rx_desc { 3373 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 3374 __le16 length; /* Length of data DMAed into data buffer */ 3375 __le16 csum; /* Packet checksum */ 3376 u8 status; /* Descriptor status */ 3377 u8 errors; /* Descriptor Errors */ 3378 __le16 vlan; 3379 }; 3380 3381 /* Receive Descriptor - Advanced */ 3382 union ixgbe_adv_rx_desc { 3383 struct { 3384 __le64 pkt_addr; /* Packet buffer address */ 3385 __le64 hdr_addr; /* Header buffer address */ 3386 } read; 3387 struct { 3388 struct { 3389 union { 3390 __le32 data; 3391 struct { 3392 __le16 pkt_info; /* RSS, Pkt type */ 3393 __le16 hdr_info; /* Splithdr, hdrlen */ 3394 } hs_rss; 3395 } lo_dword; 3396 union { 3397 __le32 rss; /* RSS Hash */ 3398 struct { 3399 __le16 ip_id; /* IP id */ 3400 __le16 csum; /* Packet Checksum */ 3401 } csum_ip; 3402 } hi_dword; 3403 } lower; 3404 struct { 3405 __le32 status_error; /* ext status/error */ 3406 __le16 length; /* Packet length */ 3407 __le16 vlan; /* VLAN tag */ 3408 } upper; 3409 } wb; /* writeback */ 3410 }; 3411 3412 /* Context descriptors */ 3413 struct ixgbe_adv_tx_context_desc { 3414 __le32 vlan_macip_lens; 3415 __le32 seqnum_seed; 3416 __le32 type_tucmd_mlhl; 3417 __le32 mss_l4len_idx; 3418 }; 3419 3420 /* Adv Transmit Descriptor Config Masks */ 3421 #define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */ 3422 #define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */ 3423 #define IXGBE_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 time stamp */ 3424 #define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */ 3425 #define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */ 3426 #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ 3427 #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Adv Context Desc */ 3428 #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Adv Data Descriptor */ 3429 #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ 3430 #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ 3431 #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ 3432 #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 3433 #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext 1=Adv */ 3434 #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ 3435 #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 3436 #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ 3437 #define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */ 3438 #define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */ 3439 #define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 3440 #define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ 3441 #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ 3442 #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ 3443 IXGBE_ADVTXD_POPTS_SHIFT) 3444 #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ 3445 IXGBE_ADVTXD_POPTS_SHIFT) 3446 #define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 3447 #define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 3448 #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 3449 /* 1st&Last TSO-full iSCSI PDU */ 3450 #define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 3451 #define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */ 3452 #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 3453 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 3454 #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 3455 #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 3456 #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 3457 #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 3458 #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 3459 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 3460 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* RSV L4 Packet TYPE */ 3461 #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* req Markers and CRC */ 3462 #define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 3463 #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ 3464 #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */ 3465 #define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */ 3466 #define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */ 3467 #define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */ 3468 #define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */ 3469 #define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation End */ 3470 #define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation Start */ 3471 #define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */ 3472 #define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */ 3473 #define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */ 3474 #define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */ 3475 #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 3476 #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 3477 3478 #define IXGBE_ADVTXD_OUTER_IPLEN 16 /* Adv ctxt OUTERIPLEN shift */ 3479 #define IXGBE_ADVTXD_TUNNEL_LEN 24 /* Adv ctxt TUNNELLEN shift */ 3480 #define IXGBE_ADVTXD_TUNNEL_TYPE_SHIFT 16 /* Adv Tx Desc Tunnel Type shift */ 3481 #define IXGBE_ADVTXD_OUTERIPCS_SHIFT 17 /* Adv Tx Desc OUTERIPCS Shift */ 3482 #define IXGBE_ADVTXD_TUNNEL_TYPE_NVGRE 1 /* Adv Tx Desc Tunnel Type NVGRE */ 3483 /* Adv Tx Desc OUTERIPCS Shift for X550EM_a */ 3484 #define IXGBE_ADVTXD_OUTERIPCS_SHIFT_X550EM_a 26 3485 /* Autonegotiation advertised speeds */ 3486 typedef u32 ixgbe_autoneg_advertised; 3487 /* Link speed */ 3488 typedef u32 ixgbe_link_speed; 3489 #define IXGBE_LINK_SPEED_UNKNOWN 0 3490 #define IXGBE_LINK_SPEED_10_FULL 0x0002 3491 #define IXGBE_LINK_SPEED_100_FULL 0x0008 3492 #define IXGBE_LINK_SPEED_1GB_FULL 0x0020 3493 #define IXGBE_LINK_SPEED_2_5GB_FULL 0x0400 3494 #define IXGBE_LINK_SPEED_5GB_FULL 0x0800 3495 #define IXGBE_LINK_SPEED_10GB_FULL 0x0080 3496 #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \ 3497 IXGBE_LINK_SPEED_10GB_FULL) 3498 #define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \ 3499 IXGBE_LINK_SPEED_1GB_FULL | \ 3500 IXGBE_LINK_SPEED_10GB_FULL) 3501 3502 /* Physical layer type */ 3503 typedef u64 ixgbe_physical_layer; 3504 #define IXGBE_PHYSICAL_LAYER_UNKNOWN 0 3505 #define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x00001 3506 #define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x00002 3507 #define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x00004 3508 #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x00008 3509 #define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x00010 3510 #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x00020 3511 #define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x00040 3512 #define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x00080 3513 #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x00100 3514 #define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x00200 3515 #define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x00400 3516 #define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x00800 3517 #define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x01000 3518 #define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x02000 3519 #define IXGBE_PHYSICAL_LAYER_1000BASE_SX 0x04000 3520 #define IXGBE_PHYSICAL_LAYER_10BASE_T 0x08000 3521 #define IXGBE_PHYSICAL_LAYER_2500BASE_KX 0x10000 3522 #define IXGBE_PHYSICAL_LAYER_2500BASE_T 0x20000 3523 #define IXGBE_PHYSICAL_LAYER_5GBASE_T 0x40000 3524 3525 /* Flow Control Data Sheet defined values 3526 * Calculation and defines taken from 802.1bb Annex O 3527 */ 3528 3529 /* BitTimes (BT) conversion */ 3530 #define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024)) 3531 #define IXGBE_B2BT(BT) (BT * 8) 3532 3533 /* Calculate Delay to respond to PFC */ 3534 #define IXGBE_PFC_D 672 3535 3536 /* Calculate Cable Delay */ 3537 #define IXGBE_CABLE_DC 5556 /* Delay Copper */ 3538 #define IXGBE_CABLE_DO 5000 /* Delay Optical */ 3539 3540 /* Calculate Interface Delay X540 */ 3541 #define IXGBE_PHY_DC 25600 /* Delay 10G BASET */ 3542 #define IXGBE_MAC_DC 8192 /* Delay Copper XAUI interface */ 3543 #define IXGBE_XAUI_DC (2 * 2048) /* Delay Copper Phy */ 3544 3545 #define IXGBE_ID_X540 (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC) 3546 3547 /* Calculate Interface Delay 82598, 82599 */ 3548 #define IXGBE_PHY_D 12800 3549 #define IXGBE_MAC_D 4096 3550 #define IXGBE_XAUI_D (2 * 1024) 3551 3552 #define IXGBE_ID (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D) 3553 3554 /* Calculate Delay incurred from higher layer */ 3555 #define IXGBE_HD 6144 3556 3557 /* Calculate PCI Bus delay for low thresholds */ 3558 #define IXGBE_PCI_DELAY 10000 3559 3560 /* Calculate X540 delay value in bit times */ 3561 #define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \ 3562 ((36 * \ 3563 (IXGBE_B2BT(_max_frame_link) + \ 3564 IXGBE_PFC_D + \ 3565 (2 * IXGBE_CABLE_DC) + \ 3566 (2 * IXGBE_ID_X540) + \ 3567 IXGBE_HD) / 25 + 1) + \ 3568 2 * IXGBE_B2BT(_max_frame_tc)) 3569 3570 /* Calculate 82599, 82598 delay value in bit times */ 3571 #define IXGBE_DV(_max_frame_link, _max_frame_tc) \ 3572 ((36 * \ 3573 (IXGBE_B2BT(_max_frame_link) + \ 3574 IXGBE_PFC_D + \ 3575 (2 * IXGBE_CABLE_DC) + \ 3576 (2 * IXGBE_ID) + \ 3577 IXGBE_HD) / 25 + 1) + \ 3578 2 * IXGBE_B2BT(_max_frame_tc)) 3579 3580 /* Calculate low threshold delay values */ 3581 #define IXGBE_LOW_DV_X540(_max_frame_tc) \ 3582 (2 * IXGBE_B2BT(_max_frame_tc) + \ 3583 (36 * IXGBE_PCI_DELAY / 25) + 1) 3584 #define IXGBE_LOW_DV(_max_frame_tc) \ 3585 (2 * IXGBE_LOW_DV_X540(_max_frame_tc)) 3586 3587 /* Software ATR hash keys */ 3588 #define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2 3589 #define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614 3590 3591 /* Software ATR input stream values and masks */ 3592 #define IXGBE_ATR_HASH_MASK 0x7fff 3593 #define IXGBE_ATR_L4TYPE_MASK 0x3 3594 #define IXGBE_ATR_L4TYPE_UDP 0x1 3595 #define IXGBE_ATR_L4TYPE_TCP 0x2 3596 #define IXGBE_ATR_L4TYPE_SCTP 0x3 3597 #define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4 3598 #define IXGBE_ATR_L4TYPE_TUNNEL_MASK 0x10 3599 enum ixgbe_atr_flow_type { 3600 IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0, 3601 IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1, 3602 IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2, 3603 IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3, 3604 IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4, 3605 IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5, 3606 IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6, 3607 IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7, 3608 IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4 = 0x10, 3609 IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4 = 0x11, 3610 IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4 = 0x12, 3611 IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4 = 0x13, 3612 IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6 = 0x14, 3613 IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6 = 0x15, 3614 IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6 = 0x16, 3615 IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6 = 0x17, 3616 }; 3617 3618 /* Flow Director ATR input struct. */ 3619 union ixgbe_atr_input { 3620 /* 3621 * Byte layout in order, all values with MSB first: 3622 * 3623 * vm_pool - 1 byte 3624 * flow_type - 1 byte 3625 * vlan_id - 2 bytes 3626 * src_ip - 16 bytes 3627 * inner_mac - 6 bytes 3628 * cloud_mode - 2 bytes 3629 * tni_vni - 4 bytes 3630 * dst_ip - 16 bytes 3631 * src_port - 2 bytes 3632 * dst_port - 2 bytes 3633 * flex_bytes - 2 bytes 3634 * bkt_hash - 2 bytes 3635 */ 3636 struct { 3637 u8 vm_pool; 3638 u8 flow_type; 3639 __be16 vlan_id; 3640 __be32 dst_ip[4]; 3641 __be32 src_ip[4]; 3642 u8 inner_mac[6]; 3643 __be16 tunnel_type; 3644 __be32 tni_vni; 3645 __be16 src_port; 3646 __be16 dst_port; 3647 __be16 flex_bytes; 3648 __be16 bkt_hash; 3649 } formatted; 3650 __be32 dword_stream[14]; 3651 }; 3652 3653 /* Flow Director compressed ATR hash input struct */ 3654 union ixgbe_atr_hash_dword { 3655 struct { 3656 u8 vm_pool; 3657 u8 flow_type; 3658 __be16 vlan_id; 3659 } formatted; 3660 __be32 ip; 3661 struct { 3662 __be16 src; 3663 __be16 dst; 3664 } port; 3665 __be16 flex_bytes; 3666 __be32 dword; 3667 }; 3668 3669 #define IXGBE_MVALS_INIT(m) \ 3670 IXGBE_CAT(EEC, m), \ 3671 IXGBE_CAT(FLA, m), \ 3672 IXGBE_CAT(GRC, m), \ 3673 IXGBE_CAT(SRAMREL, m), \ 3674 IXGBE_CAT(FACTPS, m), \ 3675 IXGBE_CAT(SWSM, m), \ 3676 IXGBE_CAT(SWFW_SYNC, m), \ 3677 IXGBE_CAT(FWSM, m), \ 3678 IXGBE_CAT(SDP0_GPIEN, m), \ 3679 IXGBE_CAT(SDP1_GPIEN, m), \ 3680 IXGBE_CAT(SDP2_GPIEN, m), \ 3681 IXGBE_CAT(EICR_GPI_SDP0, m), \ 3682 IXGBE_CAT(EICR_GPI_SDP1, m), \ 3683 IXGBE_CAT(EICR_GPI_SDP2, m), \ 3684 IXGBE_CAT(CIAA, m), \ 3685 IXGBE_CAT(CIAD, m), \ 3686 IXGBE_CAT(I2C_CLK_IN, m), \ 3687 IXGBE_CAT(I2C_CLK_OUT, m), \ 3688 IXGBE_CAT(I2C_DATA_IN, m), \ 3689 IXGBE_CAT(I2C_DATA_OUT, m), \ 3690 IXGBE_CAT(I2C_DATA_OE_N_EN, m), \ 3691 IXGBE_CAT(I2C_BB_EN, m), \ 3692 IXGBE_CAT(I2C_CLK_OE_N_EN, m), \ 3693 IXGBE_CAT(I2CCTL, m) 3694 3695 enum ixgbe_mvals { 3696 IXGBE_MVALS_INIT(_IDX), 3697 IXGBE_MVALS_IDX_LIMIT 3698 }; 3699 3700 /* 3701 * Unavailable: The FCoE Boot Option ROM is not present in the flash. 3702 * Disabled: Present; boot order is not set for any targets on the port. 3703 * Enabled: Present; boot order is set for at least one target on the port. 3704 */ 3705 enum ixgbe_fcoe_boot_status { 3706 ixgbe_fcoe_bootstatus_disabled = 0, 3707 ixgbe_fcoe_bootstatus_enabled = 1, 3708 ixgbe_fcoe_bootstatus_unavailable = 0xFFFF 3709 }; 3710 3711 enum ixgbe_eeprom_type { 3712 ixgbe_eeprom_uninitialized = 0, 3713 ixgbe_eeprom_spi, 3714 ixgbe_flash, 3715 ixgbe_eeprom_none /* No NVM support */ 3716 }; 3717 3718 enum ixgbe_mac_type { 3719 ixgbe_mac_unknown = 0, 3720 ixgbe_mac_82598EB, 3721 ixgbe_mac_82599EB, 3722 ixgbe_mac_82599_vf, 3723 ixgbe_mac_X540, 3724 ixgbe_mac_X540_vf, 3725 ixgbe_mac_X550, 3726 ixgbe_mac_X550EM_x, 3727 ixgbe_mac_X550EM_a, 3728 ixgbe_mac_X550_vf, 3729 ixgbe_mac_X550EM_x_vf, 3730 ixgbe_mac_X550EM_a_vf, 3731 ixgbe_num_macs 3732 }; 3733 3734 enum ixgbe_phy_type { 3735 ixgbe_phy_unknown = 0, 3736 ixgbe_phy_none, 3737 ixgbe_phy_tn, 3738 ixgbe_phy_aq, 3739 ixgbe_phy_x550em_kr, 3740 ixgbe_phy_x550em_kx4, 3741 ixgbe_phy_x550em_xfi, 3742 ixgbe_phy_x550em_ext_t, 3743 ixgbe_phy_ext_1g_t, 3744 ixgbe_phy_cu_unknown, 3745 ixgbe_phy_qt, 3746 ixgbe_phy_xaui, 3747 ixgbe_phy_nl, 3748 ixgbe_phy_sfp_passive_tyco, 3749 ixgbe_phy_sfp_passive_unknown, 3750 ixgbe_phy_sfp_active_unknown, 3751 ixgbe_phy_sfp_avago, 3752 ixgbe_phy_sfp_ftl, 3753 ixgbe_phy_sfp_ftl_active, 3754 ixgbe_phy_sfp_unknown, 3755 ixgbe_phy_sfp_intel, 3756 ixgbe_phy_qsfp_passive_unknown, 3757 ixgbe_phy_qsfp_active_unknown, 3758 ixgbe_phy_qsfp_intel, 3759 ixgbe_phy_qsfp_unknown, 3760 ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/ 3761 ixgbe_phy_sgmii, 3762 ixgbe_phy_fw, 3763 ixgbe_phy_generic 3764 }; 3765 3766 /* 3767 * SFP+ module type IDs: 3768 * 3769 * ID Module Type 3770 * ============= 3771 * 0 SFP_DA_CU 3772 * 1 SFP_SR 3773 * 2 SFP_LR 3774 * 3 SFP_DA_CU_CORE0 - 82599-specific 3775 * 4 SFP_DA_CU_CORE1 - 82599-specific 3776 * 5 SFP_SR/LR_CORE0 - 82599-specific 3777 * 6 SFP_SR/LR_CORE1 - 82599-specific 3778 */ 3779 enum ixgbe_sfp_type { 3780 ixgbe_sfp_type_da_cu = 0, 3781 ixgbe_sfp_type_sr = 1, 3782 ixgbe_sfp_type_lr = 2, 3783 ixgbe_sfp_type_da_cu_core0 = 3, 3784 ixgbe_sfp_type_da_cu_core1 = 4, 3785 ixgbe_sfp_type_srlr_core0 = 5, 3786 ixgbe_sfp_type_srlr_core1 = 6, 3787 ixgbe_sfp_type_da_act_lmt_core0 = 7, 3788 ixgbe_sfp_type_da_act_lmt_core1 = 8, 3789 ixgbe_sfp_type_1g_cu_core0 = 9, 3790 ixgbe_sfp_type_1g_cu_core1 = 10, 3791 ixgbe_sfp_type_1g_sx_core0 = 11, 3792 ixgbe_sfp_type_1g_sx_core1 = 12, 3793 ixgbe_sfp_type_1g_lx_core0 = 13, 3794 ixgbe_sfp_type_1g_lx_core1 = 14, 3795 ixgbe_sfp_type_not_present = 0xFFFE, 3796 ixgbe_sfp_type_unknown = 0xFFFF 3797 }; 3798 3799 enum ixgbe_media_type { 3800 ixgbe_media_type_unknown = 0, 3801 ixgbe_media_type_fiber, 3802 ixgbe_media_type_fiber_fixed, 3803 ixgbe_media_type_fiber_qsfp, 3804 ixgbe_media_type_fiber_lco, 3805 ixgbe_media_type_copper, 3806 ixgbe_media_type_backplane, 3807 ixgbe_media_type_cx4, 3808 ixgbe_media_type_virtual 3809 }; 3810 3811 /* Flow Control Settings */ 3812 enum ixgbe_fc_mode { 3813 ixgbe_fc_none = 0, 3814 ixgbe_fc_rx_pause, 3815 ixgbe_fc_tx_pause, 3816 ixgbe_fc_full, 3817 ixgbe_fc_default 3818 }; 3819 3820 /* Smart Speed Settings */ 3821 #define IXGBE_SMARTSPEED_MAX_RETRIES 3 3822 enum ixgbe_smart_speed { 3823 ixgbe_smart_speed_auto = 0, 3824 ixgbe_smart_speed_on, 3825 ixgbe_smart_speed_off 3826 }; 3827 3828 /* PCI bus types */ 3829 enum ixgbe_bus_type { 3830 ixgbe_bus_type_unknown = 0, 3831 ixgbe_bus_type_pci, 3832 ixgbe_bus_type_pcix, 3833 ixgbe_bus_type_pci_express, 3834 ixgbe_bus_type_internal, 3835 ixgbe_bus_type_reserved 3836 }; 3837 3838 /* PCI bus speeds */ 3839 enum ixgbe_bus_speed { 3840 ixgbe_bus_speed_unknown = 0, 3841 ixgbe_bus_speed_33 = 33, 3842 ixgbe_bus_speed_66 = 66, 3843 ixgbe_bus_speed_100 = 100, 3844 ixgbe_bus_speed_120 = 120, 3845 ixgbe_bus_speed_133 = 133, 3846 ixgbe_bus_speed_2500 = 2500, 3847 ixgbe_bus_speed_5000 = 5000, 3848 ixgbe_bus_speed_8000 = 8000, 3849 ixgbe_bus_speed_reserved 3850 }; 3851 3852 /* PCI bus widths */ 3853 enum ixgbe_bus_width { 3854 ixgbe_bus_width_unknown = 0, 3855 ixgbe_bus_width_pcie_x1 = 1, 3856 ixgbe_bus_width_pcie_x2 = 2, 3857 ixgbe_bus_width_pcie_x4 = 4, 3858 ixgbe_bus_width_pcie_x8 = 8, 3859 ixgbe_bus_width_32 = 32, 3860 ixgbe_bus_width_64 = 64, 3861 ixgbe_bus_width_reserved 3862 }; 3863 3864 struct ixgbe_addr_filter_info { 3865 u32 num_mc_addrs; 3866 u32 rar_used_count; 3867 u32 mta_in_use; 3868 u32 overflow_promisc; 3869 bool user_set_promisc; 3870 }; 3871 3872 /* Bus parameters */ 3873 struct ixgbe_bus_info { 3874 enum ixgbe_bus_speed speed; 3875 enum ixgbe_bus_width width; 3876 enum ixgbe_bus_type type; 3877 3878 u16 func; 3879 u8 lan_id; 3880 u16 instance_id; 3881 }; 3882 3883 /* Flow control parameters */ 3884 struct ixgbe_fc_info { 3885 u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */ 3886 u32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */ 3887 u16 pause_time; /* Flow Control Pause timer */ 3888 bool send_xon; /* Flow control send XON */ 3889 bool strict_ieee; /* Strict IEEE mode */ 3890 bool disable_fc_autoneg; /* Do not autonegotiate FC */ 3891 bool fc_was_autonegged; /* Is current_mode the result of autonegging? */ 3892 enum ixgbe_fc_mode current_mode; /* FC mode in effect */ 3893 enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */ 3894 }; 3895 3896 /* 3897 * NetBSD currently uses traffic class 0 only. Other traffic classes aren't 3898 * used yet. When IXGBE_TC_COUNTER_NUM is set to lower than 3899 * IXGBE_DCB_MAX_TRAFFIC_CLASS (e.g. 1), other traffic classes' counters are 3900 * not used. It means we don't generate evcnt for them and don't add the values 3901 * in ixgbe_update_stats_counters(). 3902 */ 3903 #if !defined(IXGBE_TC_COUNTER_NUM) 3904 #define IXGBE_TC_COUNTER_NUM IXGBE_DCB_MAX_TRAFFIC_CLASS 3905 #endif 3906 #if ((IXGBE_TC_COUNTER_NUM < 1) \ 3907 || (IXGBE_TC_COUNTER_NUM > IXGBE_DCB_MAX_TRAFFIC_CLASS)) 3908 #error Wrong IXGBE_TC_COUNTER_NUM value 3909 #endif 3910 3911 /* Statistics counters collected by the MAC */ 3912 struct ixgbe_hw_stats { 3913 char namebuf[32]; 3914 struct evcnt ipcs; 3915 struct evcnt ipcs_bad; 3916 struct evcnt l4cs; 3917 struct evcnt l4cs_bad; 3918 3919 struct evcnt crcerrs; 3920 struct evcnt illerrc; 3921 struct evcnt errbc; 3922 struct evcnt mspdc; 3923 struct evcnt mbsdc; 3924 struct evcnt mpctotal; 3925 struct evcnt mpc[IXGBE_TC_COUNTER_NUM]; 3926 struct evcnt mlfc; 3927 struct evcnt mrfc; 3928 struct evcnt link_dn_cnt; 3929 struct evcnt rlec; 3930 struct evcnt lxontxc; 3931 struct evcnt lxonrxc; 3932 struct evcnt lxofftxc; 3933 struct evcnt lxoffrxc; 3934 struct evcnt pxontxc[IXGBE_TC_COUNTER_NUM]; 3935 struct evcnt pxonrxc[IXGBE_TC_COUNTER_NUM]; 3936 struct evcnt pxofftxc[IXGBE_TC_COUNTER_NUM]; 3937 struct evcnt pxoffrxc[IXGBE_TC_COUNTER_NUM]; 3938 struct evcnt prc64; 3939 struct evcnt prc127; 3940 struct evcnt prc255; 3941 struct evcnt prc511; 3942 struct evcnt prc1023; 3943 struct evcnt prc1522; 3944 struct evcnt gprc; 3945 struct evcnt bprc; 3946 struct evcnt mprc; 3947 struct evcnt gptc; 3948 struct evcnt gorc; 3949 struct evcnt gotc; 3950 struct evcnt rnbc[IXGBE_TC_COUNTER_NUM]; 3951 struct evcnt ruc; 3952 struct evcnt rfc; 3953 struct evcnt roc; 3954 struct evcnt rjc; 3955 struct evcnt mngprc; 3956 struct evcnt mngpdc; 3957 struct evcnt mngptc; 3958 struct evcnt tor; 3959 struct evcnt tpr; 3960 struct evcnt tpt; 3961 struct evcnt ptc64; 3962 struct evcnt ptc127; 3963 struct evcnt ptc255; 3964 struct evcnt ptc511; 3965 struct evcnt ptc1023; 3966 struct evcnt ptc1522; 3967 struct evcnt mptc; 3968 struct evcnt bptc; 3969 struct evcnt xec; 3970 struct evcnt qprc[16]; 3971 struct evcnt qptc[16]; 3972 struct evcnt qbrc[16]; 3973 struct evcnt qbtc[16]; 3974 struct evcnt qprdc[16]; 3975 struct evcnt pxon2offc[IXGBE_TC_COUNTER_NUM]; 3976 u64 fdirustat_add; 3977 u64 fdirustat_remove; 3978 u64 fdirfstat_fadd; 3979 u64 fdirfstat_fremove; 3980 u64 fdirmatch; 3981 u64 fdirmiss; 3982 struct evcnt fccrc; 3983 struct evcnt fclast; 3984 struct evcnt fcoerpdc; 3985 struct evcnt fcoeprc; 3986 struct evcnt fcoeptc; 3987 struct evcnt fcoedwrc; 3988 struct evcnt fcoedwtc; 3989 struct evcnt fcoe_noddp; 3990 struct evcnt fcoe_noddp_ext_buff; 3991 struct evcnt ldpcec; 3992 struct evcnt pcrc8ec; 3993 struct evcnt b2ospc; 3994 struct evcnt b2ogprc; 3995 struct evcnt o2bgptc; 3996 struct evcnt o2bspc; 3997 struct evcnt legint; /* legacy interrupts */ 3998 struct evcnt intzero; /* no legacy interrupt conditions */ 3999 }; 4000 4001 /* forward declaration */ 4002 struct ixgbe_hw; 4003 4004 /* iterator type for walking multicast address lists */ 4005 typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr, 4006 u32 *vmdq); 4007 4008 /* Function pointer table */ 4009 struct ixgbe_eeprom_operations { 4010 s32 (*init_params)(struct ixgbe_hw *); 4011 s32 (*read)(struct ixgbe_hw *, u16, u16 *); 4012 s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *); 4013 s32 (*write)(struct ixgbe_hw *, u16, u16); 4014 s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *); 4015 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *); 4016 s32 (*update_checksum)(struct ixgbe_hw *); 4017 s32 (*calc_checksum)(struct ixgbe_hw *); 4018 }; 4019 4020 struct ixgbe_mac_operations { 4021 s32 (*init_hw)(struct ixgbe_hw *); 4022 s32 (*reset_hw)(struct ixgbe_hw *); 4023 s32 (*start_hw)(struct ixgbe_hw *); 4024 s32 (*clear_hw_cntrs)(struct ixgbe_hw *); 4025 void (*enable_relaxed_ordering)(struct ixgbe_hw *); 4026 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); 4027 u64 (*get_supported_physical_layer)(struct ixgbe_hw *); 4028 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); 4029 s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *); 4030 s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *); 4031 s32 (*get_device_caps)(struct ixgbe_hw *, u16 *); 4032 s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *); 4033 s32 (*get_fcoe_boot_status)(struct ixgbe_hw *, u16 *); 4034 s32 (*stop_adapter)(struct ixgbe_hw *); 4035 s32 (*get_bus_info)(struct ixgbe_hw *); 4036 s32 (*negotiate_api_version)(struct ixgbe_hw *, int); 4037 void (*set_lan_id)(struct ixgbe_hw *); 4038 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*); 4039 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8); 4040 s32 (*setup_sfp)(struct ixgbe_hw *); 4041 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32); 4042 s32 (*disable_sec_rx_path)(struct ixgbe_hw *); 4043 s32 (*enable_sec_rx_path)(struct ixgbe_hw *); 4044 s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32); 4045 void (*release_swfw_sync)(struct ixgbe_hw *, u32); 4046 void (*init_swfw_sync)(struct ixgbe_hw *); 4047 s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *); 4048 s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool); 4049 4050 /* Link */ 4051 void (*disable_tx_laser)(struct ixgbe_hw *); 4052 void (*enable_tx_laser)(struct ixgbe_hw *); 4053 void (*flap_tx_laser)(struct ixgbe_hw *); 4054 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool); 4055 s32 (*setup_mac_link)(struct ixgbe_hw *, ixgbe_link_speed, bool); 4056 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool); 4057 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, 4058 bool *); 4059 void (*set_rate_select_speed)(struct ixgbe_hw *, ixgbe_link_speed); 4060 4061 /* Packet Buffer manipulation */ 4062 void (*setup_rxpba)(struct ixgbe_hw *, int, u32, int); 4063 4064 /* LED */ 4065 s32 (*led_on)(struct ixgbe_hw *, u32); 4066 s32 (*led_off)(struct ixgbe_hw *, u32); 4067 s32 (*blink_led_start)(struct ixgbe_hw *, u32); 4068 s32 (*blink_led_stop)(struct ixgbe_hw *, u32); 4069 s32 (*init_led_link_act)(struct ixgbe_hw *); 4070 4071 /* RAR, Multicast, VLAN */ 4072 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32); 4073 s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *); 4074 s32 (*clear_rar)(struct ixgbe_hw *, u32); 4075 s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32); 4076 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32); 4077 s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32); 4078 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32); 4079 s32 (*init_rx_addrs)(struct ixgbe_hw *); 4080 s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32, 4081 ixgbe_mc_addr_itr); 4082 s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32, 4083 ixgbe_mc_addr_itr, bool clear); 4084 s32 (*update_xcast_mode)(struct ixgbe_hw *, int); 4085 s32 (*get_link_state)(struct ixgbe_hw *hw, bool *link_state); 4086 s32 (*enable_mc)(struct ixgbe_hw *); 4087 s32 (*disable_mc)(struct ixgbe_hw *); 4088 s32 (*clear_vfta)(struct ixgbe_hw *); 4089 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool, bool); 4090 s32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, u32 *, u32, 4091 bool); 4092 s32 (*set_rlpml)(struct ixgbe_hw *, u16); 4093 s32 (*init_uta_tables)(struct ixgbe_hw *); 4094 void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int); 4095 void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int); 4096 s32 (*toggle_txdctl)(struct ixgbe_hw *hw, u32 vf_index); 4097 4098 /* Flow Control */ 4099 s32 (*fc_enable)(struct ixgbe_hw *); 4100 s32 (*setup_fc)(struct ixgbe_hw *); 4101 void (*fc_autoneg)(struct ixgbe_hw *); 4102 4103 /* Manageability interface */ 4104 s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8, u16, 4105 const char *); 4106 s32 (*bypass_rw) (struct ixgbe_hw *hw, u32 cmd, u32 *status); 4107 bool (*bypass_valid_rd) (u32 in_reg, u32 out_reg); 4108 s32 (*bypass_set) (struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action); 4109 s32 (*bypass_rd_eep) (struct ixgbe_hw *hw, u32 addr, u8 *value); 4110 void (*get_rtrup2tc)(struct ixgbe_hw *hw, u8 *map); 4111 void (*disable_rx)(struct ixgbe_hw *hw); 4112 void (*enable_rx)(struct ixgbe_hw *hw); 4113 void (*set_source_address_pruning)(struct ixgbe_hw *, bool, 4114 unsigned int); 4115 void (*set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int); 4116 s32 (*dmac_update_tcs)(struct ixgbe_hw *hw); 4117 s32 (*dmac_config_tcs)(struct ixgbe_hw *hw); 4118 s32 (*dmac_config)(struct ixgbe_hw *hw); 4119 s32 (*setup_eee)(struct ixgbe_hw *hw, bool enable_eee); 4120 s32 (*read_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32 *); 4121 s32 (*write_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32); 4122 void (*disable_mdd)(struct ixgbe_hw *hw); 4123 void (*enable_mdd)(struct ixgbe_hw *hw); 4124 void (*mdd_event)(struct ixgbe_hw *hw, u32 *vf_bitmap); 4125 void (*restore_mdd_vf)(struct ixgbe_hw *hw, u32 vf); 4126 bool (*fw_recovery_mode)(struct ixgbe_hw *hw); 4127 }; 4128 4129 struct ixgbe_phy_operations { 4130 s32 (*identify)(struct ixgbe_hw *); 4131 s32 (*identify_sfp)(struct ixgbe_hw *); 4132 s32 (*init)(struct ixgbe_hw *); 4133 s32 (*reset)(struct ixgbe_hw *); 4134 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *); 4135 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16); 4136 s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *); 4137 s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16); 4138 s32 (*setup_link)(struct ixgbe_hw *); 4139 s32 (*setup_internal_link)(struct ixgbe_hw *); 4140 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool); 4141 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *); 4142 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *); 4143 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *); 4144 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8); 4145 s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *); 4146 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *); 4147 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8); 4148 void (*i2c_bus_clear)(struct ixgbe_hw *); 4149 s32 (*check_overtemp)(struct ixgbe_hw *); 4150 s32 (*set_phy_power)(struct ixgbe_hw *, bool on); 4151 s32 (*enter_lplu)(struct ixgbe_hw *); 4152 s32 (*handle_lasi)(struct ixgbe_hw *hw); 4153 s32 (*read_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr, 4154 u8 *value); 4155 s32 (*write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr, 4156 u8 value); 4157 }; 4158 4159 struct ixgbe_link_operations { 4160 s32 (*read_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val); 4161 s32 (*read_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg, 4162 u16 *val); 4163 s32 (*write_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val); 4164 s32 (*write_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg, 4165 u16 val); 4166 }; 4167 4168 struct ixgbe_link_info { 4169 struct ixgbe_link_operations ops; 4170 u8 addr; 4171 }; 4172 4173 struct ixgbe_eeprom_info { 4174 struct ixgbe_eeprom_operations ops; 4175 enum ixgbe_eeprom_type type; 4176 u32 semaphore_delay; 4177 u16 word_size; 4178 u16 address_bits; 4179 u16 word_page_size; 4180 u16 ctrl_word_3; 4181 u8 nvm_image_ver_high; 4182 u8 nvm_image_ver_low; 4183 }; 4184 4185 #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01 4186 struct ixgbe_mac_info { 4187 struct ixgbe_mac_operations ops; 4188 enum ixgbe_mac_type type; 4189 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 4190 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 4191 u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 4192 /* prefix for World Wide Node Name (WWNN) */ 4193 u16 wwnn_prefix; 4194 /* prefix for World Wide Port Name (WWPN) */ 4195 u16 wwpn_prefix; 4196 #define IXGBE_MAX_MTA 128 4197 u32 mta_shadow[IXGBE_MAX_MTA]; 4198 s32 mc_filter_type; 4199 u32 mcft_size; 4200 u32 vft_size; 4201 u32 num_rar_entries; 4202 u32 rar_highwater; 4203 u32 rx_pb_size; 4204 u32 max_tx_queues; 4205 u32 max_rx_queues; 4206 u32 orig_autoc; 4207 u8 san_mac_rar_index; 4208 bool get_link_status; 4209 u32 orig_autoc2; 4210 u16 max_msix_vectors; 4211 bool arc_subsystem_valid; 4212 bool orig_link_settings_stored; 4213 bool autotry_restart; 4214 u8 flags; 4215 struct ixgbe_dmac_config dmac_config; 4216 bool set_lben; 4217 u32 max_link_up_time; 4218 u8 led_link_act; 4219 }; 4220 4221 struct ixgbe_phy_info { 4222 struct ixgbe_phy_operations ops; 4223 enum ixgbe_phy_type type; 4224 u32 addr; 4225 u32 id; 4226 enum ixgbe_sfp_type sfp_type; 4227 bool sfp_setup_needed; 4228 u32 revision; 4229 enum ixgbe_media_type media_type; 4230 u32 phy_semaphore_mask; 4231 bool reset_disable; 4232 bool force_10_100_autonego; 4233 ixgbe_autoneg_advertised autoneg_advertised; 4234 ixgbe_link_speed speeds_supported; 4235 ixgbe_link_speed eee_speeds_supported; 4236 ixgbe_link_speed eee_speeds_advertised; 4237 enum ixgbe_smart_speed smart_speed; 4238 bool smart_speed_active; 4239 bool multispeed_fiber; 4240 bool reset_if_overtemp; 4241 bool qsfp_shared_i2c_bus; 4242 u32 nw_mng_if_sel; 4243 }; 4244 4245 #include "ixgbe_mbx.h" 4246 4247 struct ixgbe_hw { 4248 struct ixgbe_softc *back; 4249 struct ixgbe_mac_info mac; 4250 struct ixgbe_addr_filter_info addr_ctrl; 4251 struct ixgbe_fc_info fc; 4252 struct ixgbe_phy_info phy; 4253 struct ixgbe_link_info link; 4254 struct ixgbe_eeprom_info eeprom; 4255 struct ixgbe_bus_info bus; 4256 struct ixgbe_mbx_info mbx; 4257 const u32 *mvals; 4258 u16 device_id; 4259 u16 vendor_id; 4260 u16 subsystem_device_id; 4261 u16 subsystem_vendor_id; 4262 u8 revision_id; 4263 bool adapter_stopped; 4264 int api_version; 4265 bool force_full_reset; 4266 bool allow_unsupported_sfp; 4267 bool wol_enabled; 4268 bool need_crosstalk_fix; 4269 bool need_unsupported_sfp_recovery; 4270 u32 quirks; 4271 }; 4272 4273 #define ixgbe_call_func(hw, func, params, error) \ 4274 (func != NULL) ? func params : error 4275 4276 /* Error Codes */ 4277 #define IXGBE_SUCCESS 0 4278 #define IXGBE_ERR_EEPROM -1 4279 #define IXGBE_ERR_EEPROM_CHECKSUM -2 4280 #define IXGBE_ERR_PHY -3 4281 #define IXGBE_ERR_CONFIG -4 4282 #define IXGBE_ERR_PARAM -5 4283 #define IXGBE_ERR_MAC_TYPE -6 4284 #define IXGBE_ERR_UNKNOWN_PHY -7 4285 #define IXGBE_ERR_LINK_SETUP -8 4286 #define IXGBE_ERR_ADAPTER_STOPPED -9 4287 #define IXGBE_ERR_INVALID_MAC_ADDR -10 4288 #define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11 4289 #define IXGBE_ERR_PRIMARY_REQUESTS_PENDING -12 4290 #define IXGBE_ERR_INVALID_LINK_SETTINGS -13 4291 #define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14 4292 #define IXGBE_ERR_RESET_FAILED -15 4293 #define IXGBE_ERR_SWFW_SYNC -16 4294 #define IXGBE_ERR_PHY_ADDR_INVALID -17 4295 #define IXGBE_ERR_I2C -18 4296 #define IXGBE_ERR_SFP_NOT_SUPPORTED -19 4297 #define IXGBE_ERR_SFP_NOT_PRESENT -20 4298 #define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21 4299 #define IXGBE_ERR_NO_SAN_ADDR_PTR -22 4300 #define IXGBE_ERR_FDIR_REINIT_FAILED -23 4301 #define IXGBE_ERR_EEPROM_VERSION -24 4302 #define IXGBE_ERR_NO_SPACE -25 4303 #define IXGBE_ERR_OVERTEMP -26 4304 #define IXGBE_ERR_FC_NOT_NEGOTIATED -27 4305 #define IXGBE_ERR_FC_NOT_SUPPORTED -28 4306 #define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30 4307 #define IXGBE_ERR_PBA_SECTION -31 4308 #define IXGBE_ERR_INVALID_ARGUMENT -32 4309 #define IXGBE_ERR_HOST_INTERFACE_COMMAND -33 4310 #define IXGBE_ERR_OUT_OF_MEM -34 4311 #define IXGBE_BYPASS_FW_WRITE_FAILURE -35 4312 #define IXGBE_ERR_FEATURE_NOT_SUPPORTED -36 4313 #define IXGBE_ERR_EEPROM_PROTECTED_REGION -37 4314 #define IXGBE_ERR_FDIR_CMD_INCOMPLETE -38 4315 #define IXGBE_ERR_FW_RESP_INVALID -39 4316 #define IXGBE_ERR_TOKEN_RETRY -40 4317 #define IXGBE_ERR_MBX -41 4318 #define IXGBE_ERR_MBX_NOMSG -42 4319 #define IXGBE_ERR_TIMEOUT -43 4320 4321 #define IXGBE_ERR_NOT_TRUSTED -50 /* XXX NetBSD */ 4322 #define IXGBE_ERR_NOT_IN_PROMISC -51 /* XXX NetBSD */ 4323 #define IXGBE_ERR_FAN_FAILURE -52 /* XXX NetBSD */ 4324 #define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF 4325 4326 #define BYPASS_PAGE_CTL0 0x00000000 4327 #define BYPASS_PAGE_CTL1 0x40000000 4328 #define BYPASS_PAGE_CTL2 0x80000000 4329 #define BYPASS_PAGE_M 0xc0000000 4330 #define BYPASS_WE 0x20000000 4331 4332 #define BYPASS_AUTO 0x0 4333 #define BYPASS_NOP 0x0 4334 #define BYPASS_NORM 0x1 4335 #define BYPASS_BYPASS 0x2 4336 #define BYPASS_ISOLATE 0x3 4337 4338 #define BYPASS_EVENT_MAIN_ON 0x1 4339 #define BYPASS_EVENT_AUX_ON 0x2 4340 #define BYPASS_EVENT_MAIN_OFF 0x3 4341 #define BYPASS_EVENT_AUX_OFF 0x4 4342 #define BYPASS_EVENT_WDT_TO 0x5 4343 #define BYPASS_EVENT_USR 0x6 4344 4345 #define BYPASS_MODE_OFF_M 0x00000003 4346 #define BYPASS_STATUS_OFF_M 0x0000000c 4347 #define BYPASS_AUX_ON_M 0x00000030 4348 #define BYPASS_MAIN_ON_M 0x000000c0 4349 #define BYPASS_MAIN_OFF_M 0x00000300 4350 #define BYPASS_AUX_OFF_M 0x00000c00 4351 #define BYPASS_WDTIMEOUT_M 0x00003000 4352 #define BYPASS_WDT_ENABLE_M 0x00004000 4353 #define BYPASS_WDT_VALUE_M 0x00070000 4354 4355 #define BYPASS_MODE_OFF_SHIFT 0 4356 #define BYPASS_STATUS_OFF_SHIFT 2 4357 #define BYPASS_AUX_ON_SHIFT 4 4358 #define BYPASS_MAIN_ON_SHIFT 6 4359 #define BYPASS_MAIN_OFF_SHIFT 8 4360 #define BYPASS_AUX_OFF_SHIFT 10 4361 #define BYPASS_WDTIMEOUT_SHIFT 12 4362 #define BYPASS_WDT_ENABLE_SHIFT 14 4363 #define BYPASS_WDT_TIME_SHIFT 16 4364 4365 #define BYPASS_WDT_1 0x0 4366 #define BYPASS_WDT_1_5 0x1 4367 #define BYPASS_WDT_2 0x2 4368 #define BYPASS_WDT_3 0x3 4369 #define BYPASS_WDT_4 0x4 4370 #define BYPASS_WDT_8 0x5 4371 #define BYPASS_WDT_16 0x6 4372 #define BYPASS_WDT_32 0x7 4373 #define BYPASS_WDT_OFF 0xffff 4374 4375 #define BYPASS_CTL1_TIME_M 0x01ffffff 4376 #define BYPASS_CTL1_VALID_M 0x02000000 4377 #define BYPASS_CTL1_OFFTRST_M 0x04000000 4378 #define BYPASS_CTL1_WDT_PET_M 0x08000000 4379 4380 #define BYPASS_CTL1_VALID 0x02000000 4381 #define BYPASS_CTL1_OFFTRST 0x04000000 4382 #define BYPASS_CTL1_WDT_PET 0x08000000 4383 4384 #define BYPASS_CTL2_DATA_M 0x000000ff 4385 #define BYPASS_CTL2_OFFSET_M 0x0000ff00 4386 #define BYPASS_CTL2_RW_M 0x00010000 4387 #define BYPASS_CTL2_HEAD_M 0x0ff00000 4388 4389 #define BYPASS_CTL2_OFFSET_SHIFT 8 4390 #define BYPASS_CTL2_HEAD_SHIFT 20 4391 4392 #define BYPASS_CTL2_RW 0x00010000 4393 4394 struct ixgbe_bypass_eeprom { 4395 u32 logs; 4396 u32 clear_off; 4397 u8 actions; 4398 }; 4399 4400 #define BYPASS_MAX_LOGS 43 4401 #define BYPASS_LOG_SIZE 5 4402 #define BYPASS_LOG_LINE_SIZE 37 4403 4404 #define BYPASS_EEPROM_VER_ADD 0x02 4405 4406 #define BYPASS_LOG_TIME_M 0x01ffffff 4407 #define BYPASS_LOG_TIME_VALID_M 0x02000000 4408 #define BYPASS_LOG_HEAD_M 0x04000000 4409 #define BYPASS_LOG_CLEAR_M 0x08000000 4410 #define BYPASS_LOG_EVENT_M 0xf0000000 4411 #define BYPASS_LOG_ACTION_M 0x03 4412 4413 #define BYPASS_LOG_EVENT_SHIFT 28 4414 #define BYPASS_LOG_CLEAR_SHIFT 24 /* bit offset */ 4415 4416 #define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4)) 4417 #define IXGBE_FUSES0_300MHZ (1 << 5) 4418 #define IXGBE_FUSES0_REV_MASK (3 << 6) 4419 4420 #define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010) 4421 #define IXGBE_KRM_LINK_S1(P) ((P) ? 0x8200 : 0x4200) 4422 #define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C) 4423 #define IXGBE_KRM_AN_CNTL_1(P) ((P) ? 0x822C : 0x422C) 4424 #define IXGBE_KRM_AN_CNTL_4(P) ((P) ? 0x8238 : 0x4238) 4425 #define IXGBE_KRM_AN_CNTL_8(P) ((P) ? 0x8248 : 0x4248) 4426 #define IXGBE_KRM_PCS_KX_AN(P) ((P) ? 0x9918 : 0x5918) 4427 #define IXGBE_KRM_PCS_KX_AN_LP(P) ((P) ? 0x991C : 0x591C) 4428 #define IXGBE_KRM_SGMII_CTRL(P) ((P) ? 0x82A0 : 0x42A0) 4429 #define IXGBE_KRM_LP_BASE_PAGE_HIGH(P) ((P) ? 0x836C : 0x436C) 4430 #define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634) 4431 #define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638) 4432 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00) 4433 #define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P) ? 0x8E00 : 0x4E00) 4434 #define IXGBE_KRM_PMD_FLX_MASK_ST20(P) ((P) ? 0x9054 : 0x5054) 4435 #define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P) ? 0x9520 : 0x5520) 4436 #define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00) 4437 4438 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA ~(0x3 << 20) 4439 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR (1u << 20) 4440 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_LR (0x2 << 20) 4441 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN (1u << 25) 4442 #define IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN (1u << 26) 4443 #define IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN (1u << 27) 4444 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10M ~(0x7 << 28) 4445 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_100M (1u << 28) 4446 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G (0x2 << 28) 4447 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G (0x3 << 28) 4448 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN (0x4 << 28) 4449 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_2_5G (0x7 << 28) 4450 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK (0x7 << 28) 4451 #define IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART (1u << 31) 4452 4453 #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B (1 << 9) 4454 #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS (1 << 11) 4455 4456 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (0x7 << 8) 4457 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2 << 8) 4458 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4 << 8) 4459 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN (1 << 12) 4460 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN (1 << 13) 4461 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ (1 << 14) 4462 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC (1 << 15) 4463 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX (1 << 16) 4464 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR (1 << 18) 4465 #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX (1 << 24) 4466 #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR (1 << 26) 4467 #define IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE (1 << 28) 4468 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE (1 << 29) 4469 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART (1UL << 31) 4470 4471 #define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE (1 << 28) 4472 #define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE (1 << 29) 4473 #define IXGBE_KRM_PCS_KX_AN_SYM_PAUSE (1 << 1) 4474 #define IXGBE_KRM_PCS_KX_AN_ASM_PAUSE (1 << 2) 4475 #define IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE (1 << 2) 4476 #define IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE (1 << 3) 4477 #define IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73 (1 << 29) 4478 #define IXGBE_KRM_AN_CNTL_8_LINEAR (1 << 0) 4479 #define IXGBE_KRM_AN_CNTL_8_LIMITING (1 << 1) 4480 4481 #define IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE (1 << 10) 4482 #define IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE (1 << 11) 4483 4484 #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D (1 << 12) 4485 #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D (1 << 19) 4486 4487 #define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN (1 << 6) 4488 #define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN (1 << 15) 4489 #define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN (1 << 16) 4490 4491 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL (1 << 4) 4492 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS (1 << 2) 4493 4494 #define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (0x3 << 16) 4495 4496 #define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN (1 << 1) 4497 #define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN (1 << 2) 4498 #define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN (1 << 3) 4499 #define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN (1UL << 31) 4500 4501 #define IXGBE_SB_IOSF_INDIRECT_CTRL 0x00011144 4502 #define IXGBE_SB_IOSF_INDIRECT_DATA 0x00011148 4503 4504 #define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT 0 4505 #define IXGBE_SB_IOSF_CTRL_ADDR_MASK 0xFF 4506 #define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT 18 4507 #define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK \ 4508 (0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT) 4509 #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT 20 4510 #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK \ 4511 (0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT) 4512 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT 28 4513 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7 4514 #define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT 31 4515 #define IXGBE_SB_IOSF_CTRL_BUSY (1UL << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT) 4516 #define IXGBE_SB_IOSF_TARGET_KR_PHY 0 4517 4518 #define IXGBE_NW_MNG_IF_SEL 0x00011178 4519 #define IXGBE_NW_MNG_IF_SEL_MDIO_ACT (1u << 1) 4520 #define IXGBE_NW_MNG_IF_SEL_MDIO_IF_MODE (1u << 2) 4521 #define IXGBE_NW_MNG_IF_SEL_EN_SHARED_MDIO (1u << 13) 4522 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10M (1u << 17) 4523 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_100M (1u << 18) 4524 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_1G (1u << 19) 4525 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G (1u << 20) 4526 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10G (1u << 21) 4527 #define IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE (1u << 25) 4528 #define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24) /* X552 reg field only */ 4529 #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT 3 4530 #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD \ 4531 (0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT) 4532 4533 /* Code Command (Flash I/F Interface) */ 4534 #define IXGBE_HOST_INTERFACE_FLASH_READ_CMD 0x30 4535 #define IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD 0x31 4536 #define IXGBE_HOST_INTERFACE_FLASH_WRITE_CMD 0x32 4537 #define IXGBE_HOST_INTERFACE_SHADOW_RAM_WRITE_CMD 0x33 4538 #define IXGBE_HOST_INTERFACE_FLASH_MODULE_UPDATE_CMD 0x34 4539 #define IXGBE_HOST_INTERFACE_FLASH_BLOCK_EREASE_CMD 0x35 4540 #define IXGBE_HOST_INTERFACE_SHADOW_RAM_DUMP_CMD 0x36 4541 #define IXGBE_HOST_INTERFACE_FLASH_INFO_CMD 0x37 4542 #define IXGBE_HOST_INTERFACE_APPLY_UPDATE_CMD 0x38 4543 #define IXGBE_HOST_INTERFACE_MASK_CMD 0x000000FF 4544 4545 /* Flags for hw.quirks */ 4546 #define IXGBE_QUIRK_MOD_ABS_INVERT __BIT(0) 4547 4548 #endif /* _IXGBE_TYPE_H_ */ 4549
Indexes created Sat Sep 20 22:09:52 GMT 2025