1 /* $NetBSD: cbiisc.c,v 1.34 2019/01/08 19:41:09 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 #ifdef __m68k__ 35 #include "opt_m68k_arch.h" 36 #endif 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: cbiisc.c,v 1.34 2019/01/08 19:41:09 jdolecek Exp $"); 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/errno.h> 46 #include <sys/ioctl.h> 47 #include <sys/device.h> 48 #include <sys/buf.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 52 #include <dev/scsipi/scsi_all.h> 53 #include <dev/scsipi/scsipi_all.h> 54 #include <dev/scsipi/scsiconf.h> 55 #include <dev/scsipi/scsi_message.h> 56 57 #include <machine/cpu.h> 58 59 #include <dev/ic/ncr53c9xreg.h> 60 #include <dev/ic/ncr53c9xvar.h> 61 62 #include <amiga/amiga/isr.h> 63 #include <amiga/dev/cbiiscvar.h> 64 #include <amiga/dev/zbusvar.h> 65 66 #ifdef __powerpc__ 67 #define badaddr(a) badaddr_read(a, 2, NULL) 68 #endif 69 70 int cbiiscmatch(device_t, cfdata_t, void *); 71 void cbiiscattach(device_t, device_t, void *); 72 73 /* Linkup to the rest of the kernel */ 74 CFATTACH_DECL_NEW(cbiisc, sizeof(struct cbiisc_softc), 75 cbiiscmatch, cbiiscattach, NULL, NULL); 76 77 /* 78 * Functions and the switch for the MI code. 79 */ 80 uint8_t cbiisc_read_reg(struct ncr53c9x_softc *, int); 81 void cbiisc_write_reg(struct ncr53c9x_softc *, int, uint8_t); 82 int cbiisc_dma_isintr(struct ncr53c9x_softc *); 83 void cbiisc_dma_reset(struct ncr53c9x_softc *); 84 int cbiisc_dma_intr(struct ncr53c9x_softc *); 85 int cbiisc_dma_setup(struct ncr53c9x_softc *, uint8_t **, 86 size_t *, int, size_t *); 87 void cbiisc_dma_go(struct ncr53c9x_softc *); 88 void cbiisc_dma_stop(struct ncr53c9x_softc *); 89 int cbiisc_dma_isactive(struct ncr53c9x_softc *); 90 91 struct ncr53c9x_glue cbiisc_glue = { 92 cbiisc_read_reg, 93 cbiisc_write_reg, 94 cbiisc_dma_isintr, 95 cbiisc_dma_reset, 96 cbiisc_dma_intr, 97 cbiisc_dma_setup, 98 cbiisc_dma_go, 99 cbiisc_dma_stop, 100 cbiisc_dma_isactive, 101 NULL, 102 }; 103 104 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 105 u_long cbiisc_max_dma = 1024; 106 extern int ser_open_speed; 107 108 u_long cbiisc_cnt_pio = 0; /* number of PIO transfers */ 109 u_long cbiisc_cnt_dma = 0; /* number of DMA transfers */ 110 u_long cbiisc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 111 u_long cbiisc_cnt_dma3 = 0; /* number of pages combined */ 112 113 #ifdef DEBUG 114 struct { 115 uint8_t hardbits; 116 uint8_t status; 117 uint8_t xx; 118 uint8_t yy; 119 } cbiisc_trace[128]; 120 int cbiisc_trace_ptr = 0; 121 int cbiisc_trace_enable = 1; 122 void cbiisc_dump(void); 123 #endif 124 125 /* 126 * if we are a Phase5 CyberSCSI II 127 */ 128 int 129 cbiiscmatch(device_t parent, cfdata_t cf, void *aux) 130 { 131 struct zbus_args *zap; 132 volatile uint8_t *regs; 133 134 zap = aux; 135 if (zap->manid != 0x2140 || zap->prodid != 25) 136 return 0; 137 regs = &((volatile uint8_t *)zap->va)[0x1ff03]; 138 if (badaddr((void *)__UNVOLATILE(regs))) 139 return 0; 140 regs[NCR_CFG1 * 4] = 0; 141 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 142 delay(5); 143 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 144 return 0; 145 return 1; 146 } 147 148 /* 149 * Attach this instance, and then all the sub-devices 150 */ 151 void 152 cbiiscattach(device_t parent, device_t self, void *aux) 153 { 154 struct cbiisc_softc *csc = device_private(self); 155 struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x; 156 struct zbus_args *zap; 157 extern u_long scsi_nosync; 158 extern int shift_nosync; 159 extern int ncr53c9x_debug; 160 161 /* 162 * Set up the glue for MI code early; we use some of it here. 163 */ 164 sc->sc_dev = self; 165 sc->sc_glue = &cbiisc_glue; 166 167 /* 168 * Save the regs 169 */ 170 zap = aux; 171 csc->sc_reg = &((volatile uint8_t *)zap->va)[0x1ff03]; 172 csc->sc_dmabase = &csc->sc_reg[0x80]; 173 174 sc->sc_freq = 40; /* Clocked at 40 MHz */ 175 176 aprint_normal(": address %p", csc->sc_reg); 177 178 sc->sc_id = 7; 179 180 /* 181 * It is necessary to try to load the 2nd config register here, 182 * to find out what rev the FAS chip is, else the ncr53c9x_reset 183 * will not set up the defaults correctly. 184 */ 185 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 186 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 187 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 188 sc->sc_rev = NCR_VARIANT_FAS216; 189 190 /* 191 * This is the value used to start sync negotiations 192 * Note that the NCR register "SYNCTP" is programmed 193 * in "clocks per byte", and has a minimum value of 4. 194 * The SCSI period used in negotiation is one-fourth 195 * of the time (in nanoseconds) needed to transfer one byte. 196 * Since the chip's clock is given in MHz, we have the following 197 * formula: 4 * period = (1000 / freq) * 4 198 */ 199 sc->sc_minsync = 1000 / sc->sc_freq; 200 201 /* 202 * get flags from -I argument and set cf_flags. 203 * NOTE: low 8 bits are to disable disconnect, and the next 204 * 8 bits are to disable sync. 205 */ 206 device_cfdata(self)->cf_flags |= (scsi_nosync >> shift_nosync) 207 & 0xffff; 208 shift_nosync += 16; 209 210 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 211 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 212 shift_nosync += 16; 213 214 #if 1 215 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 216 sc->sc_minsync = 0; 217 #endif 218 219 /* Really no limit, but since we want to fit into the TCR... */ 220 sc->sc_maxxfer = 64 * 1024; 221 222 /* 223 * Configure interrupts. 224 */ 225 csc->sc_isr.isr_intr = ncr53c9x_intr; 226 csc->sc_isr.isr_arg = sc; 227 csc->sc_isr.isr_ipl = 2; 228 add_isr(&csc->sc_isr); 229 230 /* 231 * Now try to attach all the sub-devices 232 */ 233 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 234 sc->sc_adapter.adapt_minphys = minphys; 235 ncr53c9x_attach(sc); 236 } 237 238 /* 239 * Glue functions. 240 */ 241 242 uint8_t 243 cbiisc_read_reg(struct ncr53c9x_softc *sc, int reg) 244 { 245 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 246 247 return csc->sc_reg[reg * 4]; 248 } 249 250 void 251 cbiisc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val) 252 { 253 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 254 uint8_t v = val; 255 256 csc->sc_reg[reg * 4] = v; 257 #ifdef DEBUG 258 if (cbiisc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ && 259 reg == NCR_CMD/* && csc->sc_active*/) { 260 cbiisc_trace[(cbiisc_trace_ptr - 1) & 127].yy = v; 261 /* printf(" cmd %x", v);*/ 262 } 263 #endif 264 } 265 266 int 267 cbiisc_dma_isintr(struct ncr53c9x_softc *sc) 268 { 269 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 270 271 if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 272 return 0; 273 274 if (sc->sc_state == NCR_CONNECTED) 275 csc->sc_reg[0x40] = CBIISC_PB_LED; 276 else 277 csc->sc_reg[0x40] = 0; 278 279 #ifdef DEBUG 280 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ cbiisc_trace_enable) { 281 cbiisc_trace[cbiisc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4]; 282 cbiisc_trace[cbiisc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4]; 283 cbiisc_trace[cbiisc_trace_ptr].yy = csc->sc_active; 284 cbiisc_trace_ptr = (cbiisc_trace_ptr + 1) & 127; 285 } 286 #endif 287 return 1; 288 } 289 290 void 291 cbiisc_dma_reset(struct ncr53c9x_softc *sc) 292 { 293 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 294 295 csc->sc_active = 0; 296 } 297 298 int 299 cbiisc_dma_intr(struct ncr53c9x_softc *sc) 300 { 301 register struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 302 register int cnt; 303 304 NCR_DMA(("cbiisc_dma_intr: cnt %d int %x stat %x fifo %d ", 305 csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 306 csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 307 if (csc->sc_active == 0) { 308 printf("cbiisc_intr--inactive DMA\n"); 309 return -1; 310 } 311 312 /* update sc_dmaaddr and sc_pdmalen */ 313 cnt = csc->sc_reg[NCR_TCL * 4]; 314 cnt += csc->sc_reg[NCR_TCM * 4] << 8; 315 cnt += csc->sc_reg[NCR_TCH * 4] << 16; 316 if (!csc->sc_datain) { 317 cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 318 csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 319 } 320 cnt = csc->sc_dmasize - cnt; /* number of bytes transferred */ 321 NCR_DMA(("DMA xferred %d\n", cnt)); 322 if (csc->sc_xfr_align) { 323 memcpy(*csc->sc_dmaaddr, csc->sc_alignbuf, cnt); 324 csc->sc_xfr_align = 0; 325 } 326 *csc->sc_dmaaddr += cnt; 327 *csc->sc_pdmalen -= cnt; 328 csc->sc_active = 0; 329 return 0; 330 } 331 332 int 333 cbiisc_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 334 int datain, size_t *dmasize) 335 { 336 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 337 paddr_t pa; 338 uint8_t *ptr; 339 size_t xfer; 340 341 csc->sc_dmaaddr = addr; 342 csc->sc_pdmalen = len; 343 csc->sc_datain = datain; 344 csc->sc_dmasize = *dmasize; 345 /* 346 * DMA can be nasty for high-speed serial input, so limit the 347 * size of this DMA operation if the serial port is running at 348 * a high speed (higher than 19200 for now - should be adjusted 349 * based on CPU type and speed?). 350 * XXX - add serial speed check XXX 351 */ 352 if (ser_open_speed > 19200 && cbiisc_max_dma != 0 && 353 csc->sc_dmasize > cbiisc_max_dma) 354 csc->sc_dmasize = cbiisc_max_dma; 355 ptr = *addr; /* Kernel virtual address */ 356 pa = kvtop(ptr); /* Physical address of DMA */ 357 xfer = uimin(csc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1))); 358 csc->sc_xfr_align = 0; 359 /* 360 * If output and unaligned, stuff odd byte into FIFO 361 */ 362 if (datain == 0 && (int)ptr & 1) { 363 NCR_DMA(("cbiisc_dma_setup: align byte written to fifo\n")); 364 pa++; 365 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 366 csc->sc_reg[NCR_FIFO * 4] = *ptr++; 367 } 368 /* 369 * If unaligned address, read unaligned bytes into alignment buffer 370 */ 371 else if ((int)ptr & 1) { 372 pa = kvtop((void *)&csc->sc_alignbuf); 373 xfer = csc->sc_dmasize = uimin(xfer, sizeof(csc->sc_alignbuf)); 374 NCR_DMA(("cbiisc_dma_setup: align read by %d bytes\n", xfer)); 375 csc->sc_xfr_align = 1; 376 } 377 ++cbiisc_cnt_dma; /* number of DMA operations */ 378 379 while (xfer < csc->sc_dmasize) { 380 if ((pa + xfer) != kvtop(*addr + xfer)) 381 break; 382 if ((csc->sc_dmasize - xfer) < PAGE_SIZE) 383 xfer = csc->sc_dmasize; 384 else 385 xfer += PAGE_SIZE; 386 ++cbiisc_cnt_dma3; 387 } 388 if (xfer != *len) 389 ++cbiisc_cnt_dma2; 390 391 csc->sc_dmasize = xfer; 392 *dmasize = csc->sc_dmasize; 393 csc->sc_pa = pa; 394 #if defined(M68040) || defined(M68060) 395 if (mmutype == MMU_68040) { 396 if (csc->sc_xfr_align) { 397 dma_cachectl(csc->sc_alignbuf, 398 sizeof(csc->sc_alignbuf)); 399 } 400 else 401 dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize); 402 } 403 #endif 404 405 if (csc->sc_datain) 406 pa &= ~1; 407 else 408 pa |= 1; 409 csc->sc_dmabase[0] = (uint8_t)(pa >> 24); 410 csc->sc_dmabase[4] = (uint8_t)(pa >> 16); 411 csc->sc_dmabase[8] = (uint8_t)(pa >> 8); 412 csc->sc_dmabase[12] = (uint8_t)(pa); 413 csc->sc_active = 1; 414 return 0; 415 } 416 417 void 418 cbiisc_dma_go(struct ncr53c9x_softc *sc) 419 { 420 } 421 422 void 423 cbiisc_dma_stop(struct ncr53c9x_softc *sc) 424 { 425 } 426 427 int 428 cbiisc_dma_isactive(struct ncr53c9x_softc *sc) 429 { 430 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 431 432 return csc->sc_active; 433 } 434 435 #ifdef DEBUG 436 void 437 cbiisc_dump(void) 438 { 439 int i; 440 441 i = cbiisc_trace_ptr; 442 printf("cbiisc_trace dump: ptr %x\n", cbiisc_trace_ptr); 443 do { 444 if (cbiisc_trace[i].hardbits == 0) { 445 i = (i + 1) & 127; 446 continue; 447 } 448 printf("%02x%02x%02x%02x(", cbiisc_trace[i].hardbits, 449 cbiisc_trace[i].status, cbiisc_trace[i].xx, cbiisc_trace[i].yy); 450 if (cbiisc_trace[i].status & NCRSTAT_INT) 451 printf("NCRINT/"); 452 if (cbiisc_trace[i].status & NCRSTAT_TC) 453 printf("NCRTC/"); 454 switch(cbiisc_trace[i].status & NCRSTAT_PHASE) { 455 case 0: 456 printf("dataout"); break; 457 case 1: 458 printf("datain"); break; 459 case 2: 460 printf("cmdout"); break; 461 case 3: 462 printf("status"); break; 463 case 6: 464 printf("msgout"); break; 465 case 7: 466 printf("msgin"); break; 467 default: 468 printf("phase%d?", cbiisc_trace[i].status & NCRSTAT_PHASE); 469 } 470 printf(") "); 471 i = (i + 1) & 127; 472 } while (i != cbiisc_trace_ptr); 473 printf("\n"); 474 } 475 #endif 476
Indexes created Sat Sep 20 22:09:52 GMT 2025