| /src/sys/arch/evbmips/rasoc/ |
| autoconf.c | 137 const uint32_t cfg1 = bus_space_read_4(ma->ma_memt, local in function:device_register
139 if ((cfg1 & SYSCTL_CFG1_USB0_HOST_MODE) == 0) {
142 cfg1 | SYSCTL_CFG1_USB0_HOST_MODE);
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| /src/sys/arch/evbarm/iyonix/ |
| autoconf.c | 114 prop_number_t cfg1, cfg2, swdpin; local in function:device_register
122 cfg1 = prop_number_create_integer(0);
123 KASSERT(cfg1 != NULL);
134 SETPROP("i82543-cfg1", cfg1);
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| /src/sys/arch/iyonix/iyonix/ |
| autoconf.c | 114 prop_number_t cfg1, cfg2, swdpin; local in function:device_register
122 cfg1 = prop_number_create_integer(0);
123 KASSERT(cfg1 != NULL);
134 SETPROP("i82543-cfg1", cfg1);
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| /src/sys/arch/mips/mips/ |
| cache.c | 1067 uint32_t cfg, cfg1; local in function:mips_config_cache_modern
1070 cfg1 = mipsNN_cp0_config1_read();
1073 cfg1 &= ~MIPSNN_CFG1_IL_MASK;
1074 cfg1 &= ~MIPSNN_CFG1_DL_MASK;
1075 mipsNN_cp0_config1_write(cfg1);
1079 switch (MIPSNN_GET(CFG1_DL, cfg1)) {
1097 if (MIPSNN_GET(CFG1_DS, cfg1) == MIPSNN_CFG1_DS_RSVD)
1099 mci->mci_pdcache_line_size = MIPSNN_CFG1_DL(cfg1);
1101 mci->mci_pdcache_line_size * MIPSNN_CFG1_DS(cfg1);
1102 mci->mci_pdcache_ways = MIPSNN_CFG1_DA(cfg1) + 1
[all...] |
| mips_machdep.c | 1190 uint32_t cfg, cfg1, cfg4; local in function:mips_vector_init
1193 cfg1 = mipsNN_cp0_config1_read();
1248 opts->mips_num_tlb_entries = MIPSNN_CFG1_MS(cfg1);
1538 uint32_t cfg1; local in function:cpu_identify
1547 cfg1 = mipsNN_cp0_config1_read();
1548 if (cfg1 & MIPSNN_CFG1_FP)
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| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/ |
| nouveau_dispnv04_arb.c | 207 uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1); local in function:nv04_update_arb
229 sim_data.mem_latency = cfg1 & 0xf;
230 sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1);
|
| /src/sys/dev/ic/ |
| igpio.c | 530 bus_addr_t cfg0, cfg1; local in function:igpio_pin_ctl
536 cfg1 = igpio_pincfg(ib, pin, IGPIO_PADCFG1);
541 val1 = bus_space_read_4(sc->sc_bst, sc->sc_bsh[ib->ib_barno], cfg1);
593 bus_space_write_4(sc->sc_bst, sc->sc_bsh[ib->ib_barno], cfg1, newval1);
|
| rtw.c | 2858 uint8_t cfg0, cfg1; local in function:rtw_led_init
2866 cfg1 = RTW_READ8(regs, RTW_CONFIG1);
2868 ("%s: read %" PRIx8 " from reg[CONFIG1]\n", __func__, cfg1));
2870 cfg1 &= ~RTW_CONFIG1_LEDS_MASK;
2871 cfg1 |= RTW_CONFIG1_LEDS_TX_RX;
2872 RTW_WRITE8(regs, RTW_CONFIG1, cfg1);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dsi_vbt.c | 278 u16 cfg0, cfg1; local in function:chv_exec_gpio
316 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);
319 vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
|
| /src/sys/dev/pci/ |
| if_et.c | 451 uint32_t cfg1, cfg2, ctrl; local in function:et_miibus_statchg
476 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1);
477 cfg1 &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW |
508 cfg1 |= ET_MAC_CFG1_TXFLOW;
511 cfg1 |= ET_MAC_CFG1_RXFLOW;
517 cfg1 |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN;
518 CSR_WRITE_4(sc, ET_MAC_CFG1, cfg1);
523 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1);
524 if ((cfg1 & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) ==
|
| if_wm.c | 2027 uint16_t cfg1, cfg2, swdpin, nvmword; local in function:wm_attach
2784 pn = prop_dictionary_get(dict, "i82543-cfg1");
2787 cfg1 = (uint16_t) prop_number_signed_value(pn);
2789 if (wm_nvm_read(sc, NVM_OFF_CFG1, 1, &cfg1)) {
2790 aprint_error_dev(sc->sc_dev, "unable to read CFG1\n");
2938 if (cfg1 & NVM_CFG1_ILOS)
2958 ((cfg1 >> NVM_CFG1_SWDPIO_SHIFT) & 0xf) <<
2973 if (cfg1 & NVM_CFG1_IPS0)
2975 if (cfg1 & NVM_CFG1_IPS1)
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/ |
| nouveau_nvkm_subdev_fb_ramgk104.c | 1558 u32 cfg1 = nvkm_rd32(device, 0x110204 + (i * 0x1000)); local in function:gk104_ram_new_
1559 if (tmp && tmp != cfg1) {
1563 tmp = cfg1;
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