1 /* $NetBSD: ciss_pci.c,v 1.23 2023/12/20 05:08:34 thorpej Exp $ */ 2 /* $OpenBSD: ciss_pci.c,v 1.9 2005/12/13 15:56:01 brad Exp $ */ 3 4 /* 5 * Copyright (c) 2005 Michael Shalayeff 6 * All rights reserved. 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN 17 * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT 18 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/cdefs.h> 22 __KERNEL_RCSID(0, "$NetBSD: ciss_pci.c,v 1.23 2023/12/20 05:08:34 thorpej Exp $"); 23 24 #include <sys/param.h> 25 #include <sys/systm.h> 26 #include <sys/kernel.h> 27 #include <sys/device.h> 28 29 #include <dev/pci/pcidevs.h> 30 #include <dev/pci/pcivar.h> 31 32 #include <sys/bus.h> 33 34 #include <dev/scsipi/scsipi_all.h> 35 #include <dev/scsipi/scsipi_disk.h> 36 #include <dev/scsipi/scsipiconf.h> 37 38 #include <dev/ic/cissreg.h> 39 #include <dev/ic/cissvar.h> 40 41 #define CISS_BAR 0x10 42 43 int ciss_pci_match(device_t, cfdata_t, void *); 44 void ciss_pci_attach(device_t, device_t, void *); 45 46 CFATTACH_DECL_NEW(ciss_pci, sizeof(struct ciss_softc), 47 ciss_pci_match, ciss_pci_attach, NULL, NULL); 48 49 50 static const struct { 51 int vendor; 52 int product; 53 const char *name; 54 } ciss_pci_devices[] = { 55 #define CISS_PCI_DEVICE(v, p, d) { PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p, d } 56 CISS_PCI_DEVICE(COMPAQ, CSA532, "Compaq Smart Array 532"), 57 CISS_PCI_DEVICE(COMPAQ, CSA5300, "Compaq Smart Array 5300 V1"), 58 CISS_PCI_DEVICE(COMPAQ, CSA5300_2, "Compaq Smart Array 5300 V2"), 59 CISS_PCI_DEVICE(COMPAQ, CSA5312, "Compaq Smart Array 5312"), 60 CISS_PCI_DEVICE(COMPAQ, CSA5i, "Compaq Smart Array 5i"), 61 CISS_PCI_DEVICE(COMPAQ, CSA5i_2, "Compaq Smart Array 5i V2"), 62 CISS_PCI_DEVICE(COMPAQ, CSA6i, "Compaq Smart Array 6i"), 63 CISS_PCI_DEVICE(COMPAQ, CSA641, "Compaq Smart Array 641"), 64 CISS_PCI_DEVICE(COMPAQ, CSA642, "Compaq Smart Array 642"), 65 CISS_PCI_DEVICE(COMPAQ, CSA6400, "Compaq Smart Array 6400"), 66 CISS_PCI_DEVICE(COMPAQ, CSA6400EM, "Compaq Smart Array 6400EM"), 67 CISS_PCI_DEVICE(COMPAQ, CSA6422, "Compaq Smart Array 6422"), 68 CISS_PCI_DEVICE(COMPAQ, CSA64XX, "Compaq Smart Array 64XX"), 69 CISS_PCI_DEVICE(HP, HPSAE200, "Smart Array E200"), 70 CISS_PCI_DEVICE(HP, HPSAE200I_1, "HP Smart Array E200I-1"), 71 CISS_PCI_DEVICE(HP, HPSAE200I_2, "HP Smart Array E200I-2"), 72 CISS_PCI_DEVICE(HP, HPSAE200I_3, "HP Smart Array E200I-3"), 73 CISS_PCI_DEVICE(HP, HPSAP600, "HP Smart Array P600"), 74 CISS_PCI_DEVICE(HP, HPSAP800, "HP Smart Array P800"), 75 CISS_PCI_DEVICE(HP, HPSAV100, "HP Smart Array V100"), 76 CISS_PCI_DEVICE(HP, HPSA_1, "HP Smart Array 1"), 77 CISS_PCI_DEVICE(HP, HPSA_2, "HP Smart Array 2"), 78 CISS_PCI_DEVICE(HP, HPSA_3, "HP Smart Array 3"), 79 CISS_PCI_DEVICE(HP, HPSA_4, "HP Smart Array 4"), 80 CISS_PCI_DEVICE(HP, HPSA_5, "HP Smart Array 5"), 81 CISS_PCI_DEVICE(HP, HPSA_6, "HP Smart Array 6"), 82 CISS_PCI_DEVICE(HP, HPSA_7, "HP Smart Array 7"), 83 CISS_PCI_DEVICE(HP, HPSA_8, "HP Smart Array 8"), 84 CISS_PCI_DEVICE(HP, HPSA_9, "HP Smart Array 9"), 85 CISS_PCI_DEVICE(HP, HPSA_10, "HP Smart Array 10"), 86 CISS_PCI_DEVICE(HP, HPSA_11, "HP Smart Array 11"), 87 CISS_PCI_DEVICE(HP, HPSA_12, "HP Smart Array 12"), 88 CISS_PCI_DEVICE(HP, HPSA_13, "HP Smart Array 13"), 89 CISS_PCI_DEVICE(HP, HPSA_P700M, "Smart Array P700m"), 90 CISS_PCI_DEVICE(HP, HPSA_P212, "Smart Array P212"), 91 CISS_PCI_DEVICE(HP, HPSA_P410, "Smart Array P410"), 92 CISS_PCI_DEVICE(HP, HPSA_P410I, "Smart Array P410i"), 93 CISS_PCI_DEVICE(HP, HPSA_P411, "Smart Array P411"), 94 CISS_PCI_DEVICE(HP, HPSA_P812, "Smart Array P822"), 95 CISS_PCI_DEVICE(HP, HPSA_P712M, "Smart Array P712m"), 96 CISS_PCI_DEVICE(HP, HPSA_14, "Smart Array 14"), 97 CISS_PCI_DEVICE(HP, HPSA_P222, "Smart Array P222"), 98 CISS_PCI_DEVICE(HP, HPSA_P420, "Smart Array P420"), 99 CISS_PCI_DEVICE(HP, HPSA_P421, "Smart Array P421"), 100 CISS_PCI_DEVICE(HP, HPSA_P822, "Smart Array P822"), 101 CISS_PCI_DEVICE(HP, HPSA_P420I, "Smart Array P420i"), 102 CISS_PCI_DEVICE(HP, HPSA_P220I, "Smart Array P220i"), 103 CISS_PCI_DEVICE(HP, HPSA_P721I, "Smart Array P721i"), 104 CISS_PCI_DEVICE(HP, HPSA_P430I, "Smart Array P430i"), 105 CISS_PCI_DEVICE(HP, HPSA_P830I, "Smart Array P830i"), 106 CISS_PCI_DEVICE(HP, HPSA_P430, "Smart Array P430"), 107 CISS_PCI_DEVICE(HP, HPSA_P431, "Smart Array P431"), 108 CISS_PCI_DEVICE(HP, HPSA_P830, "Smart Array P830"), 109 CISS_PCI_DEVICE(HP, HPSA_P731M, "Smart Array P731m"), 110 CISS_PCI_DEVICE(HP, HPSA_P230I, "Smart Array P230i"), 111 CISS_PCI_DEVICE(HP, HPSA_P530, "Smart Array P530"), 112 CISS_PCI_DEVICE(HP, HPSA_P531, "Smart Array P531"), 113 CISS_PCI_DEVICE(HP, HPSA_P244BR, "Smart Array P244br"), 114 CISS_PCI_DEVICE(HP, HPSA_P741M, "Smart Array P741m"), 115 CISS_PCI_DEVICE(HP, HPSA_H240AR, "Smart Array H240ar"), 116 CISS_PCI_DEVICE(HP, HPSA_P440AR, "Smart Array H440ar"), 117 CISS_PCI_DEVICE(HP, HPSA_P840AR, "Smart Array P840ar"), 118 CISS_PCI_DEVICE(HP, HPSA_P440, "Smart Array P440"), 119 CISS_PCI_DEVICE(HP, HPSA_P441, "Smart Array P441"), 120 CISS_PCI_DEVICE(HP, HPSA_P841, "Smart Array P841"), 121 CISS_PCI_DEVICE(HP, HPSA_H244BR, "Smart Array H244br"), 122 CISS_PCI_DEVICE(HP, HPSA_H240, "Smart Array H240"), 123 CISS_PCI_DEVICE(HP, HPSA_H241, "Smart Array H241"), 124 CISS_PCI_DEVICE(HP, HPSA_P246BR, "Smart Array P246br"), 125 CISS_PCI_DEVICE(HP, HPSA_P840, "Smart Array P840"), 126 CISS_PCI_DEVICE(HP, HPSA_P542D, "Smart Array P542d"), 127 CISS_PCI_DEVICE(HP, HPSA_P240NR, "Smart Array P240nr"), 128 CISS_PCI_DEVICE(HP, HPSA_H240NR, "Smart Array H240nr"), 129 }; 130 131 int 132 ciss_pci_match(device_t parent, cfdata_t match, void *aux) 133 { 134 struct pci_attach_args *pa = aux; 135 pcireg_t reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 136 int i; 137 138 for (i = 0; i < __arraycount(ciss_pci_devices); i++) 139 { 140 if ((PCI_VENDOR(pa->pa_id) == ciss_pci_devices[i].vendor && 141 PCI_PRODUCT(pa->pa_id) == ciss_pci_devices[i].product) || 142 (PCI_VENDOR(reg) == ciss_pci_devices[i].vendor && 143 PCI_PRODUCT(reg) == ciss_pci_devices[i].product)) 144 return 1; 145 } 146 147 return 0; 148 } 149 150 void 151 ciss_pci_attach(device_t parent, device_t self, void *aux) 152 { 153 struct ciss_softc *sc = device_private(self); 154 struct pci_attach_args *pa = aux; 155 bus_size_t size, cfgsz; 156 pci_intr_handle_t *ih; 157 const char *intrstr; 158 int cfg_bar, memtype; 159 pcireg_t reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 160 int i; 161 char intrbuf[PCI_INTRSTR_LEN]; 162 int (*intr_handler)(void *); 163 164 sc->sc_dev = self; 165 166 aprint_naive("\n"); 167 for (i = 0; i < __arraycount(ciss_pci_devices); i++) 168 { 169 if ((PCI_VENDOR(pa->pa_id) == ciss_pci_devices[i].vendor && 170 PCI_PRODUCT(pa->pa_id) == ciss_pci_devices[i].product) || 171 (PCI_VENDOR(reg) == ciss_pci_devices[i].vendor && 172 PCI_PRODUCT(reg) == ciss_pci_devices[i].product)) 173 { 174 aprint_normal(": %s\n", ciss_pci_devices[i].name); 175 break; 176 } 177 } 178 179 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, CISS_BAR); 180 if (memtype != (PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT) && 181 memtype != (PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT)) { 182 aprint_error_dev(self, "wrong BAR type\n"); 183 return; 184 } 185 if (pci_mapreg_map(pa, CISS_BAR, memtype, 0, 186 &sc->sc_iot, &sc->sc_ioh, NULL, &size)) { 187 aprint_error_dev(self, "can't map controller i/o space\n"); 188 return; 189 } 190 sc->sc_dmat = pa->pa_dmat; 191 192 sc->iem = CISS_INTR_OPQ_SA5; 193 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 194 if (PCI_VENDOR(reg) == PCI_VENDOR_COMPAQ && 195 (PCI_PRODUCT(reg) == PCI_PRODUCT_COMPAQ_CSA5i || 196 PCI_PRODUCT(reg) == PCI_PRODUCT_COMPAQ_CSA532 || 197 PCI_PRODUCT(reg) == PCI_PRODUCT_COMPAQ_CSA5312)) 198 sc->iem = CISS_INTR_OPQ_SA5B; 199 200 cfg_bar = bus_space_read_2(sc->sc_iot, sc->sc_ioh, CISS_CFG_BAR); 201 sc->cfgoff = bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_CFG_OFF); 202 if (cfg_bar != CISS_BAR) { 203 if (pci_mapreg_map(pa, cfg_bar, PCI_MAPREG_TYPE_MEM, 0, 204 NULL, &sc->cfg_ioh, NULL, &cfgsz)) { 205 aprint_error_dev(self, 206 "can't map controller config space\n"); 207 bus_space_unmap(sc->sc_iot, sc->sc_ioh, size); 208 return; 209 } 210 } else { 211 sc->cfg_ioh = sc->sc_ioh; 212 cfgsz = size; 213 } 214 215 if (sc->cfgoff + sizeof(struct ciss_config) > cfgsz) { 216 aprint_error_dev(self, "unfit config space\n"); 217 bus_space_unmap(sc->sc_iot, sc->sc_ioh, size); 218 if (cfg_bar != CISS_BAR) 219 bus_space_unmap(sc->sc_iot, sc->cfg_ioh, cfgsz); 220 return; 221 } 222 223 /* Read the configuration */ 224 bus_space_read_region_4(sc->sc_iot, sc->cfg_ioh, sc->cfgoff, 225 (u_int32_t *)&sc->cfg, sizeof(sc->cfg) / 4); 226 227 /* disable interrupts until ready */ 228 bus_space_write_4(sc->sc_iot, sc->sc_ioh, CISS_IMR, 229 bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_IMR) | 230 sc->iem | CISS_INTR_OPQ | CISS_INTR_MSI); 231 232 int counts[PCI_INTR_TYPE_SIZE] = { 233 [PCI_INTR_TYPE_INTX] = 1, 234 [PCI_INTR_TYPE_MSI] = 0, 235 [PCI_INTR_TYPE_MSIX] = 0, 236 }; 237 int max_type = PCI_INTR_TYPE_INTX; 238 239 /* 240 * Allow MSI/MSI-X only if PERFORMANT method is supported, SIMPLE 241 * doesn't seem to work with MSI. 242 */ 243 if (CISS_PERF_SUPPORTED(sc)) { 244 #if 1 245 counts[PCI_INTR_TYPE_MSI] = counts[PCI_INTR_TYPE_MSIX] = 1; 246 max_type = PCI_INTR_TYPE_MSIX; 247 #endif 248 sc->iem |= CISS_INTR_OPQ | CISS_INTR_MSI; 249 } 250 251 if (pci_intr_alloc(pa, &ih, counts, max_type)) { 252 aprint_error_dev(self, "can't map interrupt\n"); 253 bus_space_unmap(sc->sc_iot, sc->sc_ioh, size); 254 if (cfg_bar != CISS_BAR) 255 bus_space_unmap(sc->sc_iot, sc->cfg_ioh, cfgsz); 256 return; 257 } 258 intrstr = pci_intr_string(pa->pa_pc, ih[0], intrbuf, sizeof(intrbuf)); 259 260 switch (pci_intr_type(pa->pa_pc, ih[0])) { 261 case PCI_INTR_TYPE_INTX: 262 intr_handler = CISS_PERF_SUPPORTED(sc) 263 ? ciss_intr_perf_intx : ciss_intr_simple_intx; 264 break; 265 default: 266 KASSERT(CISS_PERF_SUPPORTED(sc)); 267 intr_handler = ciss_intr_perf_msi; 268 break; 269 } 270 271 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih[0], IPL_BIO, 272 intr_handler, sc, device_xname(self)); 273 if (!sc->sc_ih) { 274 aprint_error_dev(sc->sc_dev, "can't establish interrupt"); 275 if (intrstr) 276 aprint_error(" at %s", intrstr); 277 aprint_error("\n"); 278 pci_intr_release(pa->pa_pc, ih, 1); 279 bus_space_unmap(sc->sc_iot, sc->sc_ioh, size); 280 if (cfg_bar != CISS_BAR) 281 bus_space_unmap(sc->sc_iot, sc->cfg_ioh, cfgsz); 282 return; 283 } 284 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 285 286 aprint_normal("%s", device_xname(sc->sc_dev)); 287 if (ciss_attach(sc)) { 288 pci_intr_disestablish(pa->pa_pc, sc->sc_ih); 289 sc->sc_ih = NULL; 290 bus_space_unmap(sc->sc_iot, sc->sc_ioh, size); 291 if (cfg_bar != CISS_BAR) 292 bus_space_unmap(sc->sc_iot, sc->cfg_ioh, cfgsz); 293 return; 294 } 295 296 /* enable interrupts now */ 297 bus_space_write_4(sc->sc_iot, sc->sc_ioh, CISS_IMR, 298 bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_IMR) & ~sc->iem); 299 } 300
Indexes created Thu Oct 02 01:09:59 GMT 2025