| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| meson8.dtsi | 6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
29 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
31 clocks = <&clkc CLKID_CPUCLK>;
41 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
43 clocks = <&clkc CLKID_CPUCLK>;
53 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
55 clocks = <&clkc CLKID_CPUCLK>;
65 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>
611 clkc: clock-controller { label
[all...] |
| meson8b.dtsi | 7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
27 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
29 clocks = <&clkc CLKID_CPUCLK>;
39 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
41 clocks = <&clkc CLKID_CPUCLK>;
51 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
53 clocks = <&clkc CLKID_CPUCLK>;
63 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>
589 clkc: clock-controller { label
[all...] |
| zynq-7000.dtsi | 19 clocks = <&clkc 3>;
33 clocks = <&clkc 3>;
64 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
107 clocks = <&clkc 12>;
113 clocks = <&clkc 19>, <&clkc 36>;
125 clocks = <&clkc 20>, <&clkc 37>
302 clkc: clkc@100 { label in label:amba.slcr
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/ |
| meson-gxbb.dtsi | 10 #include <dt-bindings/clock/gxbb-clkc.h>
23 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
33 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
42 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
54 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
66 clocks = <&clkc CLKID_AIU_GLUE>,
67 <&clkc CLKID_I2S_OUT>,
68 <&clkc CLKID_AOCLK_GATE>
321 clkc: clock-controller { label
[all...] |
| meson-gxl.dtsi | 8 #include <dt-bindings/clock/gxbb-clkc.h>
25 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
38 clocks = <&clkc CLKID_USB1>;
62 clocks = <&clkc CLKID_ACODEC>;
73 clocks = <&clkc CLKID_BLKMV>;
82 clocks = <&clkc CLKID_AIU_GLUE>,
83 <&clkc CLKID_I2S_OUT>,
84 <&clkc CLKID_AOCLK_GATE>,
85 <&clkc CLKID_CTS_AMCLK>
333 clkc: clock-controller { label
[all...] |
| meson-axg.dtsi | 7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h>
117 clocks = <&clkc CLKID_EFUSE>;
191 clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>;
217 clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>;
235 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>
1217 clkc: clock-controller { label in label:hiubus.sysctrl
[all...] |
| meson-g12-common.dtsi | 8 #include <dt-bindings/clock/g12a-clkc.h>
35 clocks = <&clkc CLKID_HDMI>,
36 <&clkc CLKID_HTX_PCLK>,
37 <&clkc CLKID_VPU_INTR>;
45 clocks = <&clkc CLKID_HDMI>,
46 <&clkc CLKID_HTX_PCLK>,
47 <&clkc CLKID_VPU_INTR>;
54 clocks = <&clkc CLKID_EFUSE>;
146 clocks = <&clkc CLKID_PCIE_PHY
147 &clkc CLKID_PCIE_COM
1640 clkc: clock-controller { label in label:hiu.hhi
[all...] |
| /src/sys/arch/arm/amlogic/ |
| meson_sdhc.c | 364 const u_int clkc = SDHC_READ(sc, SD_CLKC_REG); local in function:meson_sdhc_default_rx_phase
365 const u_int clk_div = __SHIFTOUT(clkc, SD_CLKC_CLK_DIV);
390 uint32_t clkc; local in function:meson_sdhc_set_clock
394 clkc = SDHC_READ(sc, SD_CLKC_REG);
395 clkc &= ~SD_CLKC_TX_CLK_ENABLE;
396 clkc &= ~SD_CLKC_RX_CLK_ENABLE;
397 clkc &= ~SD_CLKC_SD_CLK_ENABLE;
398 SDHC_WRITE(sc, SD_CLKC_REG, clkc);
399 clkc &= ~SD_CLKC_MOD_CLK_ENABLE;
400 SDHC_WRITE(sc, SD_CLKC_REG, clkc);
925 const uint32_t clkc = SDHC_READ(sc, SD_CLKC_REG); local in function:meson_sdhc_execute_tuning
[all...] |
