1 /* $NetBSD: am3_prcm.c,v 1.14 2021/01/27 03:10:20 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: am3_prcm.c,v 1.14 2021/01/27 03:10:20 thorpej Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #define TI_PRCM_PRIVATE 41 #include <arm/ti/ti_prcm.h> 42 43 #define AM3_PRCM_CM_PER 0x0000 44 #define AM3_PRCM_CM_WKUP 0x0400 45 #define AM3_PRCM_CM_DPLL 0x0500 46 #define AM3_PRCM_CM_MPU 0x0600 47 #define AM3_PRCM_CM_DEVICE 0x0700 48 #define AM3_PRCM_CM_RTC 0x0800 49 #define AM3_PRCM_CM_GFX 0x0900 50 #define AM3_PRCM_CM_CEFUSE 0x0a00 51 52 #define AM3_PRCM_CLKCTRL_MODULEMODE __BITS(1,0) 53 #define AM3_PRCM_CLKCTRL_MODULEMODE_ENABLE 0x2 54 55 #define AM3_PRCM_CM_IDLEST_DPLL_DISP (AM3_PRCM_CM_WKUP + 0x48) 56 #define AM3_PRCM_CM_IDLEST_DPLL_DISP_ST_MN_BYPASS __BIT(8) 57 #define AM3_PRCM_CM_IDLEST_DPLL_DISP_ST_DPLL_CLK __BIT(0) 58 #define AM3_PRCM_CM_CLKSEL_DPLL_DISP (AM3_PRCM_CM_WKUP + 0x54) 59 #define AM3_PRCM_CM_CLKSEL_DPLL_DISP_DPLL_MULT __BITS(18,8) 60 #define AM3_PRCM_CM_CLKSEL_DPLL_DISP_DPLL_DIV __BITS(6,0) 61 #define AM3_PRCM_CM_CLKMODE_DPLL_DISP (AM3_PRCM_CM_WKUP + 0x98) 62 #define AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN __BITS(2,0) 63 #define AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN_MN_BYPASS 4 64 #define AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN_LOCK 7 65 66 #define DPLL_DISP_RATE 297000000 67 68 struct am3_prcm_softc { 69 struct ti_prcm_softc sc_prcm; /* must be first */ 70 bus_addr_t sc_regbase; 71 }; 72 73 static int am3_prcm_match(device_t, cfdata_t, void *); 74 static void am3_prcm_attach(device_t, device_t, void *); 75 76 static int 77 am3_prcm_hwmod_enable(struct ti_prcm_softc *sc, struct ti_prcm_clk *tc, int enable) 78 { 79 uint32_t val; 80 81 val = PRCM_READ(sc, tc->u.hwmod.reg); 82 val &= ~AM3_PRCM_CLKCTRL_MODULEMODE; 83 if (enable) 84 val |= __SHIFTIN(AM3_PRCM_CLKCTRL_MODULEMODE_ENABLE, 85 AM3_PRCM_CLKCTRL_MODULEMODE); 86 PRCM_WRITE(sc, tc->u.hwmod.reg, val); 87 88 return 0; 89 } 90 91 static int 92 am3_prcm_hwmod_enable_display(struct ti_prcm_softc *sc, struct ti_prcm_clk *tc, int enable) 93 { 94 uint32_t val; 95 int retry; 96 97 if (enable) { 98 /* Put the DPLL in MN bypass mode */ 99 PRCM_WRITE(sc, AM3_PRCM_CM_CLKMODE_DPLL_DISP, 100 __SHIFTIN(AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN_MN_BYPASS, 101 AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN)); 102 for (retry = 10000; retry > 0; retry--) { 103 val = PRCM_READ(sc, AM3_PRCM_CM_IDLEST_DPLL_DISP); 104 if ((val & AM3_PRCM_CM_IDLEST_DPLL_DISP_ST_MN_BYPASS) != 0) 105 break; 106 delay(10); 107 } 108 109 /* Set DPLL frequency to DPLL_DISP_RATE (297 MHz) */ 110 val = __SHIFTIN(DPLL_DISP_RATE / 1000000, AM3_PRCM_CM_CLKSEL_DPLL_DISP_DPLL_MULT); 111 val |= __SHIFTIN(24 - 1, AM3_PRCM_CM_CLKSEL_DPLL_DISP_DPLL_DIV); 112 PRCM_WRITE(sc, AM3_PRCM_CM_CLKSEL_DPLL_DISP, val); 113 114 /* Disable MN bypass mode */ 115 PRCM_WRITE(sc, AM3_PRCM_CM_CLKMODE_DPLL_DISP, 116 __SHIFTIN(AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN_LOCK, 117 AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN)); 118 for (retry = 10000; retry > 0; retry--) { 119 val = PRCM_READ(sc, AM3_PRCM_CM_IDLEST_DPLL_DISP); 120 if ((val & AM3_PRCM_CM_IDLEST_DPLL_DISP_ST_DPLL_CLK) != 0) 121 break; 122 delay(10); 123 } 124 } 125 126 return am3_prcm_hwmod_enable(sc, tc, enable); 127 } 128 129 #define AM3_PRCM_HWMOD_PER(_name, _reg, _parent) \ 130 TI_PRCM_HWMOD((_name), AM3_PRCM_CM_PER + (_reg), (_parent), am3_prcm_hwmod_enable) 131 #define AM3_PRCM_HWMOD_PER_DISP(_name, _reg, _parent) \ 132 TI_PRCM_HWMOD((_name), AM3_PRCM_CM_PER + (_reg), (_parent), am3_prcm_hwmod_enable_display) 133 #define AM3_PRCM_HWMOD_WKUP(_name, _reg, _parent) \ 134 TI_PRCM_HWMOD((_name), AM3_PRCM_CM_WKUP + (_reg), (_parent), am3_prcm_hwmod_enable) 135 136 static const struct device_compatible_entry compat_data[] = { 137 { .compat = "ti,am3-prcm" }, 138 DEVICE_COMPAT_EOL 139 }; 140 141 static const struct device_compatible_entry cm_compat_data[] = { 142 { .compat = "ti,omap4-cm" }, 143 DEVICE_COMPAT_EOL 144 }; 145 146 static const struct device_compatible_entry clkctrl_compat_data[] = { 147 { .compat = "ti,clkctrl" }, 148 DEVICE_COMPAT_EOL 149 }; 150 151 CFATTACH_DECL_NEW(am3_prcm, sizeof(struct am3_prcm_softc), 152 am3_prcm_match, am3_prcm_attach, NULL, NULL); 153 154 static struct ti_prcm_clk am3_prcm_clks[] = { 155 /* XXX until we get a proper clock tree */ 156 TI_PRCM_FIXED("FIXED_32K", 32768), 157 TI_PRCM_FIXED("FIXED_24MHZ", 24000000), 158 TI_PRCM_FIXED("FIXED_48MHZ", 48000000), 159 TI_PRCM_FIXED("FIXED_96MHZ", 96000000), 160 TI_PRCM_FIXED("DISPLAY_CLK", DPLL_DISP_RATE), 161 TI_PRCM_FIXED_FACTOR("PERIPH_CLK", 1, 1, "FIXED_48MHZ"), 162 TI_PRCM_FIXED_FACTOR("MMC_CLK", 1, 1, "FIXED_96MHZ"), 163 164 AM3_PRCM_HWMOD_WKUP("uart0", 0xb4, "PERIPH_CLK"), 165 AM3_PRCM_HWMOD_PER("uart1", 0x6c, "PERIPH_CLK"), 166 AM3_PRCM_HWMOD_PER("uart2", 0x70, "PERIPH_CLK"), 167 AM3_PRCM_HWMOD_PER("uart3", 0x74, "PERIPH_CLK"), 168 AM3_PRCM_HWMOD_PER("uart4", 0x78, "PERIPH_CLK"), 169 AM3_PRCM_HWMOD_PER("uart5", 0x38, "PERIPH_CLK"), 170 171 AM3_PRCM_HWMOD_WKUP("i2c1", 0xb8, "PERIPH_CLK"), 172 AM3_PRCM_HWMOD_PER("i2c2", 0x48, "PERIPH_CLK"), 173 AM3_PRCM_HWMOD_PER("i2c3", 0x44, "PERIPH_CLK"), 174 175 AM3_PRCM_HWMOD_WKUP("gpio1", 0x8, "PERIPH_CLK"), 176 AM3_PRCM_HWMOD_PER("gpio2", 0xac, "PERIPH_CLK"), 177 AM3_PRCM_HWMOD_PER("gpio3", 0xb0, "PERIPH_CLK"), 178 AM3_PRCM_HWMOD_PER("gpio4", 0xb4, "PERIPH_CLK"), 179 180 AM3_PRCM_HWMOD_WKUP("timer1", 0x10, "FIXED_32K"), 181 AM3_PRCM_HWMOD_PER("timer2", 0x80, "FIXED_24MHZ"), 182 AM3_PRCM_HWMOD_PER("timer3", 0x84, "FIXED_24MHZ"), 183 AM3_PRCM_HWMOD_PER("timer4", 0x88, "FIXED_24MHZ"), 184 AM3_PRCM_HWMOD_PER("timer5", 0xec, "FIXED_24MHZ"), 185 AM3_PRCM_HWMOD_PER("timer6", 0xf0, "FIXED_24MHZ"), 186 AM3_PRCM_HWMOD_PER("timer7", 0x7c, "FIXED_24MHZ"), 187 188 AM3_PRCM_HWMOD_WKUP("wd_timer2", 0xd4, "FIXED_32K"), 189 190 AM3_PRCM_HWMOD_PER("mmc1", 0x3c, "MMC_CLK"), 191 AM3_PRCM_HWMOD_PER("mmc2", 0xf4, "MMC_CLK"), 192 AM3_PRCM_HWMOD_PER("mmc3", 0xf8, "MMC_CLK"), 193 194 AM3_PRCM_HWMOD_PER("tpcc", 0xbc, "PERIPH_CLK"), 195 AM3_PRCM_HWMOD_PER("tptc0", 0x24, "PERIPH_CLK"), 196 AM3_PRCM_HWMOD_PER("tptc1", 0xfc, "PERIPH_CLK"), 197 AM3_PRCM_HWMOD_PER("tptc2", 0x100, "PERIPH_CLK"), 198 199 AM3_PRCM_HWMOD_PER("usb_otg_hs", 0x1c, "PERIPH_CLK"), 200 201 AM3_PRCM_HWMOD_PER("rng", 0x90, "PERIPH_CLK"), 202 203 AM3_PRCM_HWMOD_PER_DISP("lcdc", 0x18, "DISPLAY_CLK"), 204 }; 205 206 static struct clk * 207 am3_prcm_clock_decode(device_t dev, int cc_phandle, const void *data, size_t len) 208 { 209 struct am3_prcm_softc * const sc = device_private(dev); 210 const u_int *cells = data; 211 bus_addr_t regbase; 212 u_int n; 213 214 if (len != 8) 215 return NULL; 216 217 bus_size_t regoff = be32toh(cells[0]); 218 const u_int clock_index = be32toh(cells[1]); 219 220 /* XXX not sure how to handle this yet */ 221 if (clock_index != 0) 222 return NULL; 223 224 /* 225 * Register offset in specifier is relative to base address of the 226 * clock node. Translate this to an address relative to the start 227 * of PRCM space. 228 */ 229 if (fdtbus_get_reg(cc_phandle, 0, ®base, NULL) != 0) 230 return NULL; 231 regoff += (regbase - sc->sc_regbase); 232 233 /* 234 * Look for a matching hwmod. 235 */ 236 for (n = 0; n < sc->sc_prcm.sc_nclks; n++) { 237 struct ti_prcm_clk *tclk = &sc->sc_prcm.sc_clks[n]; 238 if (tclk->type != TI_PRCM_HWMOD) 239 continue; 240 241 if (tclk->u.hwmod.reg == regoff) 242 return &tclk->base; 243 } 244 245 /* Not found */ 246 return NULL; 247 } 248 249 static const struct fdtbus_clock_controller_func am3_prcm_clock_fdt_funcs = { 250 .decode = am3_prcm_clock_decode 251 }; 252 253 static int 254 am3_prcm_match(device_t parent, cfdata_t cf, void *aux) 255 { 256 struct fdt_attach_args * const faa = aux; 257 258 return of_compatible_match(faa->faa_phandle, compat_data); 259 } 260 261 static void 262 am3_prcm_attach(device_t parent, device_t self, void *aux) 263 { 264 struct am3_prcm_softc * const sc = device_private(self); 265 struct fdt_attach_args * const faa = aux; 266 const int phandle = faa->faa_phandle; 267 int clocks, child, cm_child; 268 269 if (fdtbus_get_reg(phandle, 0, &sc->sc_regbase, NULL) != 0) { 270 aprint_error(": couldn't get registers\n"); 271 return; 272 } 273 274 sc->sc_prcm.sc_dev = self; 275 sc->sc_prcm.sc_phandle = phandle; 276 sc->sc_prcm.sc_bst = faa->faa_bst; 277 sc->sc_prcm.sc_clks = am3_prcm_clks; 278 sc->sc_prcm.sc_nclks = __arraycount(am3_prcm_clks); 279 280 if (ti_prcm_attach(&sc->sc_prcm) != 0) 281 return; 282 283 aprint_naive("\n"); 284 aprint_normal(": AM3xxx PRCM\n"); 285 286 for (child = OF_child(phandle); child; child = OF_peer(child)) { 287 if (of_compatible_match(child, cm_compat_data) == 0) 288 continue; 289 290 for (cm_child = OF_child(child); cm_child; 291 cm_child = OF_peer(cm_child)) { 292 if (of_compatible_match(cm_child, 293 clkctrl_compat_data) == 0) 294 continue; 295 296 aprint_debug_dev(self, "clkctrl: %s\n", fdtbus_get_string(cm_child, "name")); 297 fdtbus_register_clock_controller(self, cm_child, 298 &am3_prcm_clock_fdt_funcs); 299 } 300 } 301 302 clocks = of_find_firstchild_byname(phandle, "clocks"); 303 if (clocks > 0) 304 fdt_add_bus(self, clocks, faa); 305 } 306
Indexes created Fri Sep 26 08:10:20 GMT 2025