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/src/sys/arch/arm/nvidia/ | |
tegra_clock.h | 70 u_int clr_reg; member in struct:tegra_gate_clk |
tegra124_car.c | 350 .clr_reg = (_clr), \ 673 u_int clr_reg; member in struct:tegra124_car_rst 679 u_int clr_reg; member in struct:tegra124_car_reset_reg 1372 if (tgate->set_reg == tgate->clr_reg) { 1384 reg = tgate->clr_reg; 1546 rst->clr_reg = tegra124_car_reset_regs[reg].clr_reg; 1577 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask); |
tegra210_car.c | 362 .clr_reg = (_clr), \ 687 u_int clr_reg; member in struct:tegra210_car_rst 693 u_int clr_reg; member in struct:tegra210_car_reset_reg 1470 if (tgate->set_reg == tgate->clr_reg) { 1482 reg = tgate->clr_reg; 1636 rst->clr_reg = tegra210_car_reset_regs[reg].clr_reg; 1667 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask); |
/src/sys/arch/arm/apple/ | |
apple_intc.c | 307 bus_size_t clr_reg; local in function:apple_intc_irq_handler 329 clr_reg = AIC_MASK_CLR(evdata); 339 clr_reg = 0; 354 AIC_WRITE(sc, clr_reg, clr_val); |