1 /* $NetBSD: cmdide.c,v 1.47 2021/12/26 16:08:21 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: cmdide.c,v 1.47 2021/12/26 16:08:21 andvar Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/atomic.h> 33 34 #include <dev/pci/pcivar.h> 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pciidereg.h> 37 #include <dev/pci/pciidevar.h> 38 #include <dev/pci/pciide_cmd_reg.h> 39 40 #define CMDIDE_ACT_CHANNEL_NONE 0xff 41 42 static int cmdide_match(device_t, cfdata_t, void *); 43 static void cmdide_attach(device_t, device_t, void *); 44 45 CFATTACH_DECL_NEW(cmdide, sizeof(struct pciide_softc), 46 cmdide_match, cmdide_attach, pciide_detach, NULL); 47 48 static void cmd_chip_map(struct pciide_softc*, const struct pci_attach_args*); 49 static void cmd0643_9_chip_map(struct pciide_softc*, 50 const struct pci_attach_args*); 51 static void cmd0643_9_setup_channel(struct ata_channel*); 52 static void cmd_channel_map(const struct pci_attach_args *, 53 struct pciide_softc *, int); 54 static int cmd064x_claim_hw(struct ata_channel *, int); 55 static void cmd064x_free_hw(struct ata_channel *); 56 static int cmd_pci_intr(void *); 57 static void cmd646_9_irqack(struct ata_channel *); 58 static void cmd680_chip_map(struct pciide_softc*, 59 const struct pci_attach_args*); 60 static void cmd680_setup_channel(struct ata_channel*); 61 static void cmd680_channel_map(const struct pci_attach_args *, 62 struct pciide_softc *, int); 63 64 /* Older CMD64X doesn't have independent channels */ 65 static const struct pciide_product_desc pciide_cmd_products[] = { 66 { PCI_PRODUCT_CMDTECH_640, 67 IDE_SHARED_CHANNELS, 68 "CMD Technology PCI0640", 69 cmd_chip_map 70 }, 71 { PCI_PRODUCT_CMDTECH_643, 72 IDE_SHARED_CHANNELS, 73 "CMD Technology PCI0643", 74 cmd0643_9_chip_map, 75 }, 76 { PCI_PRODUCT_CMDTECH_646, 77 IDE_SHARED_CHANNELS, 78 "CMD Technology PCI0646", 79 cmd0643_9_chip_map, 80 }, 81 { PCI_PRODUCT_CMDTECH_648, 82 IDE_SHARED_CHANNELS, 83 "CMD Technology PCI0648", 84 cmd0643_9_chip_map, 85 }, 86 { PCI_PRODUCT_CMDTECH_649, 87 0, 88 "CMD Technology PCI0649", 89 cmd0643_9_chip_map, 90 }, 91 { PCI_PRODUCT_CMDTECH_680, 92 0, 93 "Silicon Image 0680", 94 cmd680_chip_map, 95 }, 96 { 0, 97 0, 98 NULL, 99 NULL 100 } 101 }; 102 103 static int 104 cmdide_match(device_t parent, cfdata_t match, void *aux) 105 { 106 struct pci_attach_args *pa = aux; 107 108 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 109 if (pciide_lookup_product(pa->pa_id, pciide_cmd_products)) 110 return (2); 111 } 112 return (0); 113 } 114 115 static void 116 cmdide_attach(device_t parent, device_t self, void *aux) 117 { 118 struct pci_attach_args *pa = aux; 119 struct pciide_softc *sc = device_private(self); 120 121 sc->sc_wdcdev.sc_atac.atac_dev = self; 122 123 pciide_common_attach(sc, pa, 124 pciide_lookup_product(pa->pa_id, pciide_cmd_products)); 125 126 } 127 128 static void 129 cmd_channel_map(const struct pci_attach_args *pa, struct pciide_softc *sc, 130 int channel) 131 { 132 struct pciide_channel *cp = &sc->pciide_channels[channel]; 133 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 134 int interface; 135 bool one_channel = ISSET(sc->sc_pp->ide_flags, IDE_SHARED_CHANNELS); 136 137 /* 138 * The 0648/0649 can be told to identify as a RAID controller. 139 * In this case, we have to fake interface 140 */ 141 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 142 interface = PCIIDE_INTERFACE_SETTABLE(0) | 143 PCIIDE_INTERFACE_SETTABLE(1); 144 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 145 CMD_CONF_DSA1) 146 interface |= PCIIDE_INTERFACE_PCI(0) | 147 PCIIDE_INTERFACE_PCI(1); 148 } else { 149 interface = PCI_INTERFACE(pa->pa_class); 150 } 151 152 sc->wdc_chanarray[channel] = &cp->ata_channel; 153 cp->name = PCIIDE_CHANNEL_NAME(channel); 154 cp->ata_channel.ch_channel = channel; 155 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 156 157 if (channel > 0 && one_channel) { 158 /* Channels are not independent, need synchronization */ 159 sc->sc_wdcdev.sc_atac.atac_claim_hw = cmd064x_claim_hw; 160 sc->sc_wdcdev.sc_atac.atac_free_hw = cmd064x_free_hw; 161 sc->sc_cmd_act_channel = CMDIDE_ACT_CHANNEL_NONE; 162 } 163 164 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 165 "%s channel %s to %s mode%s\n", cp->name, 166 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 167 "configured" : "wired", 168 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 169 "native-PCI" : "compatibility", 170 one_channel ? ", channel non-independent" : ""); 171 172 /* 173 * with a CMD PCI64x, if we get here, the first channel is enabled: 174 * there's no way to disable the first channel without disabling 175 * the whole device 176 */ 177 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 178 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 179 "%s channel ignored (disabled)\n", cp->name); 180 cp->ata_channel.ch_flags |= ATACH_DISABLED; 181 return; 182 } 183 184 pciide_mapchan(pa, cp, interface, cmd_pci_intr); 185 } 186 187 /* 188 * Check if we can execute next xfer on the channel. 189 * Called with chp channel lock held. 190 */ 191 static int 192 cmd064x_claim_hw(struct ata_channel *chp, int maysleep) 193 { 194 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 195 196 return atomic_cas_uint(&sc->sc_cmd_act_channel, 197 CMDIDE_ACT_CHANNEL_NONE, chp->ch_channel) 198 == CMDIDE_ACT_CHANNEL_NONE; 199 } 200 201 /* Allow another channel to run. Called with ochp channel lock held. */ 202 static void 203 cmd064x_free_hw(struct ata_channel *ochp) 204 { 205 struct pciide_softc *sc = CHAN_TO_PCIIDE(ochp); 206 uint oact = atomic_cas_uint(&sc->sc_cmd_act_channel, 207 ochp->ch_channel, CMDIDE_ACT_CHANNEL_NONE); 208 struct ata_channel *nchp; 209 210 KASSERT(oact == ochp->ch_channel); 211 212 /* Start the other channel(s) */ 213 for(uint i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 214 /* Skip the current channel */ 215 if (i == oact) 216 continue; 217 218 nchp = &sc->pciide_channels[i].ata_channel; 219 if (nchp->ch_ndrives == 0) 220 continue; 221 222 atastart(nchp); 223 } 224 } 225 226 static int 227 cmd_pci_intr(void *arg) 228 { 229 struct pciide_softc *sc = arg; 230 struct pciide_channel *cp; 231 struct ata_channel *wdc_cp; 232 int i, rv, crv; 233 u_int32_t priirq, secirq; 234 235 rv = 0; 236 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 237 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 238 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 239 cp = &sc->pciide_channels[i]; 240 wdc_cp = &cp->ata_channel; 241 /* If a compat channel skip. */ 242 if (cp->compat) 243 continue; 244 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 245 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 246 crv = wdcintr(wdc_cp); 247 if (crv == 0) { 248 aprint_verbose("%s:%d: bogus intr\n", 249 device_xname( 250 sc->sc_wdcdev.sc_atac.atac_dev), i); 251 } else 252 rv = 1; 253 } 254 } 255 return rv; 256 } 257 258 static void 259 cmd_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 260 { 261 int channel; 262 263 /* 264 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 265 * and base addresses registers can be disabled at 266 * hardware level. In this case, the device is wired 267 * in compat mode and its first channel is always enabled, 268 * but we can't rely on PCI_COMMAND_IO_ENABLE. 269 * In fact, it seems that the first channel of the CMD PCI0640 270 * can't be disabled. 271 */ 272 273 #ifdef PCIIDE_CMD064x_DISABLE 274 if (pciide_chipen(sc, pa) == 0) 275 return; 276 #endif 277 278 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 279 "hardware does not support DMA\n"); 280 sc->sc_dma_ok = 0; 281 282 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 283 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 284 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 285 sc->sc_wdcdev.wdc_maxdrives = 2; 286 287 wdc_allocate_regs(&sc->sc_wdcdev); 288 289 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 290 channel++) { 291 cmd_channel_map(pa, sc, channel); 292 } 293 } 294 295 static void 296 cmd0643_9_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 297 { 298 int channel; 299 pcireg_t rev = PCI_REVISION(pa->pa_class); 300 301 /* 302 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 303 * and base addresses registers can be disabled at 304 * hardware level. In this case, the device is wired 305 * in compat mode and its first channel is always enabled, 306 * but we can't rely on PCI_COMMAND_IO_ENABLE. 307 * In fact, it seems that the first channel of the CMD PCI0640 308 * can't be disabled. 309 */ 310 311 #ifdef PCIIDE_CMD064x_DISABLE 312 if (pciide_chipen(sc, pa) == 0) 313 return; 314 #endif 315 316 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 317 "bus-master DMA support present"); 318 pciide_mapreg_dma(sc, pa); 319 aprint_verbose("\n"); 320 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 321 if (sc->sc_dma_ok) { 322 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 323 switch (sc->sc_pp->ide_product) { 324 case PCI_PRODUCT_CMDTECH_649: 325 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 326 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 327 sc->sc_wdcdev.irqack = cmd646_9_irqack; 328 break; 329 case PCI_PRODUCT_CMDTECH_648: 330 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 331 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 332 sc->sc_wdcdev.irqack = cmd646_9_irqack; 333 break; 334 case PCI_PRODUCT_CMDTECH_646: 335 if (rev >= CMD0646U2_REV) { 336 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 337 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 338 } else if (rev >= CMD0646U_REV) { 339 /* 340 * Linux's driver claims that the 646U is broken 341 * with UDMA. Only enable it if we know what we're 342 * doing 343 */ 344 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 345 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 346 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 347 #endif 348 /* explicitly disable UDMA */ 349 pciide_pci_write(sc->sc_pc, sc->sc_tag, 350 CMD_UDMATIM(0), 0); 351 pciide_pci_write(sc->sc_pc, sc->sc_tag, 352 CMD_UDMATIM(1), 0); 353 } 354 sc->sc_wdcdev.irqack = cmd646_9_irqack; 355 break; 356 default: 357 sc->sc_wdcdev.irqack = pciide_irqack; 358 } 359 } 360 361 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 362 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 363 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 364 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 365 sc->sc_wdcdev.sc_atac.atac_set_modes = cmd0643_9_setup_channel; 366 sc->sc_wdcdev.wdc_maxdrives = 2; 367 368 ATADEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 369 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 370 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 371 DEBUG_PROBE); 372 373 wdc_allocate_regs(&sc->sc_wdcdev); 374 375 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 376 channel++) 377 cmd_channel_map(pa, sc, channel); 378 379 /* 380 * note - this also makes sure we clear the irq disable and reset 381 * bits 382 */ 383 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 384 ATADEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 385 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 386 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 387 DEBUG_PROBE); 388 } 389 390 static void 391 cmd0643_9_setup_channel(struct ata_channel *chp) 392 { 393 struct ata_drive_datas *drvp; 394 u_int8_t tim; 395 u_int32_t idedma_ctl, udma_reg; 396 int drive, s; 397 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 398 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 399 400 idedma_ctl = 0; 401 /* setup DMA if needed */ 402 pciide_channel_dma_setup(cp); 403 404 for (drive = 0; drive < 2; drive++) { 405 drvp = &chp->ch_drive[drive]; 406 /* If no drive, skip */ 407 if (drvp->drive_type == ATA_DRIVET_NONE) 408 continue; 409 /* add timing values, setup DMA if needed */ 410 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 411 if (drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) { 412 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 413 /* UltraDMA on a 646U2, 0648 or 0649 */ 414 s = splbio(); 415 drvp->drive_flags &= ~ATA_DRIVE_DMA; 416 splx(s); 417 udma_reg = pciide_pci_read(sc->sc_pc, 418 sc->sc_tag, CMD_UDMATIM(chp->ch_channel)); 419 if (drvp->UDMA_mode > 2 && 420 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 421 CMD_BICSR) & 422 CMD_BICSR_80(chp->ch_channel)) == 0) 423 drvp->UDMA_mode = 2; 424 if (drvp->UDMA_mode > 2) 425 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 426 else if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 2) 427 udma_reg |= CMD_UDMATIM_UDMA33(drive); 428 udma_reg |= CMD_UDMATIM_UDMA(drive); 429 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 430 CMD_UDMATIM_TIM_OFF(drive)); 431 udma_reg |= 432 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 433 CMD_UDMATIM_TIM_OFF(drive)); 434 pciide_pci_write(sc->sc_pc, sc->sc_tag, 435 CMD_UDMATIM(chp->ch_channel), udma_reg); 436 } else { 437 /* 438 * use Multiword DMA. 439 * Timings will be used for both PIO and DMA, 440 * so adjust DMA mode if needed 441 * if we have a 0646U2/8/9, turn off UDMA 442 */ 443 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 444 udma_reg = pciide_pci_read(sc->sc_pc, 445 sc->sc_tag, 446 CMD_UDMATIM(chp->ch_channel)); 447 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 448 pciide_pci_write(sc->sc_pc, sc->sc_tag, 449 CMD_UDMATIM(chp->ch_channel), 450 udma_reg); 451 } 452 if (drvp->PIO_mode >= 3 && 453 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 454 drvp->DMA_mode = drvp->PIO_mode - 2; 455 } 456 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 457 } 458 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 459 } 460 pciide_pci_write(sc->sc_pc, sc->sc_tag, 461 CMD_DATA_TIM(chp->ch_channel, drive), tim); 462 } 463 if (idedma_ctl != 0) { 464 /* Add software bits in status register */ 465 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 466 idedma_ctl); 467 } 468 } 469 470 static void 471 cmd646_9_irqack(struct ata_channel *chp) 472 { 473 u_int32_t priirq, secirq; 474 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 475 476 if (chp->ch_channel == 0) { 477 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 478 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 479 } else { 480 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 481 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 482 } 483 pciide_irqack(chp); 484 } 485 486 static void 487 cmd680_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 488 { 489 int channel; 490 491 if (pciide_chipen(sc, pa) == 0) 492 return; 493 494 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 495 "bus-master DMA support present"); 496 pciide_mapreg_dma(sc, pa); 497 aprint_verbose("\n"); 498 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 499 if (sc->sc_dma_ok) { 500 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 501 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 502 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 503 sc->sc_wdcdev.irqack = pciide_irqack; 504 } 505 506 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 507 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 508 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 509 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 510 sc->sc_wdcdev.sc_atac.atac_set_modes = cmd680_setup_channel; 511 sc->sc_wdcdev.wdc_maxdrives = 2; 512 513 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 514 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 515 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 516 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 517 518 wdc_allocate_regs(&sc->sc_wdcdev); 519 520 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 521 channel++) 522 cmd680_channel_map(pa, sc, channel); 523 } 524 525 static void 526 cmd680_channel_map(const struct pci_attach_args *pa, struct pciide_softc *sc, 527 int channel) 528 { 529 struct pciide_channel *cp = &sc->pciide_channels[channel]; 530 int interface, i, reg; 531 static const u_int8_t init_val[] = 532 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 533 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 534 535 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 536 interface = PCIIDE_INTERFACE_SETTABLE(0) | 537 PCIIDE_INTERFACE_SETTABLE(1); 538 interface |= PCIIDE_INTERFACE_PCI(0) | 539 PCIIDE_INTERFACE_PCI(1); 540 } else { 541 interface = PCI_INTERFACE(pa->pa_class); 542 } 543 544 sc->wdc_chanarray[channel] = &cp->ata_channel; 545 cp->name = PCIIDE_CHANNEL_NAME(channel); 546 cp->ata_channel.ch_channel = channel; 547 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 548 549 /* XXX */ 550 reg = 0xa2 + channel * 16; 551 for (i = 0; i < sizeof(init_val); i++) 552 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 553 554 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 555 "%s channel %s to %s mode\n", cp->name, 556 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 557 "configured" : "wired", 558 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 559 "native-PCI" : "compatibility"); 560 561 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 562 } 563 564 static void 565 cmd680_setup_channel(struct ata_channel *chp) 566 { 567 struct ata_drive_datas *drvp; 568 u_int8_t mode, off, scsc; 569 u_int16_t val; 570 u_int32_t idedma_ctl; 571 int drive, s; 572 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 573 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 574 pci_chipset_tag_t pc = sc->sc_pc; 575 pcitag_t pa = sc->sc_tag; 576 static const u_int8_t udma2_tbl[] = 577 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 578 static const u_int8_t udma_tbl[] = 579 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 580 static const u_int16_t dma_tbl[] = 581 { 0x2208, 0x10c2, 0x10c1 }; 582 static const u_int16_t pio_tbl[] = 583 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 584 585 idedma_ctl = 0; 586 pciide_channel_dma_setup(cp); 587 mode = pciide_pci_read(pc, pa, 0x80 + chp->ch_channel * 4); 588 589 for (drive = 0; drive < 2; drive++) { 590 drvp = &chp->ch_drive[drive]; 591 /* If no drive, skip */ 592 if (drvp->drive_type == ATA_DRIVET_NONE) 593 continue; 594 mode &= ~(0x03 << (drive * 4)); 595 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 596 s = splbio(); 597 drvp->drive_flags &= ~ATA_DRIVE_DMA; 598 splx(s); 599 off = 0xa0 + chp->ch_channel * 16; 600 if (drvp->UDMA_mode > 2 && 601 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 602 drvp->UDMA_mode = 2; 603 scsc = pciide_pci_read(pc, pa, 0x8a); 604 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 605 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 606 scsc = pciide_pci_read(pc, pa, 0x8a); 607 if ((scsc & 0x30) == 0) 608 drvp->UDMA_mode = 5; 609 } 610 mode |= 0x03 << (drive * 4); 611 off = 0xac + chp->ch_channel * 16 + drive * 2; 612 val = pciide_pci_read(pc, pa, off) & ~0x3f; 613 if (scsc & 0x30) 614 val |= udma2_tbl[drvp->UDMA_mode]; 615 else 616 val |= udma_tbl[drvp->UDMA_mode]; 617 pciide_pci_write(pc, pa, off, val); 618 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 619 } else if (drvp->drive_flags & ATA_DRIVE_DMA) { 620 mode |= 0x02 << (drive * 4); 621 off = 0xa8 + chp->ch_channel * 16 + drive * 2; 622 val = dma_tbl[drvp->DMA_mode]; 623 pciide_pci_write(pc, pa, off, val & 0xff); 624 pciide_pci_write(pc, pa, off+1, val >> 8); 625 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 626 } else { 627 mode |= 0x01 << (drive * 4); 628 off = 0xa4 + chp->ch_channel * 16 + drive * 2; 629 val = pio_tbl[drvp->PIO_mode]; 630 pciide_pci_write(pc, pa, off, val & 0xff); 631 pciide_pci_write(pc, pa, off+1, val >> 8); 632 } 633 } 634 635 pciide_pci_write(pc, pa, 0x80 + chp->ch_channel * 4, mode); 636 if (idedma_ctl != 0) { 637 /* Add software bits in status register */ 638 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 639 idedma_ctl); 640 } 641 } 642
Indexes created Mon Sep 22 13:09:51 GMT 2025