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    Searched defs:cntl0 (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/arch/arm/amlogic/
meson8b_clkc.c 122 uint32_t cntl0 = CLK_READ(sc, HHI_SYS_CPU_CLK_CNTL0); local in function:meson8b_clkc_pll_sys_set_rate
137 if ((cntl0 & HHI_SYS_CPU_CLK_CNTL0_CLKSEL) == 0) {
141 if (__SHIFTOUT(cntl0, HHI_SYS_CPU_CLK_CNTL0_PLLSEL) != 1) {
145 if (__SHIFTOUT(cntl0, HHI_SYS_CPU_CLK_CNTL0_SOUTSEL) != 0) {
158 cntl0 &= ~HHI_SYS_CPU_CLK_CNTL0_CLKSEL;
159 CLK_WRITE(sc, HHI_SYS_CPU_CLK_CNTL0, cntl0);
168 cntl0 |= HHI_SYS_CPU_CLK_CNTL0_CLKSEL;
169 CLK_WRITE(sc, HHI_SYS_CPU_CLK_CNTL0, cntl0);
mesong12_clkc.c 1422 uint32_t cntl0, cntl4, cntl3, cntl5; local in function:mesong12_clk_pcie_pll_set_rate
1424 cntl0 = __SHIFTIN(9, HHI_PCIE_PLL_CNTL0_PCIE_APLL_OD) |
1442 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL0, cntl0 |
1444 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL0, cntl0 |
1460 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL0, cntl0 |
1464 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL0, cntl0 |

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