| /src/external/mpl/bind/dist/doc/arm/_ext/ |
| mergegrammar.py | 47 def combine(): function
62 full_grammar = combine()
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsPreLegalizerCombiner.cpp | 33 virtual bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
37 bool MipsPreLegalizerCombinerInfo::combine(GISelChangeObserver &Observer, function in class:__anon4995::MipsPreLegalizerCombinerInfo
48 // Don't attempt to combine non power of 2 loads or unaligned loads when
106 "Combine Mips machine instrs before legalization", false,
110 "Combine Mips machine instrs before legalization", false,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64O0PreLegalizerCombiner.cpp | 69 virtual bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
73 bool AArch64O0PreLegalizerCombinerInfo::combine(GISelChangeObserver &Observer, function in class:__anon4617::AArch64O0PreLegalizerCombinerInfo
158 "Combine AArch64 machine instrs before legalization",
164 "Combine AArch64 machine instrs before legalization", false,
|
| AArch64PostLegalizerCombiner.cpp | 42 /// This combine tries do what performExtractVectorEltCombine does in SDAG.
297 virtual bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
301 bool AArch64PostLegalizerCombinerInfo::combine(GISelChangeObserver &Observer, function in class:__anon4618::AArch64PostLegalizerCombinerInfo
378 "Combine AArch64 MachineInstrs after legalization", false,
383 "Combine AArch64 MachineInstrs after legalization", false,
|
| /src/sys/arch/ia64/disasm/ |
| disasm_extract.c | 1894 combine(uint64_t *dst, int dl, uint64_t src, int sl, int so) function
2569 combine(&i->i_oper[1].o_value, 21, b->b_inst[1].i_bits, 41, 0);
2576 combine(&i->i_oper[2].o_value, 22, b->b_inst[1].i_bits, 41, 0);
2577 combine(&i->i_oper[2].o_value, 63, bits, 1, 36);
2583 combine(&i->i_oper[1].o_value, 20, b->b_inst[1].i_bits, 39, 2);
2584 combine(&i->i_oper[1].o_value, 59, bits, 1, 36);
2593 combine(&i->i_oper[2].o_value, 20, b->b_inst[1].i_bits, 39, 2);
2594 combine(&i->i_oper[2].o_value, 59, bits, 1, 36);
2601 combine(&i->i_oper[1].o_value, 21, b->b_inst[1].i_bits, 41, 0);
|
| /src/crypto/external/apache2/openssl/dist/ |
| Configure | 3094 # Helper function to combine several values of different types into one.
3095 # This is useful if you want to combine a string with the result of a
3098 # cflags => combine("-Wall", sub { $disabled{zlib} ? () : "-DZLIB" })
3100 sub combine { subroutine
3108 # cflags => combine("-Wall", threads("-pthread"))
|
| /src/crypto/external/bsd/openssl/dist/ |
| Configure | 2935 # Helper function to combine several values of different types into one.
2936 # This is useful if you want to combine a string with the result of a
2939 # cflags => combine("-Wall", sub { $disabled{zlib} ? () : "-DZLIB" })
2941 sub combine { subroutine
2949 # cflags => combine("-Wall", threads("-pthread"))
|
| /src/usr.bin/elf2aout/ |
| elf2aout.c | 67 static void combine(struct sect *, struct sect *, int);
336 combine(&data, &ndata, 0);
337 combine(&bss, &nbss, 1);
344 combine(&text, &ntxt, 0);
605 /* Combine two segments, which must be contiguous. If pad is true, it's
608 combine(struct sect *base, struct sect *new, int pad) function
|
| /src/crypto/external/bsd/heimdal/dist/lib/wind/ |
| normalize.c | 252 combine(const uint32_t *in, size_t in_len, function
324 ret = combine(tmp, tmp_len, out, out_len);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUPostLegalizerCombiner.cpp | 296 bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
300 bool AMDGPUPostLegalizerCombinerInfo::combine(GISelChangeObserver &Observer, function in class:__anon4662::AMDGPUPostLegalizerCombinerInfo
391 "Combine AMDGPU machine instrs after legalization",
396 "Combine AMDGPU machine instrs after legalization", false,
|
| AMDGPUPreLegalizerCombiner.cpp | 192 virtual bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
196 bool AMDGPUPreLegalizerCombinerInfo::combine(GISelChangeObserver &Observer, function in class:__anon4663::AMDGPUPreLegalizerCombinerInfo
287 "Combine AMDGPU machine instrs before legalization",
292 "Combine AMDGPU machine instrs before legalization", false,
|
| AMDGPURegBankCombiner.cpp | 179 bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
183 bool AMDGPURegBankCombinerInfo::combine(GISelChangeObserver &Observer, function in class:__anon4667::AMDGPURegBankCombinerInfo
264 "Combine AMDGPU machine instrs after regbankselect",
269 "Combine AMDGPU machine instrs after regbankselect", false,
|
| /src/external/mit/lua/dist/src/ |
| luac.c | 145 static const Proto* combine(lua_State* L, int n) function
183 f=combine(L,argc);
|
| /src/usr.bin/elf2ecoff/ |
| elf2ecoff.c | 85 static void combine(struct sect *, struct sect *, int);
257 combine(&data, &ndata, 0);
258 combine(&bss, &nbss, 1);
269 combine(&text, &ntxt, 0);
477 /* Combine two segments, which must be contiguous. If pad is true, it's
480 combine(struct sect *base, struct sect *new, int pad) function
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/ADT/ |
| Hashing.h | 339 /// A type trait which is true if we want to combine values for hashing by
506 /// This sets up the state for a recursive hash combine, including getting
511 /// Combine one chunk of data into the current in-flight hash.
522 // with the variadic combine because that formation can have varying
557 hash_code combine(size_t length, char *buffer_ptr, char *buffer_end, function in struct:llvm::hashing::detail::hash_combine_recursive_helper
562 return combine(length, buffer_ptr, buffer_end, args...);
570 hash_code combine(size_t length, char *buffer_ptr, char *buffer_end) { function in struct:llvm::hashing::detail::hash_combine_recursive_helper
593 /// Combine values into a single hash_code.
596 /// attempt to combine them into a single hash_code. For user-defined types it
607 return helper.combine(0, helper.buffer, helper.buffer + 64, args...)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonCopyToCombine.cpp | 1 //===------- HexagonCopyToCombine.cpp - Hexagon Copy-To-Combine Pass ------===//
8 // This pass replaces transfer instructions by combine instructions.
11 // replace them with a combine instruction.
34 #define DEBUG_TYPE "hexagon-copy-combine"
82 return "Hexagon Copy-To-Combine Pass";
98 void combine(MachineInstr &I1, MachineInstr &I2,
126 INITIALIZE_PASS(HexagonCopyToCombine, "hexagon-copy-combine",
127 "Hexagon Copy-To-Combine Pass", false, false)
153 // workaround for an ABI bug that prevents GOT relocations on combine
158 // Only combine constant extended A2_tfrsi if we are in aggressive mode
579 void HexagonCopyToCombine::combine(MachineInstr &I1, MachineInstr &I2, function in class:HexagonCopyToCombine
[all...] |
| /src/external/gpl3/gdb/dist/sim/igen/ |
| igen.h | 102 int combine; member in struct:_igen_trace_options
134 /* Combine tables? Should the generator make a second pass through
138 int combine; member in struct:_igen_decode_options
|
| /src/external/gpl3/gdb.old/dist/sim/igen/ |
| igen.h | 102 int combine; member in struct:_igen_trace_options
134 /* Combine tables? Should the generator make a second pass through
138 int combine; member in struct:_igen_decode_options
|
| /src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| CodeGenPGO.cpp | 135 void combine(HashType Type);
227 Hash.combine(Type);
242 Hash.combine(PGOHash::IfThenBranch);
244 Hash.combine(PGOHash::IfElseBranch);
247 Hash.combine(PGOHash::EndOfScope);
258 Hash.combine(PGOHash::EndOfScope); \
741 void PGOHash::combine(HashType Type) { function in class:PGOHash
742 // Check that we never combine 0 and only have six bits.
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| InterleavedLoadCombinePass.cpp | 1 //===- InterleavedLoadCombine.cpp - Combine Interleaved Loads ---*- C++ -*-===//
11 // This file defines the interleaved-load-combine pass. The pass searches for
50 #define DEBUG_TYPE "interleaved-load-combine"
99 bool combine(std::list<VectorInfo> &InterleavedLoad,
1114 bool InterleavedLoadCombineImpl::combine(std::list<VectorInfo> &InterleavedLoad, function in class:InterleavedLoadCombineImpl
1151 // There is nothing to combine.
1192 assert(!LIs.empty() && "There are no LoadInst to combine");
1290 if (combine(InterleavedLoad, ORE)) {
1317 return "Interleaved Load Combine Pass";
1352 "Combine interleaved loads into wide loads and shufflevector instructions"
[all...] |
| /src/external/gpl3/gcc/dist/libcpp/ |
| charset.cc | 993 unsigned char combine;
1419 if (ucnranges[mn].combine != 0 && ucnranges[mn].combine < nst->prev_class)
1455 if (ucnranges[mn].combine == 0)
1457 nst->prev_class = ucnranges[mn].combine;
991 unsigned char combine; member in struct:ucnrange
|
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 674 // Try to combine Idx's compose map into Vec if it is compatible.
676 static bool combine(const CodeGenSubRegIndex *Idx, function
719 if (combine(&Idx, Rows[r])) {
728 combine(&Idx, Rows.back());
|
| /src/external/gpl3/gcc.old/dist/libcpp/ |
| charset.cc | 917 unsigned char combine;
971 if (ucnranges[mn].combine != 0 && ucnranges[mn].combine < nst->prev_class)
1007 if (ucnranges[mn].combine == 0)
1009 nst->prev_class = ucnranges[mn].combine;
915 unsigned char combine; member in struct:ucnrange
|
| /src/external/mit/isl/dist/ |
| isl_output.c | 820 isl_bool combine; local
847 combine = dump ? isl_bool_false : next_is_opposite(bmap, i, l);
848 if (combine < 0)
850 if (combine) {
|
| /src/external/gpl3/gcc/dist/gcc/config/visium/ |
| visium.cc | 3528 unsigned int combine; /* Nonzero if we can combine the allocation of member in struct:visium_frame_info
3646 int combine; local
3685 combine = (local_frame_offset + var_size + reg_size) <= 32 * UNITS_PER_WORD;
3697 current_frame_info.combine = combine;
3872 const int combine = current_frame_info.combine; local
3898 /* If we can't combine register stacking with variable allocation, partially
3900 if (reg_size && !combine)
4132 const int combine = current_frame_info.combine; local
[all...] |
