1 /* $NetBSD: coram.c,v 1.21 2025/09/15 13:23:03 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2008, 2011 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: coram.c,v 1.21 2025/09/15 13:23:03 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/kmem.h> 36 #include <sys/mutex.h> 37 #include <sys/module.h> 38 #include <sys/bus.h> 39 40 #include <dev/dtv/dtvif.h> 41 42 #include <dev/pci/cx23885reg.h> 43 #include <dev/pci/coramvar.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/i2c/i2cvar.h> 49 #include <dev/i2c/at24cxxvar.h> 50 51 #include <dev/i2c/cx24227var.h> 52 #include <dev/i2c/mt2131var.h> 53 54 /* #define CORAM_DEBUG */ 55 /* #define CORAM_ATTACH_I2C */ 56 57 static const struct coram_board coram_boards[] = { 58 { PCI_VENDOR_HAUPPAUGE, 0x7911, "Hauppauge HVR-1250" }, 59 }; 60 61 static int coram_match(device_t, cfdata_t, void *); 62 static void coram_attach(device_t, device_t, void *); 63 static int coram_detach(device_t, int); 64 static int coram_rescan(device_t, const char *, const int *); 65 static void coram_childdet(device_t, device_t); 66 static bool coram_resume(device_t, const pmf_qual_t *); 67 static int coram_intr(void *); 68 static const struct coram_board * coram_board_lookup(uint16_t, uint16_t); 69 70 static int coram_iic_exec(void *, i2c_op_t, i2c_addr_t, 71 const void *, size_t, void *, size_t, int); 72 static int coram_iic_read(struct coram_iic_softc *, i2c_op_t, i2c_addr_t, 73 const void *, size_t, void *, size_t, int); 74 static int coram_iic_write(struct coram_iic_softc *, i2c_op_t, i2c_addr_t, 75 const void *, size_t, void *, size_t, int); 76 77 static void coram_dtv_get_devinfo(void *, struct dvb_frontend_info *); 78 static int coram_dtv_open(void *, int); 79 static void coram_dtv_close(void *); 80 static int coram_dtv_set_tuner(void *, const struct dvb_frontend_parameters *); 81 static fe_status_t coram_dtv_get_status(void *); 82 static uint16_t coram_dtv_get_signal_strength(void *); 83 static uint16_t coram_dtv_get_snr(void *); 84 static int coram_dtv_start_transfer(void *, void (*)(void *, const struct dtv_payload *), void *); 85 static int coram_dtv_stop_transfer(void *); 86 87 static int coram_mpeg_attach(struct coram_softc *); 88 static int coram_mpeg_detach(struct coram_softc *, int); 89 static int coram_mpeg_reset(struct coram_softc *); 90 static void * coram_mpeg_malloc(struct coram_softc *, size_t); 91 static int coram_allocmem(struct coram_softc *, size_t, size_t, struct coram_dma *); 92 static void coram_mpeg_free(struct coram_softc *, void *); 93 static int coram_mpeg_halt(struct coram_softc *); 94 static int coram_freemem(struct coram_softc *, struct coram_dma *); 95 static int coram_mpeg_trigger(struct coram_softc *, void *); 96 static int coram_risc_buffer(struct coram_softc *, uint32_t, uint32_t); 97 static int coram_risc_field(struct coram_softc *, uint32_t *, uint32_t); 98 static int coram_sram_ch_setup(struct coram_softc *, struct coram_sram_ch *, uint32_t); 99 static int coram_mpeg_intr(struct coram_softc *); 100 101 CFATTACH_DECL2_NEW(coram, sizeof(struct coram_softc), 102 coram_match, coram_attach, coram_detach, NULL, 103 coram_rescan, coram_childdet); 104 105 #define CORAM_SRAM_CH6 0 106 107 #define CORAM_TS_PKTSIZE (188 * 8) 108 109 static struct coram_sram_ch coram_sram_chs[] = { 110 [CORAM_SRAM_CH6] = { 111 .csc_cmds= 0x10140, 112 .csc_iq = 0x10500, 113 .csc_iqsz = 0x40, 114 .csc_cdt = 0x10600, 115 .csc_cdtsz = 0x10, 116 .csc_fifo = 0x6000, 117 .csc_fifosz = 0x1000, 118 .csc_risc = 0x10800, 119 .csc_riscsz = 0x800, 120 .csc_ptr1 = DMA5_PTR1, 121 .csc_ptr2 = DMA5_PTR2, 122 .csc_cnt1 = DMA5_CNT1, 123 .csc_cnt2 = DMA5_CNT2, 124 }, 125 }; 126 127 static const struct dtv_hw_if coram_dtv_if = { 128 .get_devinfo = coram_dtv_get_devinfo, 129 .open = coram_dtv_open, 130 .close = coram_dtv_close, 131 .set_tuner = coram_dtv_set_tuner, 132 .get_status = coram_dtv_get_status, 133 .get_signal_strength = coram_dtv_get_signal_strength, 134 .get_snr = coram_dtv_get_snr, 135 .start_transfer = coram_dtv_start_transfer, 136 .stop_transfer = coram_dtv_stop_transfer, 137 }; 138 139 static int 140 coram_match(device_t parent, cfdata_t match, void *v) 141 { 142 const struct pci_attach_args *pa = v; 143 pcireg_t subid; 144 145 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CONEXANT) 146 return 0; 147 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_CONEXANT_CX23885) 148 return 0; 149 150 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 151 if (coram_board_lookup(PCI_VENDOR(subid), PCI_PRODUCT(subid)) == NULL) 152 return 0; 153 154 return 1; 155 } 156 157 static void 158 coram_attach(device_t parent, device_t self, void *aux) 159 { 160 struct coram_softc *sc = device_private(self); 161 const struct pci_attach_args *pa = aux; 162 pci_intr_handle_t ih; 163 pcireg_t reg; 164 const char *intrstr; 165 struct coram_iic_softc *cic; 166 uint32_t value; 167 int i; 168 char intrbuf[PCI_INTRSTR_LEN]; 169 170 sc->sc_dev = self; 171 172 pci_aprint_devinfo(pa, NULL); 173 174 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 175 sc->sc_board = coram_board_lookup(PCI_VENDOR(reg), PCI_PRODUCT(reg)); 176 KASSERT(sc->sc_board != NULL); 177 178 if (pci_mapreg_map(pa, CX23885_MMBASE, PCI_MAPREG_TYPE_MEM, 0, 179 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { 180 aprint_error_dev(self, "couldn't map memory space\n"); 181 return; 182 } 183 184 sc->sc_dmat = pa->pa_dmat; 185 sc->sc_pc = pa->pa_pc; 186 187 if (pci_intr_map(pa, &ih)) { 188 aprint_error_dev(self, "couldn't map interrupt\n"); 189 return; 190 } 191 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 192 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_VM, coram_intr, 193 self, device_xname(self)); 194 if (sc->sc_ih == NULL) { 195 aprint_error_dev(self, "couldn't establish interrupt"); 196 if (intrstr != NULL) 197 aprint_error(" at %s", intrstr); 198 aprint_error("\n"); 199 return; 200 } 201 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 202 203 /* set master */ 204 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 205 reg |= PCI_COMMAND_MASTER_ENABLE; 206 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 207 208 /* I2C */ 209 for(i = 0; i < I2C_NUM; i++) { 210 cic = &sc->sc_iic[i]; 211 212 cic->cic_sc = sc; 213 if (bus_space_subregion(sc->sc_memt, sc->sc_memh, 214 I2C_BASE + (I2C_SIZE * i), I2C_SIZE, &cic->cic_regh)) 215 panic("failed to subregion i2c"); 216 217 iic_tag_init(&cic->cic_i2c); 218 cic->cic_i2c.ic_cookie = cic; 219 cic->cic_i2c.ic_exec = coram_iic_exec; 220 221 #ifdef CORAM_ATTACH_I2C 222 /* attach iic(4) */ 223 cic->cic_i2cdev = iicbus_attach(self, &cic->cic_i2c); 224 #endif 225 } 226 227 /* HVR1250 GPIO */ 228 value = bus_space_read_4(sc->sc_memt, sc->sc_memh, 0x110010); 229 #if 1 230 value &= ~0x00010001; 231 bus_space_write_4(sc->sc_memt, sc->sc_memh, 0x110010, value); 232 delay(5000); 233 #endif 234 value |= 0x00010001; 235 bus_space_write_4(sc->sc_memt, sc->sc_memh, 0x110010, value); 236 237 #if 0 238 int i; 239 uint8_t foo[256]; 240 uint8_t bar; 241 bar = 0; 242 // seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0, 256, foo, 256); 243 244 iic_acquire_bus(&sc->sc_i2c, 0); 245 iic_exec(&sc->sc_i2c, I2C_OP_READ_WITH_STOP, 0x50, &bar, 1, foo, 256, 246 0); 247 iic_release_bus(&sc->sc_i2c, 0); 248 249 printf("\n"); 250 for ( i = 0; i < 256; i++) { 251 if ( (i % 8) == 0 ) 252 printf("%02x: ", i); 253 254 printf("%02x", foo[i]); 255 256 if ( (i % 8) == 7 ) 257 printf("\n"); 258 else 259 printf(" "); 260 } 261 printf("\n"); 262 #endif 263 264 sc->sc_demod = cx24227_open(sc->sc_dev, &sc->sc_iic[0].cic_i2c, 0x19); 265 if (sc->sc_demod == NULL) 266 aprint_error_dev(self, "couldn't open cx24227\n"); 267 sc->sc_tuner = mt2131_open(sc->sc_dev, &sc->sc_iic[0].cic_i2c, 0x61); 268 if (sc->sc_tuner == NULL) 269 aprint_error_dev(self, "couldn't open mt2131\n"); 270 271 coram_mpeg_attach(sc); 272 273 if (!pmf_device_register(self, NULL, coram_resume)) 274 aprint_error_dev(self, "couldn't establish power handler\n"); 275 276 return; 277 } 278 279 static int 280 coram_detach(device_t self, int flags) 281 { 282 struct coram_softc *sc = device_private(self); 283 struct coram_iic_softc *cic; 284 unsigned int i; 285 int error; 286 287 error = coram_mpeg_detach(sc, flags); 288 if (error) 289 return error; 290 291 if (sc->sc_tuner) 292 mt2131_close(sc->sc_tuner); 293 if (sc->sc_demod) 294 cx24227_close(sc->sc_demod); 295 for (i = 0; i < I2C_NUM; i++) { 296 cic = &sc->sc_iic[i]; 297 if (cic->cic_i2cdev) 298 config_detach(cic->cic_i2cdev, flags); 299 iic_tag_fini(&cic->cic_i2c); 300 } 301 pmf_device_deregister(self); 302 303 if (sc->sc_mems) 304 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 305 if (sc->sc_ih) 306 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 307 308 return 0; 309 } 310 311 static int 312 coram_rescan(device_t self, const char *ifattr, const int *locs) 313 { 314 struct coram_softc *sc = device_private(self); 315 struct dtv_attach_args daa; 316 317 daa.hw = &coram_dtv_if; 318 daa.priv = sc; 319 320 if (ifattr_match(ifattr, "dtvbus") && sc->sc_dtvdev == NULL) 321 sc->sc_dtvdev = config_found(sc->sc_dev, &daa, dtv_print, 322 CFARGS(.iattr = "dtvbus")); 323 324 return 0; 325 } 326 327 static void 328 coram_childdet(device_t self, device_t child) 329 { 330 struct coram_softc *sc = device_private(self); 331 struct coram_iic_softc *cic; 332 unsigned int i; 333 334 if (sc->sc_dtvdev == child) 335 sc->sc_dtvdev = NULL; 336 337 for (i = 0; i < I2C_NUM; i++) { 338 cic = &sc->sc_iic[i]; 339 if (cic->cic_i2cdev == child) 340 cic->cic_i2cdev = NULL; 341 } 342 } 343 344 static int 345 coram_intr(void *v) 346 { 347 device_t self = v; 348 struct coram_softc *sc; 349 uint32_t val; 350 351 sc = device_private(self); 352 353 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSTAT ); 354 if (val == 0) 355 return 0; /* not ours */ 356 357 /* vid c */ 358 if (val & __BIT(2)) 359 coram_mpeg_intr(sc); 360 361 if (val & ~__BIT(2)) 362 printf("%s %08x\n", __func__, val); 363 364 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_STAT, val); 365 366 return 1; 367 } 368 369 static const struct coram_board * 370 coram_board_lookup(uint16_t vendor, uint16_t product) 371 { 372 unsigned int i; 373 374 for (i = 0; i < __arraycount(coram_boards); i++) { 375 if (coram_boards[i].vendor == vendor && 376 coram_boards[i].product == product) { 377 return &coram_boards[i]; 378 } 379 } 380 381 return NULL; 382 } 383 384 #define CXDTV_TS_RISCI2 (1 << 4) 385 #define CXDTV_TS_RISCI1 (1 << 0) 386 387 #define CXDTV_TS_RISCI (CXDTV_TS_RISCI1|CXDTV_TS_RISCI2) 388 389 static int 390 coram_mpeg_intr(struct coram_softc *sc) 391 { 392 struct dtv_payload payload; 393 uint32_t s, m, v; 394 int i; 395 396 s = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT); 397 m = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 398 399 if ((s & m) == 0) 400 return 0; 401 402 if ( (s & ~CXDTV_TS_RISCI) != 0 ) { 403 printf("%s: unexpected TS IS %08x\n", 404 device_xname(sc->sc_dev), s); 405 406 printf("cmds:\n"); 407 for(i = 0; i < 20; i++) 408 { 409 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, 0x10140 +(i*4)); 410 printf("%06x %08x\n", 0x10140+(i*4), v); 411 } 412 } 413 414 if (sc->sc_dtvsubmitcb == NULL) 415 goto done; 416 417 if ((s & CXDTV_TS_RISCI1) == CXDTV_TS_RISCI1) { 418 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 419 0, CORAM_TS_PKTSIZE, 420 BUS_DMASYNC_POSTREAD); 421 payload.data = KERNADDR(sc->sc_dma); 422 payload.size = CORAM_TS_PKTSIZE; 423 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 424 } 425 426 if ((s & CXDTV_TS_RISCI2) == CXDTV_TS_RISCI2) { 427 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 428 CORAM_TS_PKTSIZE, CORAM_TS_PKTSIZE, 429 BUS_DMASYNC_POSTREAD); 430 payload.data = (char *)(KERNADDR(sc->sc_dma)) + (uintptr_t)CORAM_TS_PKTSIZE; 431 payload.size = CORAM_TS_PKTSIZE; 432 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 433 } 434 435 done: 436 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT, s); 437 438 return 1; 439 } 440 441 static bool 442 coram_resume(device_t dv, const pmf_qual_t *qual) 443 { 444 return true; 445 } 446 447 /* I2C Bus */ 448 449 #define I2C_ADDR 0x0000 450 #define I2C_WDATA 0x0004 451 #define I2C_CTRL 0x0008 452 #define I2C_RDATA 0x000c 453 #define I2C_STAT 0x0010 454 455 #define I2C_EXTEND (1 << 3) 456 #define I2C_NOSTOP (1 << 4) 457 458 static int 459 coram_iic_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 460 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 461 { 462 struct coram_iic_softc *cic; 463 int ret; 464 465 cic = cookie; 466 467 if(cmdlen) { 468 ret = coram_iic_write(cic, op, addr, cmdbuf, cmdlen, buf, len, flags); 469 if(ret) 470 return ret; 471 } 472 473 if(len) { 474 ret = coram_iic_read(cic, op, addr, cmdbuf, cmdlen, buf, len, flags); 475 if(ret) 476 return ret; 477 } 478 479 480 return 0; 481 482 } 483 484 static int 485 coram_iic_read(struct coram_iic_softc *cic, i2c_op_t op, i2c_addr_t addr, 486 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 487 { 488 uint8_t *rb; 489 uint32_t ctrl; 490 int bn; 491 492 rb = buf; 493 494 for ( bn = 0; bn < len; bn++) { 495 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2) | 1; 496 if ( bn < len - 1 ) 497 ctrl |= I2C_NOSTOP | I2C_EXTEND; 498 499 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addr<<25); 500 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 501 502 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, 503 I2C_STAT) & 0x02)) { 504 delay(25); 505 } 506 if((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, 507 I2C_STAT) & 0x01) == 0x00) { 508 // printf("%s %d no ack\n", __func__, bn); 509 return EIO; 510 } 511 512 rb[bn] = bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_RDATA); 513 514 } 515 516 return 0; 517 } 518 519 static int 520 coram_iic_write(struct coram_iic_softc *cic, i2c_op_t op, i2c_addr_t addr, 521 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 522 { 523 const uint8_t *wb; 524 uint32_t wdata, addrreg, ctrl; 525 int bn; 526 527 wb = cmdbuf; 528 529 addrreg = (addr << 25) | wb[0]; 530 wdata = wb[0]; 531 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2); 532 533 if ( cmdlen > 1 ) 534 ctrl |= I2C_NOSTOP | I2C_EXTEND; 535 else if (len) 536 ctrl |= I2C_NOSTOP; 537 538 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addrreg); 539 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_WDATA, wdata); 540 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 541 542 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_STAT) & 0x02)) { 543 delay(25); } 544 545 for ( bn = 1; bn < cmdlen; bn++) { 546 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2); 547 wdata = wb[bn]; 548 549 if ( bn < cmdlen - 1 ) 550 ctrl |= I2C_NOSTOP | I2C_EXTEND; 551 else if (len) 552 ctrl |= I2C_NOSTOP; 553 554 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addrreg); 555 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_WDATA, wdata); 556 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 557 558 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_STAT) & 0x02)) { 559 delay(25); } 560 } 561 562 return 0; 563 } 564 565 static int 566 coram_mpeg_attach(struct coram_softc *sc) 567 { 568 struct coram_sram_ch *ch; 569 570 ch = &coram_sram_chs[CORAM_SRAM_CH6]; 571 572 sc->sc_riscbufsz = ch->csc_riscsz; 573 sc->sc_riscbuf = kmem_alloc(ch->csc_riscsz, KM_SLEEP); 574 575 coram_mpeg_reset(sc); 576 577 sc->sc_tsbuf = NULL; 578 579 coram_rescan(sc->sc_dev, NULL, NULL); 580 581 return (sc->sc_dtvdev != NULL); 582 } 583 584 static int 585 coram_mpeg_detach(struct coram_softc *sc, int flags) 586 { 587 struct coram_sram_ch *ch = &coram_sram_chs[CORAM_SRAM_CH6]; 588 int error; 589 590 if (sc->sc_dtvdev) { 591 error = config_detach(sc->sc_dtvdev, flags); 592 if (error) 593 return error; 594 } 595 if (sc->sc_riscbuf) { 596 kmem_free(sc->sc_riscbuf, ch->csc_riscsz); 597 } 598 599 return 0; 600 } 601 602 static void 603 coram_dtv_get_devinfo(void *cookie, struct dvb_frontend_info *info) 604 { 605 struct coram_softc *sc = cookie; 606 607 memset(info, 0, sizeof(*info)); 608 strlcpy(info->name, sc->sc_board->name, sizeof(info->name)); 609 info->type = FE_ATSC; 610 info->frequency_min = 54000000; 611 info->frequency_max = 858000000; 612 info->frequency_stepsize = 62500; 613 info->caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB; 614 } 615 616 static int 617 coram_dtv_open(void *cookie, int flags) 618 { 619 struct coram_softc *sc = cookie; 620 621 #ifdef CORAM_DEBUG 622 device_printf(sc->sc_dev, "%s\n", __func__); 623 #endif 624 625 //KASSERT(sc->sc_tsbuf == NULL); 626 627 if (sc->sc_tuner == NULL || sc->sc_demod == NULL) 628 return ENXIO; 629 630 coram_mpeg_reset(sc); 631 632 /* allocate two alternating DMA areas for MPEG TS packets */ 633 sc->sc_tsbuf = coram_mpeg_malloc(sc, CORAM_TS_PKTSIZE * 2); 634 635 if (sc->sc_tsbuf == NULL) 636 return ENOMEM; 637 638 return 0; 639 } 640 641 static void 642 coram_dtv_close(void *cookie) 643 { 644 struct coram_softc *sc = cookie; 645 646 #ifdef CORAM_DEBUG 647 device_printf(sc->sc_dev, "%s\n", __func__); 648 #endif 649 650 coram_mpeg_halt(sc); 651 652 if (sc->sc_tsbuf != NULL) { 653 coram_mpeg_free(sc, sc->sc_tsbuf); 654 sc->sc_tsbuf = NULL; 655 } 656 } 657 658 static int 659 coram_dtv_set_tuner(void *cookie, const struct dvb_frontend_parameters *params) 660 { 661 struct coram_softc *sc = cookie; 662 663 KASSERT(sc->sc_tuner != NULL); 664 mt2131_tune_dtv(sc->sc_tuner, params); 665 KASSERT(sc->sc_demod != NULL); 666 return cx24227_set_modulation(sc->sc_demod, params->u.vsb.modulation); 667 } 668 669 static fe_status_t 670 coram_dtv_get_status(void *cookie) 671 { 672 struct coram_softc *sc = cookie; 673 674 if (sc->sc_demod == NULL) 675 return ENXIO; 676 677 return cx24227_get_dtv_status(sc->sc_demod); 678 } 679 680 static uint16_t 681 coram_dtv_get_signal_strength(void *cookie) 682 { 683 return 0; 684 } 685 686 static uint16_t 687 coram_dtv_get_snr(void *cookie) 688 { 689 return 0; 690 } 691 692 static int 693 coram_dtv_start_transfer(void *cookie, 694 void (*cb)(void *, const struct dtv_payload *), void *arg) 695 { 696 struct coram_softc *sc = cookie; 697 698 #ifdef CORAM_DEBUG 699 device_printf(sc->sc_dev, "%s\n", __func__); 700 #endif 701 702 sc->sc_dtvsubmitcb = cb; 703 sc->sc_dtvsubmitarg = arg; 704 705 coram_mpeg_trigger(sc, sc->sc_tsbuf); 706 707 return 0; 708 } 709 710 static int 711 coram_dtv_stop_transfer(void *cookie) 712 { 713 struct coram_softc *sc = cookie; 714 715 #ifdef CORAM_DEBUG 716 device_printf(sc->sc_dev, "%s\n", __func__); 717 #endif 718 719 coram_mpeg_halt(sc); 720 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 0); 721 722 sc->sc_dtvsubmitcb = NULL; 723 sc->sc_dtvsubmitarg = NULL; 724 725 return 0; 726 } 727 728 729 static int 730 coram_mpeg_reset(struct coram_softc *sc) 731 { 732 /* hold RISC in reset */ 733 bus_space_write_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2, 0); 734 735 /* disable fifo + risc */ 736 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 737 738 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 0); 739 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, 0); 740 741 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_STAT, 0); 742 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT, 0); 743 744 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 745 746 return 0; 747 } 748 749 static void * 750 coram_mpeg_malloc(struct coram_softc *sc, size_t size) 751 { 752 struct coram_dma *p; 753 int err; 754 755 p = kmem_alloc(sizeof(struct coram_dma), KM_SLEEP); 756 err = coram_allocmem(sc, size, 16, p); 757 if (err) { 758 kmem_free(p, sizeof(struct coram_dma)); 759 return NULL; 760 } 761 762 p->next = sc->sc_dma; 763 sc->sc_dma = p; 764 765 return KERNADDR(p); 766 } 767 768 static int 769 coram_allocmem(struct coram_softc *sc, size_t size, size_t align, 770 struct coram_dma *p) 771 { 772 int err; 773 774 p->size = size; 775 err = bus_dmamem_alloc(sc->sc_dmat, p->size, align, 0, 776 p->segs, sizeof(p->segs) / sizeof(p->segs[0]), 777 &p->nsegs, BUS_DMA_NOWAIT); 778 if (err) 779 return err; 780 err = bus_dmamem_map(sc->sc_dmat, p->segs, p->nsegs, p->size, 781 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 782 if (err) 783 goto free; 784 err = bus_dmamap_create(sc->sc_dmat, p->size, 1, p->size, 0, 785 BUS_DMA_NOWAIT, &p->map); 786 if (err) 787 goto unmap; 788 err = bus_dmamap_load(sc->sc_dmat, p->map, p->addr, p->size, NULL, 789 BUS_DMA_NOWAIT); 790 if (err) 791 goto destroy; 792 793 return 0; 794 destroy: 795 bus_dmamap_destroy(sc->sc_dmat, p->map); 796 unmap: 797 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 798 free: 799 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 800 801 return err; 802 } 803 804 static int 805 coram_mpeg_halt(struct coram_softc *sc) 806 { 807 uint32_t v; 808 809 #ifdef CORAM_DEBUG 810 device_printf(sc->sc_dev, "%s\n", __func__); 811 #endif 812 813 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 814 815 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK); 816 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 817 v & __BIT(2)); 818 819 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 820 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, 821 v & 0); 822 823 return 0; 824 } 825 826 static void 827 coram_mpeg_free(struct coram_softc *sc, void *addr) 828 { 829 struct coram_dma *p; 830 struct coram_dma **pp; 831 832 for (pp = &sc->sc_dma; (p = *pp) != NULL; pp = &p->next) 833 if (KERNADDR(p) == addr) { 834 coram_freemem(sc, p); 835 *pp = p->next; 836 kmem_free(p, sizeof(struct coram_dma)); 837 return; 838 } 839 840 printf("%s: %p is already free\n", device_xname(sc->sc_dev), addr); 841 return; 842 } 843 844 static int 845 coram_freemem(struct coram_softc *sc, struct coram_dma *p) 846 { 847 bus_dmamap_unload(sc->sc_dmat, p->map); 848 bus_dmamap_destroy(sc->sc_dmat, p->map); 849 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 850 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 851 852 return 0; 853 } 854 855 static int 856 coram_mpeg_trigger(struct coram_softc *sc, void *buf) 857 { 858 struct coram_dma *p; 859 struct coram_sram_ch *ch; 860 uint32_t v; 861 862 ch = &coram_sram_chs[CORAM_SRAM_CH6]; 863 864 for (p = sc->sc_dma; p && KERNADDR(p) != buf; p = p->next) 865 continue; 866 if (p == NULL) { 867 printf("%s: coram_mpeg_trigger: bad addr %p\n", 868 device_xname(sc->sc_dev), buf); 869 return ENOENT; 870 } 871 872 /* disable fifo + risc */ 873 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 874 875 coram_risc_buffer(sc, CORAM_TS_PKTSIZE, 1); 876 coram_sram_ch_setup(sc, ch, CORAM_TS_PKTSIZE); 877 878 /* let me hope this bit is the same as on the 2388[0-3] */ 879 /* software reset */ 880 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL, 0x0040); 881 delay (100*1000); 882 883 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_LNGTH, CORAM_TS_PKTSIZE); 884 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_HW_SOP_CTL, 0x47 << 16 | 188 << 4); 885 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_TS_CLK_EN, 1); 886 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_VLD_MISC, 0); 887 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL, 12); 888 delay (100*1000); 889 890 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PAD_CTRL); 891 v &= ~0x4; /* Clear TS2_SOP_OE */ 892 bus_space_write_4(sc->sc_memt, sc->sc_memh, PAD_CTRL, v); 893 894 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 895 v |= 0x111111; 896 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, v); 897 898 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL); 899 v |= 0x11; /* Enable RISC controller and FIFO */ 900 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, v); 901 902 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2); 903 v |= __BIT(5); /* Enable RISC controller */ 904 bus_space_write_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2, v); 905 906 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK); 907 v |= 0x001f00; 908 v |= 0x04; 909 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, v); 910 911 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL); 912 #ifdef CORAM_DEBUG 913 printf("%s, %06x %08x\n", __func__, VID_C_GEN_CTL, v); 914 #endif 915 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_SOP_STATUS); 916 #ifdef CORAM_DEBUG 917 printf("%s, %06x %08x\n", __func__, VID_C_SOP_STATUS, v); 918 #endif 919 delay(100*1000); 920 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL); 921 #ifdef CORAM_DEBUG 922 printf("%s, %06x %08x\n", __func__, VID_C_GEN_CTL, v); 923 #endif 924 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_SOP_STATUS); 925 #ifdef CORAM_DEBUG 926 printf("%s, %06x %08x\n", __func__, VID_C_SOP_STATUS, v); 927 #endif 928 929 return 0; 930 } 931 932 static int 933 coram_risc_buffer(struct coram_softc *sc, uint32_t bpl, uint32_t lines) 934 { 935 uint32_t *rm; 936 uint32_t size; 937 938 size = 1 + (bpl * lines) / PAGE_SIZE + lines; 939 size += 2; 940 941 if (sc->sc_riscbuf == NULL) { 942 return ENOMEM; 943 } 944 945 rm = (uint32_t *)sc->sc_riscbuf; 946 coram_risc_field(sc, rm, bpl); 947 948 return 0; 949 } 950 951 static int 952 coram_risc_field(struct coram_softc *sc, uint32_t *rm, uint32_t bpl) 953 { 954 struct coram_dma *p; 955 956 for (p = sc->sc_dma; p && KERNADDR(p) != sc->sc_tsbuf; p = p->next) 957 continue; 958 if (p == NULL) { 959 printf("%s: coram_risc_field: bad addr %p\n", 960 device_xname(sc->sc_dev), sc->sc_tsbuf); 961 return ENOENT; 962 } 963 964 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 965 966 rm = sc->sc_riscbuf; 967 968 /* htole32 will be done when program is copied to chip sram */ 969 970 /* XXX */ 971 *(rm++) = (CX_RISC_SYNC|0); 972 973 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ1|bpl); 974 *(rm++) = (DMAADDR(p) + 0 * bpl); 975 *(rm++) = 0; /* high dword */ 976 977 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ2|bpl); 978 *(rm++) = (DMAADDR(p) + 1 * bpl); 979 *(rm++) = 0; 980 981 *(rm++) = (CX_RISC_JUMP|1); 982 *(rm++) = (coram_sram_chs[CORAM_SRAM_CH6].csc_risc + 4); 983 *(rm++) = 0; 984 985 return 0; 986 } 987 988 static int 989 coram_sram_ch_setup(struct coram_softc *sc, struct coram_sram_ch *csc, 990 uint32_t bpl) 991 { 992 unsigned int i, lines; 993 uint32_t cdt; 994 995 /* XXX why round? */ 996 bpl = (bpl + 7) & ~7; 997 cdt = csc->csc_cdt; 998 lines = csc->csc_fifosz / bpl; 999 #ifdef CORAM_DEBUG 1000 printf("%s %d lines\n", __func__, lines); 1001 #endif 1002 1003 /* fill in CDT */ 1004 for (i = 0; i < lines; i++) { 1005 #ifdef CORAM_DEBUG 1006 printf("CDT ent %08x, %08x\n", cdt + (16 * i), 1007 csc->csc_fifo + (bpl * i)); 1008 #endif 1009 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1010 cdt + (16 * i), csc->csc_fifo + (bpl * i)); 1011 } 1012 1013 /* copy program */ 1014 /* converts program to little endian as it goes into sram */ 1015 bus_space_write_region_4(sc->sc_memt, sc->sc_memh, 1016 csc->csc_risc, (void *)sc->sc_riscbuf, sc->sc_riscbufsz >> 2); 1017 1018 /* fill in CMDS */ 1019 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1020 csc->csc_cmds + CMDS_O_IRPC, csc->csc_risc); 1021 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1022 csc->csc_cmds + CMDS_O_IRPC + 4, 0); 1023 1024 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1025 csc->csc_cmds + CMDS_O_CDTB, csc->csc_cdt); 1026 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1027 csc->csc_cmds + CMDS_O_CDTS, (lines * 16) >> 3); /* XXX magic */ 1028 1029 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1030 csc->csc_cmds + CMDS_O_IQB, csc->csc_iq); 1031 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1032 csc->csc_cmds + CMDS_O_IQS, 1033 CMDS_IQS_ISRP | (csc->csc_iqsz >> 2) ); 1034 1035 /* zero rest of CMDS */ 1036 bus_space_set_region_4(sc->sc_memt, sc->sc_memh, 0x18, 0, 20); 1037 1038 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1039 csc->csc_ptr1, csc->csc_fifo); 1040 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1041 csc->csc_ptr2, cdt); 1042 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1043 csc->csc_cnt2, (lines * 16) >> 3); 1044 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1045 csc->csc_cnt1, (bpl >> 3) - 1); 1046 1047 return 0; 1048 } 1049 1050 MODULE(MODULE_CLASS_DRIVER, coram, "cx24227,mt2131,pci"); 1051 1052 #ifdef _MODULE 1053 #include "ioconf.c" 1054 #endif 1055 1056 static int 1057 coram_modcmd(modcmd_t cmd, void *v) 1058 { 1059 int error = 0; 1060 1061 switch (cmd) { 1062 case MODULE_CMD_INIT: 1063 #ifdef _MODULE 1064 error = config_init_component(cfdriver_ioconf_coram, 1065 cfattach_ioconf_coram, cfdata_ioconf_coram); 1066 #endif 1067 return error; 1068 case MODULE_CMD_FINI: 1069 #ifdef _MODULE 1070 error = config_fini_component(cfdriver_ioconf_coram, 1071 cfattach_ioconf_coram, cfdata_ioconf_coram); 1072 #endif 1073 return error; 1074 default: 1075 return ENOTTY; 1076 } 1077 } 1078
Indexes created Mon Sep 22 13:09:51 GMT 2025