1 /* $NetBSD: ti_wdt.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: ti_wdt.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/device.h> 36 #include <sys/wdog.h> 37 38 #include <dev/sysmon/sysmonvar.h> 39 40 #include <dev/fdt/fdtvar.h> 41 42 #include <arm/ti/ti_prcm.h> 43 44 #define WDT_WDSC 0x10 45 #define WDSC_SOFTRESET __BIT(1) 46 #define WDT_WDST 0x14 47 #define WDT_WISR 0x18 48 #define WDT_WIER 0x1c 49 #define WDT_WCLR 0x24 50 #define WCLR_PRE __BIT(5) 51 #define WCLR_PTV __BITS(4,2) 52 #define WDT_WCRR 0x28 53 #define WDT_WLDR 0x2c 54 #define WDT_WTGR 0x30 55 #define WDT_WWPS 0x34 56 #define WWPS_W_PEND_WDLY __BIT(5) 57 #define WWPS_W_PEND_WSPR __BIT(4) 58 #define WWPS_W_PEND_WTGR __BIT(3) 59 #define WWPS_W_PEND_WLDR __BIT(2) 60 #define WWPS_W_PEND_WCRR __BIT(1) 61 #define WWPS_W_PEND_WCLR __BIT(0) 62 #define WWPS_W_PEND_MASK __BITS(5,0) 63 #define WDT_WDLY 0x44 64 #define WDT_WSPR 0x48 65 #define WDT_WIRQSTATRAW 0x54 66 #define WDT_WIRQSTAT 0x58 67 #define WDT_WIRQENSET 0x5c 68 #define WDT_WIRQENCLR 0x60 69 #define WIRQ_EVENT_DLY __BIT(1) 70 #define WIRQ_EVENT_OVF __BIT(0) 71 72 #define WATCHDOG_PERIOD_DEFAULT 10 73 74 static const struct device_compatible_entry compat_data[] = { 75 { .compat = "ti,omap3-wdt" }, 76 DEVICE_COMPAT_EOL 77 }; 78 79 struct ti_wdt_softc { 80 device_t sc_dev; 81 bus_space_tag_t sc_bst; 82 bus_space_handle_t sc_bsh; 83 84 struct sysmon_wdog sc_wdog; 85 u_int sc_rate; 86 }; 87 88 #define RD4(sc, reg) \ 89 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 90 #define WR4(sc, reg, val) \ 91 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 92 93 static void 94 ti_wdt_sync(struct ti_wdt_softc *sc, uint32_t mask) 95 { 96 uint32_t val; 97 int retry; 98 99 for (retry = 10000; retry > 0; retry--) { 100 val = RD4(sc, WDT_WWPS); 101 if ((val & mask) == 0) 102 return; 103 } 104 105 aprint_error_dev(sc->sc_dev, 106 "reg sync timeout, mask=%#x, wwps=%#x\n", mask, val); 107 } 108 109 static void 110 ti_wdt_sync_all(struct ti_wdt_softc *sc) 111 { 112 ti_wdt_sync(sc, WWPS_W_PEND_MASK); 113 } 114 115 static int 116 ti_wdt_reset(struct ti_wdt_softc *sc) 117 { 118 uint32_t val; 119 int retry; 120 121 val = RD4(sc, WDT_WDSC); 122 val |= WDSC_SOFTRESET; 123 WR4(sc, WDT_WDSC, val); 124 for (retry = 10000; retry > 0; retry--) { 125 val = RD4(sc, WDT_WDSC); 126 if ((val & WDSC_SOFTRESET) == 0) 127 return 0; 128 delay(10); 129 } 130 131 return EIO; 132 } 133 134 static void 135 ti_wdt_stop(struct ti_wdt_softc *sc) 136 { 137 WR4(sc, WDT_WSPR, 0xaaaa); 138 ti_wdt_sync(sc, WWPS_W_PEND_WSPR); 139 WR4(sc, WDT_WSPR, 0x5555); 140 ti_wdt_sync(sc, WWPS_W_PEND_WSPR); 141 } 142 143 static void 144 ti_wdt_start(struct ti_wdt_softc *sc) 145 { 146 WR4(sc, WDT_WSPR, 0xbbbb); 147 ti_wdt_sync(sc, WWPS_W_PEND_WSPR); 148 WR4(sc, WDT_WSPR, 0x4444); 149 ti_wdt_sync(sc, WWPS_W_PEND_WSPR); 150 } 151 152 static int 153 ti_wdt_setmode(struct sysmon_wdog *smw) 154 { 155 struct ti_wdt_softc * const sc = smw->smw_cookie; 156 uint32_t counter_val; 157 158 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 159 ti_wdt_stop(sc); 160 return 0; 161 } 162 163 if (smw->smw_period == WDOG_PERIOD_DEFAULT) 164 sc->sc_wdog.smw_period = WATCHDOG_PERIOD_DEFAULT; 165 else 166 sc->sc_wdog.smw_period = smw->smw_period; 167 168 if (sc->sc_wdog.smw_period == 0) 169 counter_val = ~0u; 170 else 171 counter_val = ~(sc->sc_wdog.smw_period * sc->sc_rate / 2); 172 173 ti_wdt_stop(sc); 174 ti_wdt_sync_all(sc); 175 176 WR4(sc, WDT_WCLR, WCLR_PRE | __SHIFTIN(1, WCLR_PTV)); 177 WR4(sc, WDT_WLDR, counter_val); 178 WR4(sc, WDT_WCRR, counter_val); 179 180 ti_wdt_sync_all(sc); 181 182 ti_wdt_start(sc); 183 184 return 0; 185 } 186 187 static int 188 ti_wdt_tickle(struct sysmon_wdog *smw) 189 { 190 struct ti_wdt_softc * const sc = smw->smw_cookie; 191 uint32_t val; 192 193 ti_wdt_sync_all(sc); 194 val = RD4(sc, WDT_WTGR); 195 WR4(sc, WDT_WTGR, ~val); 196 197 return 0; 198 } 199 200 static int 201 ti_wdt_match(device_t parent, cfdata_t cf, void *aux) 202 { 203 struct fdt_attach_args * const faa = aux; 204 205 return of_compatible_match(faa->faa_phandle, compat_data); 206 } 207 208 static void 209 ti_wdt_attach(device_t parent, device_t self, void *aux) 210 { 211 struct ti_wdt_softc * const sc = device_private(self); 212 struct fdt_attach_args * const faa = aux; 213 const int phandle = faa->faa_phandle; 214 struct clk *clk; 215 bus_addr_t addr; 216 bus_size_t size; 217 218 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 219 aprint_error(": couldn't get registers\n"); 220 return; 221 } 222 223 clk = ti_prcm_get_hwmod(phandle, 0); 224 if (clk == NULL || clk_enable(clk) != 0) { 225 aprint_error(": couldn't enable hwmod\n"); 226 return; 227 } 228 229 sc->sc_dev = self; 230 sc->sc_bst = faa->faa_bst; 231 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 232 aprint_error(": couldn't map registers\n"); 233 return; 234 } 235 sc->sc_rate = clk_get_rate(clk); 236 237 aprint_naive("\n"); 238 aprint_normal(": WATCHDOG\n"); 239 240 /* Software reset */ 241 if (ti_wdt_reset(sc) != 0) { 242 aprint_error_dev(self, "software reset timeout\n"); 243 return; 244 } 245 246 /* Stop the watchdog */ 247 ti_wdt_stop(sc); 248 249 /* Register watchdog */ 250 sc->sc_wdog.smw_name = device_xname(self); 251 sc->sc_wdog.smw_setmode = ti_wdt_setmode; 252 sc->sc_wdog.smw_tickle = ti_wdt_tickle; 253 sc->sc_wdog.smw_period = WATCHDOG_PERIOD_DEFAULT; 254 sc->sc_wdog.smw_cookie = sc; 255 sysmon_wdog_register(&sc->sc_wdog); 256 } 257 258 CFATTACH_DECL_NEW(ti_wdt, sizeof(struct ti_wdt_softc), 259 ti_wdt_match, ti_wdt_attach, NULL, NULL); 260
Indexes created Tue Sep 30 20:09:53 GMT 2025