| /src/sys/external/bsd/compiler_rt/dist/test/builtins/Unit/arm/ |
| aeabi_cdcmpeq_test.c | 27 union cpsr cpsr = { .value = cpsr_value }; local
28 if (expected != cpsr.flags.z) {
30 a, b, cpsr.flags.z, expected);
|
| aeabi_cfcmpeq_test.c | 27 union cpsr cpsr = { .value = cpsr_value }; local
28 if (expected != cpsr.flags.z) {
30 a, b, cpsr.flags.z, expected);
|
| aeabi_cdcmple_test.c | 50 union cpsr cpsr = { .value = cpsr_value }; local
51 if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) {
53 a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c);
57 cpsr.value = r_cpsr_value;
58 if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) {
60 a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c)
[all...] |
| aeabi_cfcmple_test.c | 50 union cpsr cpsr = { .value = cpsr_value }; local
51 if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) {
53 a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c);
57 cpsr.value = r_cpsr_value;
58 if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) {
60 a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c)
[all...] |
| call_apsr.h | 22 union cpsr { union
|
| /src/external/gpl3/gdb/dist/gdb/ |
| aarch32-linux-nat.c | 70 uint32_t cpsr = regs[ARM_CPSR_GREGNUM]; local
75 | (cpsr & 0x00f00000));
|
| arm-netbsd-tdep.c | 49 uint32_t cpsr; member in struct:arm_nbsd_reg
82 regcache->raw_supply (ARM_PS_REGNUM, (char *) &gregset->cpsr);
|
| arm-linux-tdep.c | 354 CORE_ADDR cpsr = get_frame_register_unsigned (this_frame, ARM_PS_REGNUM); local
368 /* Update Thumb bit in CPSR. */
370 cpsr |= t_bit;
372 cpsr &= ~t_bit;
380 trad_frame_set_reg_value (this_cache, ARM_PS_REGNUM, cpsr);
770 CORE_ADDR cpsr local
773 *is_thumb = (cpsr & t_bit) != 0;
796 CORE_ADDR cpsr; local
810 /* Set IS_THUMB according the CPSR saved on the stack. */
811 cpsr = read_memory_unsigned_integer (sp + pc_offset + 4, 4, byte_order)
855 ULONGEST cpsr; local
[all...] |
| arm-tdep.c | 232 "fps", "cpsr" }; /* 24 25 */
619 ULONGEST cpsr; local
622 cpsr = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM);
624 return (cpsr & t_bit) != 0;
637 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
641 CORE_ADDR cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM); local
645 return (cpsr & t_bit) != 0;
765 target, then trust the current value of $cpsr. This lets
2448 /* The CPSR may have been changed by the call instruction and by the
2458 ULONGEST cpsr = get_frame_register_unsigned (this_frame, prev_regnum) local
4003 ULONGEST cpsr; local
[all...] |
| /src/external/gpl3/gdb.old/dist/gdb/ |
| aarch32-linux-nat.c | 70 uint32_t cpsr = regs[ARM_CPSR_GREGNUM]; local
75 | (cpsr & 0x00f00000));
|
| arm-netbsd-tdep.c | 49 uint32_t cpsr; member in struct:arm_nbsd_reg
82 regcache->raw_supply (ARM_PS_REGNUM, (char *) &gregset->cpsr);
|
| arm-linux-tdep.c | 353 CORE_ADDR cpsr = get_frame_register_unsigned (this_frame, ARM_PS_REGNUM); local
367 /* Update Thumb bit in CPSR. */
369 cpsr |= t_bit;
371 cpsr &= ~t_bit;
379 trad_frame_set_reg_value (this_cache, ARM_PS_REGNUM, cpsr);
769 CORE_ADDR cpsr local
772 *is_thumb = (cpsr & t_bit) != 0;
795 CORE_ADDR cpsr; local
809 /* Set IS_THUMB according the CPSR saved on the stack. */
810 cpsr = read_memory_unsigned_integer (sp + pc_offset + 4, 4, byte_order)
854 ULONGEST cpsr; local
[all...] |
| arm-tdep.c | 232 "fps", "cpsr" }; /* 24 25 */
619 ULONGEST cpsr; local
622 cpsr = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM);
624 return (cpsr & t_bit) != 0;
637 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
641 CORE_ADDR cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM); local
645 return (cpsr & t_bit) != 0;
766 target, then trust the current value of $cpsr. This lets
2451 /* The CPSR may have been changed by the call instruction and by the
2461 ULONGEST cpsr = get_frame_register_unsigned (this_frame, prev_regnum) local
4006 ULONGEST cpsr; local
[all...] |
| /src/sys/arch/zaurus/stand/zbsdmod/ |
| zbsdmod.c | 83 static int cpsr; variable
155 __asm volatile ("mrs %0, cpsr" : "=r" (cpsr));
156 cpsr |= 0xc0; /* set FI */
157 __asm volatile ("msr cpsr_all, %0" :: "r" (cpsr));
|
| /src/external/gpl3/gdb/dist/gdbserver/ |
| linux-aarch32-low.cc | 64 uint32_t cpsr = regs[ARM_CPSR_GREGNUM]; local
72 | (cpsr & 0x00f00000));
83 uint32_t cpsr = regs[ARM_CPSR_GREGNUM]; local
93 cpsr &= 0xff0fffff;
94 supply_register (regcache, ARM_PS_REGNUM, &cpsr);
174 unsigned long cpsr; local
176 collect_register_by_name (regcache, "cpsr", &cpsr);
178 if (cpsr & 0x20)
|
| linux-arm-low.cc | 929 uint32_t cpsr; local
941 /* Set IS_THUMB according the CPSR saved on the stack. */
942 the_target->read_memory (sp + pc_offset + 4, (unsigned char *) &cpsr, 4);
943 *is_thumb = ((cpsr & CPSR_T) != 0);
|
| /src/external/gpl3/gdb.old/dist/gdbserver/ |
| linux-aarch32-low.cc | 64 uint32_t cpsr = regs[ARM_CPSR_GREGNUM]; local
72 | (cpsr & 0x00f00000));
83 uint32_t cpsr = regs[ARM_CPSR_GREGNUM]; local
93 cpsr &= 0xff0fffff;
94 supply_register (regcache, ARM_PS_REGNUM, &cpsr);
174 unsigned long cpsr; local
176 collect_register_by_name (regcache, "cpsr", &cpsr);
178 if (cpsr & 0x20)
|
| linux-arm-low.cc | 888 uint32_t cpsr; local
900 /* Set IS_THUMB according the CPSR saved on the stack. */
901 the_target->read_memory (sp + pc_offset + 4, (unsigned char *) &cpsr, 4);
902 *is_thumb = ((cpsr & CPSR_T) != 0);
|
| /src/external/gpl3/gdb/dist/sim/arm/ |
| armos.c | 845 ARMword cpsr; local
848 cpsr = ARMul_GetCPSR (state);
851 ARMul_SetSPSR (state, SVC32MODE, cpsr);
853 cpsr &= ~0xbf;
854 cpsr |= SVC32MODE | 0x80;
855 ARMul_SetCPSR (state, cpsr);
|
| iwmmxt.c | 618 ARMword cpsr;
639 cpsr = ARMul_GetCPSR (state) & 0x0fffffff;
644 cpsr |= ( (wCBITS (wCASF, 28, 31) & wCBITS (wCASF, 24, 27)
651 cpsr |= ( (wCBITS (wCASF, 28, 31) & wCBITS (wCASF, 20, 23)
656 cpsr |= ((wCBITS (wCASF, 28, 31) & wCBITS (wCASF, 12, 15)) << 28);
664 ARMul_SetCPSR (state, cpsr);
718 ARMword cpsr;
741 cpsr = ARMul_GetCPSR (state) & 0x0fffffff;
754 cpsr |= wCBITS (wCASF, selector, selector + 3) << 28;
755 ARMul_SetCPSR (state, cpsr);
616 ARMword cpsr; local
716 ARMword cpsr; local
1177 ARMword cpsr = ARMul_GetCPSR (state); local
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/arm/ |
| armos.c | 845 ARMword cpsr; local
848 cpsr = ARMul_GetCPSR (state);
851 ARMul_SetSPSR (state, SVC32MODE, cpsr);
853 cpsr &= ~0xbf;
854 cpsr |= SVC32MODE | 0x80;
855 ARMul_SetCPSR (state, cpsr);
|
| iwmmxt.c | 618 ARMword cpsr;
639 cpsr = ARMul_GetCPSR (state) & 0x0fffffff;
644 cpsr |= ( (wCBITS (wCASF, 28, 31) & wCBITS (wCASF, 24, 27)
651 cpsr |= ( (wCBITS (wCASF, 28, 31) & wCBITS (wCASF, 20, 23)
656 cpsr |= ((wCBITS (wCASF, 28, 31) & wCBITS (wCASF, 12, 15)) << 28);
664 ARMul_SetCPSR (state, cpsr);
718 ARMword cpsr;
741 cpsr = ARMul_GetCPSR (state) & 0x0fffffff;
754 cpsr |= wCBITS (wCASF, selector, selector + 3) << 28;
755 ARMul_SetCPSR (state, cpsr);
616 ARMword cpsr; local
716 ARMword cpsr; local
1177 ARMword cpsr = ARMul_GetCPSR (state); local
[all...] |
| /src/sys/external/mit/xen-include-public/dist/xen/include/public/ |
| arch-arm.h | 256 uint32_t cpsr; /* SPSR_EL2 */ member in struct:vcpu_guest_core_regs
342 /* PSR bits (CPSR, SPSR) */
|
| vm_event.h | 209 uint32_t cpsr; member in struct:vm_event_regs_arm
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/BinaryFormat/ |
| MachO.h | 1808 uint32_t cpsr; member in struct:llvm::MachO::arm_thread_state32_t
1817 sys::swapByteOrder(x.cpsr);
1826 uint32_t cpsr; member in struct:llvm::MachO::arm_thread_state64_t
1837 sys::swapByteOrder(x.cpsr);
|
