1 /* $NetBSD: pxa2x0_apm.c,v 1.9 2022/10/31 21:22:05 andvar Exp $ */ 2 /* $OpenBSD: pxa2x0_apm.c,v 1.28 2007/03/29 18:42:38 uwe Exp $ */ 3 4 /*- 5 * Copyright (c) 2001 Alexander Guy. All rights reserved. 6 * Copyright (c) 1998-2001 Michael Shalayeff. All rights reserved. 7 * Copyright (c) 1995 John T. Kohl. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/kthread.h> 43 #include <sys/lock.h> 44 #include <sys/mount.h> /* for vfs_syncwait() */ 45 #include <sys/proc.h> 46 #include <sys/device.h> 47 #include <sys/fcntl.h> 48 #include <sys/ioctl.h> 49 #include <sys/event.h> 50 51 #include <machine/cpu.h> 52 #include <machine/apmvar.h> 53 54 #include <arm/xscale/pxa2x0reg.h> 55 #include <arm/xscale/pxa2x0var.h> 56 #include <arm/xscale/pxa2x0_apm.h> 57 #include <arm/xscale/pxa2x0_gpio.h> 58 59 #if defined(APMDEBUG) 60 #define DPRINTF(x) printf x 61 #else 62 #define DPRINTF(x) /**/ 63 #endif 64 65 #define APM_LOCK(sc) lockmgr(&(sc)->sc_lock, LK_EXCLUSIVE, NULL) 66 #define APM_UNLOCK(sc) lockmgr(&(sc)->sc_lock, LK_RELEASE, NULL) 67 68 #define APMUNIT(dev) (minor(dev)&0xf0) 69 #define APMDEV(dev) (minor(dev)&0x0f) 70 #define APMDEV_NORMAL 0 71 #define APMDEV_CTL 8 72 73 int apm_userstandbys; 74 int apm_suspends; 75 int apm_battlow; 76 77 extern struct cfdriver zapm_cd; 78 79 /* battery percentage at which we get verbose in our warnings. This 80 value can be changed using sysctl(8), value machdep.apmwarn. 81 Setting it to zero kills all warnings */ 82 int cpu_apmwarn = 10; 83 84 void apm_power_print(struct pxa2x0_apm_softc *, struct apm_power_info *); 85 void apm_power_info(struct pxa2x0_apm_softc *, struct apm_power_info *); 86 void apm_suspend(struct pxa2x0_apm_softc *); 87 void apm_resume(struct pxa2x0_apm_softc *); 88 int apm_get_event(struct pxa2x0_apm_softc *, u_int *); 89 int apm_handle_event(struct pxa2x0_apm_softc *, u_int); 90 void apm_thread_create(void *); 91 void apm_thread(void *); 92 93 #if 0 94 extern int perflevel; 95 #endif 96 97 int freq; 98 void pxa2x0_setperf(int speed); 99 int pxa2x0_cpuspeed(int *speed); 100 101 int apm_record_event(struct pxa2x0_apm_softc *, u_int); 102 #if 0 103 void filt_apmrdetach(struct knote *kn); 104 int filt_apmread(struct knote *kn, long hint); 105 int apmkqfilter(dev_t dev, struct knote *kn); 106 107 static const struct filterops apmread_filtops = { 108 .f_flags = FILTEROP_ISFD, 109 .f_attach = NULL, 110 .f_detach = filt_apmrdetach, 111 .f_event = filt_apmread, 112 }; 113 #endif 114 115 /* 116 * Flags to control kernel display 117 * SCFLAG_NOPRINT: do not output APM power messages due to 118 * a power change event. 119 * 120 * SCFLAG_PCTPRINT: do not output APM power messages due to 121 * to a power change event unless the battery 122 * percentage changes. 123 */ 124 125 #define SCFLAG_NOPRINT 0x0008000 126 #define SCFLAG_PCTPRINT 0x0004000 127 #define SCFLAG_PRINT (SCFLAG_NOPRINT|SCFLAG_PCTPRINT) 128 129 #define SCFLAG_OREAD (1 << 0) 130 #define SCFLAG_OWRITE (1 << 1) 131 #define SCFLAG_OPEN (SCFLAG_OREAD|SCFLAG_OWRITE) 132 133 /* This structure must be kept in sync with pxa2x0_apm_asm.S. */ 134 struct pxa2x0_memcfg { 135 /* SDRAM refresh */ 136 uint32_t mdrefr_high; /* 0x00 */ 137 uint32_t mdrefr_low; /* 0x04 */ 138 uint32_t mdrefr_low2; /* 0x08 */ 139 /* Synchronous, static, or VLIO interfaces */ 140 uint32_t msc_high[3]; /* 0x0c */ 141 uint32_t msc_low[3]; /* 0x18 */ 142 /* XXX move up */ 143 uint32_t mdrefr_91; /* 0x24 */ 144 }; 145 146 /* XXX */ 147 #define MDREFR_C3000 (MDREFR_K0DB2 | MDREFR_E1PIN | MDREFR_K1RUN | \ 148 MDREFR_K1DB2 | MDREFR_K2DB2 | MDREFR_APD) 149 #define MSC0_HIGH \ 150 ( 7 << MSC_RRR_SHIFT << 16) | \ 151 (15 << MSC_RDN_SHIFT << 16) | \ 152 (15 << MSC_RDF_SHIFT << 16) | \ 153 (MSC_RT_NONBURST << 16) | \ 154 ( 2 << MSC_RRR_SHIFT) | \ 155 (13 << MSC_RDN_SHIFT) | \ 156 (13 << MSC_RDF_SHIFT) | \ 157 MSC_RBW /* PXA271 */ | \ 158 MSC_RT_NONBURST 159 #define MSC1_HIGH \ 160 ( 7 << MSC_RRR_SHIFT << 16) | \ 161 (15 << MSC_RDN_SHIFT << 16) | \ 162 (15 << MSC_RDF_SHIFT << 16) | \ 163 (MSC_RT_VLIO << 16) | \ 164 ( 3 << MSC_RRR_SHIFT) | \ 165 ( 4 << MSC_RDN_SHIFT) | \ 166 (13 << MSC_RDF_SHIFT) | \ 167 MSC_RT_VLIO 168 #define MSC2_HIGH \ 169 ( 7 << MSC_RRR_SHIFT << 16) | \ 170 (15 << MSC_RDN_SHIFT << 16) | \ 171 (15 << MSC_RDF_SHIFT << 16) | \ 172 (MSC_RT_NONBURST << 16) | \ 173 ( 3 << MSC_RRR_SHIFT) | \ 174 ( 4 << MSC_RDN_SHIFT) | \ 175 (13 << MSC_RDF_SHIFT) | \ 176 MSC_RT_VLIO 177 #define MSC0_LOW \ 178 ( 7 << MSC_RRR_SHIFT << 16) | \ 179 (15 << MSC_RDN_SHIFT << 16) | \ 180 (15 << MSC_RDF_SHIFT << 16) | \ 181 (MSC_RT_NONBURST << 16) | \ 182 ( 1 << MSC_RRR_SHIFT) | \ 183 ( 8 << MSC_RDN_SHIFT) | \ 184 ( 8 << MSC_RDF_SHIFT) | \ 185 MSC_RBW /* PXA271 */ | \ 186 MSC_RT_NONBURST 187 #define MSC1_LOW \ 188 ( 7 << MSC_RRR_SHIFT << 16) | \ 189 (15 << MSC_RDN_SHIFT << 16) | \ 190 (15 << MSC_RDF_SHIFT << 16) | \ 191 (MSC_RT_VLIO << 16) | \ 192 ( 1 << MSC_RRR_SHIFT) | \ 193 ( 2 << MSC_RDN_SHIFT) | \ 194 ( 6 << MSC_RDF_SHIFT) | \ 195 MSC_RT_VLIO 196 #define MSC2_LOW \ 197 ( 7 << MSC_RRR_SHIFT << 16) | \ 198 (15 << MSC_RDN_SHIFT << 16) | \ 199 (15 << MSC_RDF_SHIFT << 16) | \ 200 (MSC_RT_NONBURST << 16) | \ 201 ( 1 << MSC_RRR_SHIFT) | \ 202 ( 2 << MSC_RDN_SHIFT) | \ 203 ( 6 << MSC_RDF_SHIFT) | \ 204 MSC_RT_VLIO 205 struct pxa2x0_memcfg pxa2x0_memcfg = { 206 (MDREFR_C3000 | 0x030), 207 (MDREFR_C3000 | 0x00b), 208 (MDREFR_C3000 | 0x017), 209 { MSC0_HIGH, MSC1_HIGH, MSC2_HIGH }, 210 { MSC1_LOW, MSC1_LOW, MSC2_LOW }, 211 (MDREFR_C3000 | 0x013) 212 }; 213 214 #define PI2C_RETRY_COUNT 10 215 /* XXX varies depending on voltage regulator IC. */ 216 #define PI2C_VOLTAGE_LOW 0x13 /* 1.00V */ 217 #define PI2C_VOLTAGE_HIGH 0x1a /* 1.35V */ 218 219 void pxa2x0_pi2c_open(bus_space_tag_t, bus_space_handle_t); 220 void pxa2x0_pi2c_close(bus_space_tag_t, bus_space_handle_t); 221 int pxa2x0_pi2c_read(bus_space_tag_t, bus_space_handle_t, u_char, u_char *); 222 int pxa2x0_pi2c_write(bus_space_tag_t, bus_space_handle_t, u_char, u_char); 223 int pxa2x0_pi2c_getvoltage(bus_space_tag_t, bus_space_handle_t, u_char *); 224 int pxa2x0_pi2c_setvoltage(bus_space_tag_t, bus_space_handle_t, u_char); 225 #if 0 226 void pxa2x0_pi2c_print(struct pxa2x0_apm_softc *); 227 #endif 228 229 /* XXX used in pxa2x0_apm_asm.S */ 230 bus_space_handle_t pxa2x0_gpio_ioh; 231 bus_space_handle_t pxa2x0_clkman_ioh; 232 bus_space_handle_t pxa2x0_memctl_ioh; 233 234 /* pxa2x0_apm_asm.S */ 235 void pxa27x_run_mode(void); 236 void pxa27x_fastbus_run_mode(int, uint32_t); 237 void pxa27x_frequency_change(int, int, struct pxa2x0_memcfg *); 238 void pxa2x0_cpu_suspend(void); 239 void pxa2x0_cpu_resume(void); 240 void pxa27x_cpu_speed_high(void); 241 void pxa27x_cpu_speed_low(void); 242 void pxa27x_cpu_speed_91(void); 243 void pxa27x_cpu_speed_208(void); 244 245 void 246 apm_power_print(struct pxa2x0_apm_softc *sc, struct apm_power_info *powerp) 247 { 248 249 if (powerp->battery_life != APM_BATT_LIFE_UNKNOWN) 250 printf("%s: battery life expectancy %d%%\n", 251 device_xname(sc->sc_dev), powerp->battery_life); 252 253 printf("%s: AC ", device_xname(sc->sc_dev)); 254 switch (powerp->ac_state) { 255 case APM_AC_OFF: 256 printf("off,"); 257 break; 258 case APM_AC_ON: 259 printf("on,"); 260 break; 261 case APM_AC_BACKUP: 262 printf("backup power,"); 263 break; 264 default: 265 case APM_AC_UNKNOWN: 266 printf("unknown,"); 267 break; 268 } 269 270 printf(" battery is "); 271 switch (powerp->battery_state) { 272 case APM_BATT_HIGH: 273 printf("high"); 274 break; 275 case APM_BATT_LOW: 276 printf("low"); 277 break; 278 case APM_BATT_CRITICAL: 279 printf("CRITICAL"); 280 break; 281 case APM_BATT_CHARGING: 282 printf("charging"); 283 break; 284 case APM_BATT_UNKNOWN: 285 printf("unknown"); 286 break; 287 default: 288 printf("undecoded (%x)", powerp->battery_state); 289 break; 290 } 291 292 printf("\n"); 293 } 294 295 void 296 apm_power_info(struct pxa2x0_apm_softc *sc, 297 struct apm_power_info *power) 298 { 299 300 power->ac_state = APM_AC_UNKNOWN; 301 power->battery_state = APM_BATT_UNKNOWN; 302 power->battery_life = 0 /* APM_BATT_LIFE_UNKNOWN */; 303 power->minutes_left = 0; 304 305 if (sc->sc_power_info != NULL) 306 sc->sc_power_info(sc, power); 307 } 308 309 void 310 apm_suspend(struct pxa2x0_apm_softc *sc) 311 { 312 313 resettodr(); 314 315 dopowerhooks(PWR_SUSPEND); 316 317 #if 0 318 if (cold) 319 vfs_syncwait(0); 320 #endif 321 322 if (sc->sc_suspend == NULL) 323 pxa2x0_wakeup_config(PXA2X0_WAKEUP_ALL, 1); 324 else 325 sc->sc_suspend(sc); 326 327 pxa2x0_apm_sleep(sc); 328 } 329 330 void 331 apm_resume(struct pxa2x0_apm_softc *sc) 332 { 333 334 dopowerhooks(PWR_RESUME); 335 336 inittodr(0); 337 338 /* 339 * Clear the OTG Peripheral hold after running the pxaudc and pxaohci 340 * powerhooks to re-enable their operation. See 3.8.1.2 341 */ 342 /* XXX ifdef NPXAUDC > 0 */ 343 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PSSR, PSSR_OTGPH); 344 } 345 346 #if 0 347 int 348 apm_get_event(struct pxa2x0_apm_softc *sc, u_int *typep) 349 { 350 351 if (sc->sc_get_event != NULL) 352 return (sc->sc_get_event(sc, typep)); 353 354 *typep = APM_NOEVENT; 355 return (1); 356 } 357 358 int 359 apm_handle_event(struct pxa2x0_apm_softc *sc, u_int type) 360 { 361 struct apm_power_info power; 362 int ret = 0; 363 364 switch (type) { 365 case APM_NOEVENT: 366 ret = 1; 367 break; 368 case APM_CRIT_SUSPEND_REQ: 369 DPRINTF(("suspend required immediately\n")); 370 #if 0 371 /* XXX apmd would make us suspend again after resume. */ 372 (void)apm_record_event(sc, type); 373 #endif 374 /* 375 * We ignore APM_CRIT_RESUME and just suspend here as usual 376 * to simplify the actual apm_get_event() implementation. 377 */ 378 apm_suspends++; 379 ret = 1; 380 break; 381 case APM_USER_SUSPEND_REQ: 382 case APM_SUSPEND_REQ: 383 DPRINTF(("suspend requested\n")); 384 if (apm_record_event(sc, type)) { 385 DPRINTF(("suspend ourselves\n")); 386 apm_suspends++; 387 } 388 break; 389 case APM_POWER_CHANGE: 390 DPRINTF(("power status change\n")); 391 apm_power_info(sc, &power); 392 if (power.battery_life != APM_BATT_LIFE_UNKNOWN && 393 power.battery_life < cpu_apmwarn && 394 (sc->sc_flags & SCFLAG_PRINT) != SCFLAG_NOPRINT && 395 ((sc->sc_flags & SCFLAG_PRINT) != SCFLAG_PCTPRINT || 396 sc->sc_batt_life != power.battery_life)) { 397 sc->sc_batt_life = power.battery_life; 398 apm_power_print(sc, &power); 399 } 400 apm_record_event(sc, type); 401 break; 402 case APM_BATTERY_LOW: 403 DPRINTF(("Battery low!\n")); 404 apm_battlow++; 405 apm_record_event(sc, type); 406 break; 407 default: 408 DPRINTF(("apm_handle_event: unsupported event, code %d\n", 409 type)); 410 } 411 412 return (ret); 413 } 414 415 void 416 apm_thread_create(void *v) 417 { 418 struct pxa2x0_apm_softc *sc = v; 419 420 if (kthread_create(apm_thread, sc, &sc->sc_thread, 421 "%s", device_xname(sc->sc_dev))) { 422 /* apm_disconnect(sc); */ 423 printf("%s: failed to create kernel thread, disabled", 424 device_xname(sc->sc_dev)); 425 } 426 } 427 428 void 429 apm_thread(void *v) 430 { 431 struct pxa2x0_apm_softc *sc = v; 432 u_int type; 433 434 for (;;) { 435 APM_LOCK(sc); 436 437 while (1) { 438 if (apm_get_event(sc, &type) != 0) 439 break; 440 if (apm_handle_event(sc, type) != 0) 441 break; 442 } 443 if (apm_suspends || apm_userstandbys /* || apm_battlow*/) { 444 apm_suspend(sc); 445 apm_resume(sc); 446 } 447 apm_battlow = apm_suspends = apm_userstandbys = 0; 448 449 APM_UNLOCK(sc); 450 kpause("apmev", false, hz, NULL); 451 } 452 } 453 454 int 455 apmopen(dev_t dev, int flag, int mode, struct proc *p) 456 { 457 struct pxa2x0_apm_softc *sc; 458 int error = 0; 459 460 /* apm0 only */ 461 if (!zapm_cd.cd_ndevs || APMUNIT(dev) != 0 || 462 !(sc = zapm_cd.cd_devs[APMUNIT(dev)])) 463 return (ENXIO); 464 465 DPRINTF(("apmopen: dev %d pid %d flag %x mode %x\n", 466 APMDEV(dev), p->p_pid, flag, mode)); 467 468 switch (APMDEV(dev)) { 469 case APMDEV_CTL: 470 if (!(flag & FWRITE)) { 471 error = EINVAL; 472 break; 473 } 474 if (sc->sc_flags & SCFLAG_OWRITE) { 475 error = EBUSY; 476 break; 477 } 478 sc->sc_flags |= SCFLAG_OWRITE; 479 break; 480 case APMDEV_NORMAL: 481 if (!(flag & FREAD) || (flag & FWRITE)) { 482 error = EINVAL; 483 break; 484 } 485 sc->sc_flags |= SCFLAG_OREAD; 486 break; 487 default: 488 error = ENXIO; 489 break; 490 } 491 return (error); 492 } 493 494 int 495 apmclose(dev_t dev, int flag, int mode, struct proc *p) 496 { 497 struct pxa2x0_apm_softc *sc; 498 499 /* apm0 only */ 500 if (!apm_cd.cd_ndevs || APMUNIT(dev) != 0 || 501 !(sc = apm_cd.cd_devs[APMUNIT(dev)])) 502 return (ENXIO); 503 504 DPRINTF(("apmclose: pid %d flag %x mode %x\n", p->p_pid, flag, mode)); 505 506 switch (APMDEV(dev)) { 507 case APMDEV_CTL: 508 sc->sc_flags &= ~SCFLAG_OWRITE; 509 break; 510 case APMDEV_NORMAL: 511 sc->sc_flags &= ~SCFLAG_OREAD; 512 break; 513 } 514 return (0); 515 } 516 517 int 518 apmioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 519 { 520 struct pxa2x0_apm_softc *sc; 521 struct apm_power_info *power; 522 int error = 0; 523 524 /* apm0 only */ 525 if (!apm_cd.cd_ndevs || APMUNIT(dev) != 0 || 526 !(sc = apm_cd.cd_devs[APMUNIT(dev)])) 527 return (ENXIO); 528 529 switch (cmd) { 530 /* some ioctl names from linux */ 531 case APM_IOC_STANDBY: 532 if ((flag & FWRITE) == 0) 533 error = EBADF; 534 else 535 apm_userstandbys++; 536 break; 537 case APM_IOC_SUSPEND: 538 if ((flag & FWRITE) == 0) 539 error = EBADF; 540 else 541 apm_suspends++; /* XXX */ 542 break; 543 case APM_IOC_PRN_CTL: 544 if ((flag & FWRITE) == 0) 545 error = EBADF; 546 else { 547 int flag = *(int *)data; 548 DPRINTF(( "APM_IOC_PRN_CTL: %d\n", flag )); 549 switch (flag) { 550 case APM_PRINT_ON: /* enable printing */ 551 sc->sc_flags &= ~SCFLAG_PRINT; 552 break; 553 case APM_PRINT_OFF: /* disable printing */ 554 sc->sc_flags &= ~SCFLAG_PRINT; 555 sc->sc_flags |= SCFLAG_NOPRINT; 556 break; 557 case APM_PRINT_PCT: /* disable some printing */ 558 sc->sc_flags &= ~SCFLAG_PRINT; 559 sc->sc_flags |= SCFLAG_PCTPRINT; 560 break; 561 default: 562 error = EINVAL; 563 break; 564 } 565 } 566 break; 567 case APM_IOC_DEV_CTL: 568 if ((flag & FWRITE) == 0) 569 error = EBADF; 570 break; 571 case APM_IOC_GETPOWER: 572 power = (struct apm_power_info *)data; 573 apm_power_info(sc, power); 574 break; 575 576 default: 577 error = ENOTTY; 578 } 579 580 return (error); 581 } 582 583 int 584 apm_record_event(struct pxa2x0_apm_softc *sc, u_int type) 585 { 586 static int apm_evindex; 587 588 /* skip if no user waiting */ 589 if ((sc->sc_flags & SCFLAG_OPEN) == 0) 590 return (1); 591 592 apm_evindex++; 593 KNOTE(&sc->sc_note, APM_EVENT_COMPOSE(type, apm_evindex)); 594 595 return (0); 596 } 597 598 void 599 filt_apmrdetach(struct knote *kn) 600 { 601 struct pxa2x0_apm_softc *sc = 602 (struct pxa2x0_apm_softc *)kn->kn_hook; 603 604 klist_remove(&sc->sc_note, kn); 605 } 606 607 int 608 filt_apmread(struct knote *kn, long hint) 609 { 610 /* XXX weird kqueue_scan() semantics */ 611 if (hint && !kn->kn_data) 612 kn->kn_data = (int)hint; 613 614 return (1); 615 } 616 617 int 618 apmkqfilter(dev_t dev, struct knote *kn) 619 { 620 struct pxa2x0_apm_softc *sc; 621 622 /* apm0 only */ 623 if (!apm_cd.cd_ndevs || APMUNIT(dev) != 0 || 624 !(sc = apm_cd.cd_devs[APMUNIT(dev)])) 625 return (ENXIO); 626 627 switch (kn->kn_filter) { 628 case EVFILT_READ: 629 kn->kn_fop = &apmread_filtops; 630 break; 631 default: 632 return (EINVAL); 633 } 634 635 kn->kn_hook = (caddr_t)sc; 636 klist_insert(&sc->sc_note, kn); 637 638 return (0); 639 } 640 641 void 642 pxa2x0_apm_attach_sub(struct pxa2x0_apm_softc *sc) 643 { 644 645 sc->sc_iot = &pxa2x0_bs_tag; 646 647 if (bus_space_map(sc->sc_iot, PXA2X0_POWMAN_BASE, 648 PXA2X0_POWMAN_SIZE, 0, &sc->sc_pm_ioh)) { 649 printf("pxa2x0_apm_attach_sub: failed to map POWMAN\n"); 650 return; 651 } 652 653 lockinit(&sc->sc_lock, PWAIT, "apmlk", 0, 0); 654 klist_init(&sc->sc_note); 655 656 kthread_create_deferred(apm_thread_create, sc); 657 658 printf("\n"); 659 660 if (bus_space_map(sc->sc_iot, PXA2X0_CLKMAN_BASE, PXA2X0_CLKMAN_SIZE, 661 0, &pxa2x0_clkman_ioh)) { 662 printf("%s: failed to map CLKMAN\n", device_xname(sc->sc_dev)); 663 return; 664 } 665 666 if (bus_space_map(sc->sc_iot, PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 667 0, &pxa2x0_memctl_ioh)) { 668 printf("%s: failed to map MEMCTL\n", device_xname(sc->sc_dev)); 669 return; 670 } 671 sc->sc_memctl_ioh = pxa2x0_memctl_ioh; 672 673 if (bus_space_map(sc->sc_iot, PXA2X0_GPIO_BASE, PXA2X0_GPIO_SIZE, 674 0, &pxa2x0_gpio_ioh)) { 675 printf("%s: can't map GPIO\n", device_xname(sc->sc_dev)); 676 return; 677 } 678 679 /* Clear all reset status flags. */ 680 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_RCSR, 681 RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR); 682 } 683 #endif /* 0 */ 684 685 void 686 pxa2x0_wakeup_config(u_int wsrc, int enable) 687 { 688 struct pxa2x0_apm_softc *sc; 689 uint32_t prer; 690 uint32_t pfer; 691 uint32_t pkwr; 692 693 if (zapm_cd.cd_ndevs < 1 || zapm_cd.cd_devs[0] == NULL) 694 return; 695 sc = device_private(zapm_cd.cd_devs[0]); 696 697 prer = pfer = pkwr = 0; 698 699 if ((wsrc & PXA2X0_WAKEUP_POWERON) != 0) { 700 prer |= (1<<0); 701 pfer |= (1<<0); 702 pkwr |= (1<<12); /* XXX */ 703 } 704 705 if ((wsrc & PXA2X0_WAKEUP_GPIORST) != 0) 706 pfer |= (1<<1); 707 if ((wsrc & PXA2X0_WAKEUP_SD) != 0) 708 prer |= (1<<9); 709 if ((wsrc & PXA2X0_WAKEUP_RC) != 0) 710 prer |= (1<<13); 711 if ((wsrc & PXA2X0_WAKEUP_SYNC) != 0) 712 pkwr |= (1<<1); 713 if ((wsrc & PXA2X0_WAKEUP_KEYNS0) != 0) 714 prer |= (1<<12); 715 if ((wsrc & PXA2X0_WAKEUP_KEYNS1) != 0) 716 pkwr |= (1<<2); 717 if ((wsrc & PXA2X0_WAKEUP_KEYNS2) != 0) 718 pkwr |= (1<<9); 719 if ((wsrc & PXA2X0_WAKEUP_KEYNS3) != 0) 720 pkwr |= (1<<3); 721 if ((wsrc & PXA2X0_WAKEUP_KEYNS4) != 0) 722 pkwr |= (1<<4); 723 if ((wsrc & PXA2X0_WAKEUP_KEYNS5) != 0) 724 pkwr |= (1<<6); 725 if ((wsrc & PXA2X0_WAKEUP_KEYNS6) != 0) 726 pkwr |= (1<<7); 727 if ((wsrc & PXA2X0_WAKEUP_CF0) != 0) 728 pkwr |= (1<<11); 729 if ((wsrc & PXA2X0_WAKEUP_CF1) != 0) 730 pkwr |= (1<<10); 731 if ((wsrc & PXA2X0_WAKEUP_USBD) != 0) 732 prer |= (1<<24); 733 734 if ((wsrc & PXA2X0_WAKEUP_LOCKSW) != 0) { 735 prer |= (1<<15); 736 pfer |= (1<<15); 737 } 738 739 if ((wsrc & PXA2X0_WAKEUP_JACKIN) != 0) { 740 prer |= (1<<23); 741 pfer |= (1<<23); 742 } 743 744 if ((wsrc & PXA2X0_WAKEUP_CHRGFULL) != 0) 745 pkwr |= (1<<18); 746 if ((wsrc & PXA2X0_WAKEUP_RTC) != 0) 747 prer |= (1<<31); 748 749 if (enable) { 750 sc->sc_wakeon |= wsrc; 751 prer |= bus_space_read_4(sc->sc_iot, sc->sc_pm_ioh, 752 POWMAN_PRER); 753 pfer |= bus_space_read_4(sc->sc_iot, sc->sc_pm_ioh, 754 POWMAN_PFER); 755 pkwr |= bus_space_read_4(sc->sc_iot, sc->sc_pm_ioh, 756 POWMAN_PKWR); 757 } else { 758 sc->sc_wakeon &= ~wsrc; 759 prer = bus_space_read_4(sc->sc_iot, sc->sc_pm_ioh, 760 POWMAN_PRER) & ~prer; 761 pfer = bus_space_read_4(sc->sc_iot, sc->sc_pm_ioh, 762 POWMAN_PFER) & ~pfer; 763 pkwr = bus_space_read_4(sc->sc_iot, sc->sc_pm_ioh, 764 POWMAN_PKWR) & ~pkwr; 765 } 766 767 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PKWR, pkwr); 768 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PRER, prer); 769 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PFER, pfer); 770 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PWER, 771 prer | pfer); 772 } 773 774 u_int 775 pxa2x0_wakeup_status(void) 776 { 777 struct pxa2x0_apm_softc *sc; 778 uint32_t rv; 779 u_int wsrc; 780 781 if (zapm_cd.cd_ndevs < 1 || zapm_cd.cd_devs[0] == NULL) 782 return (0); 783 784 sc = device_private(zapm_cd.cd_devs[0]); 785 wsrc = 0; 786 787 rv = bus_space_read_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PEDR); 788 if ((rv & (1<<0)) != 0) 789 wsrc |= PXA2X0_WAKEUP_POWERON; 790 if ((rv & (1<<1)) != 0) 791 wsrc |= PXA2X0_WAKEUP_GPIORST; 792 if ((rv & (1<<9)) != 0) 793 wsrc |= PXA2X0_WAKEUP_SD; 794 if ((rv & (1<<12)) != 0) 795 wsrc |= PXA2X0_WAKEUP_KEYNS0; 796 if ((rv & (1<<13)) != 0) 797 wsrc |= PXA2X0_WAKEUP_RC; 798 if ((rv & (1<<15)) != 0) 799 wsrc |= PXA2X0_WAKEUP_LOCKSW; 800 if ((rv & (1<<23)) != 0) 801 wsrc |= PXA2X0_WAKEUP_JACKIN; 802 if ((rv & (1<<24)) != 0) 803 wsrc |= PXA2X0_WAKEUP_USBD; 804 if ((rv & (1<<31)) != 0) 805 wsrc |= PXA2X0_WAKEUP_RTC; 806 807 rv = bus_space_read_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PKSR); 808 if ((rv & (1<<1)) != 0) 809 wsrc |= PXA2X0_WAKEUP_SYNC; 810 if ((rv & (1<<2)) != 0) 811 wsrc |= PXA2X0_WAKEUP_KEYNS1; 812 if ((rv & (1<<9)) != 0) 813 wsrc |= PXA2X0_WAKEUP_KEYNS2; 814 if ((rv & (1<<3)) != 0) 815 wsrc |= PXA2X0_WAKEUP_KEYNS3; 816 if ((rv & (1<<4)) != 0) 817 wsrc |= PXA2X0_WAKEUP_KEYNS4; 818 if ((rv & (1<<6)) != 0) 819 wsrc |= PXA2X0_WAKEUP_KEYNS5; 820 if ((rv & (1<<7)) != 0) 821 wsrc |= PXA2X0_WAKEUP_KEYNS6; 822 if ((rv & (1<<10)) != 0) 823 wsrc |= PXA2X0_WAKEUP_CF1; 824 if ((rv & (1<<11)) != 0) 825 wsrc |= PXA2X0_WAKEUP_CF0; 826 if ((rv & (1<<12)) != 0) 827 wsrc |= PXA2X0_WAKEUP_POWERON; 828 if ((rv & (1<<18)) != 0) 829 wsrc |= PXA2X0_WAKEUP_CHRGFULL; 830 831 return (wsrc); 832 } 833 834 struct pxa2x0_sleep_data { 835 /* OS timer registers */ 836 uint32_t sd_osmr0, sd_osmr1, sd_osmr2, sd_osmr3; 837 uint32_t sd_oscr0; 838 uint32_t sd_osmr4, sd_osmr5; 839 uint32_t sd_oscr4; 840 uint32_t sd_omcr4, sd_omcr5; 841 uint32_t sd_oier; 842 /* GPIO registers */ 843 uint32_t sd_gpdr0, sd_gpdr1, sd_gpdr2, sd_gpdr3; 844 uint32_t sd_grer0, sd_grer1, sd_grer2, sd_grer3; 845 uint32_t sd_gfer0, sd_gfer1, sd_gfer2, sd_gfer3; 846 uint32_t sd_gafr0_l, sd_gafr1_l, sd_gafr2_l, sd_gafr3_l; 847 uint32_t sd_gafr0_u, sd_gafr1_u, sd_gafr2_u, sd_gafr3_u; 848 uint32_t sd_gplr0, sd_gplr1, sd_gplr2, sd_gplr3; 849 /* Interrupt controller registers */ 850 uint32_t sd_iclr; 851 uint32_t sd_icmr; 852 uint32_t sd_iccr; 853 /* Memory controller registers */ 854 uint32_t sd_mecr; 855 uint32_t sd_mcmem0, sd_mcmem1; 856 uint32_t sd_mcatt0, sd_mcatt1; 857 uint32_t sd_mcio0, sd_mcio1; 858 /* Clocks manager registers */ 859 uint32_t sd_cken; 860 }; 861 862 void 863 pxa2x0_apm_sleep(struct pxa2x0_apm_softc *sc) 864 { 865 struct pxa2x0_sleep_data sd; 866 bus_space_handle_t ost_ioh; 867 int save; 868 uint32_t rv; 869 870 ost_ioh = (bus_space_handle_t)0; 871 if (bus_space_map(sc->sc_iot, PXA2X0_OST_BASE, PXA2X0_OST_SIZE, 0, 872 &ost_ioh)) { 873 printf("pxa2x0_apm_sleep: can't map OST\n"); 874 goto out; 875 } 876 877 save = disable_interrupts(I32_bit|F32_bit); 878 879 sd.sd_oscr0 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSCR0); 880 sd.sd_oscr4 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSCR4); 881 sd.sd_omcr4 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OMCR4); 882 sd.sd_omcr5 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OMCR5); 883 sd.sd_osmr0 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSMR0); 884 sd.sd_osmr1 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSMR1); 885 sd.sd_osmr2 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSMR2); 886 sd.sd_osmr3 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSMR3); 887 sd.sd_osmr4 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSMR4); 888 sd.sd_osmr5 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSMR5); 889 sd.sd_oier = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OIER); 890 891 /* Bring the PXA27x into 416MHz turbo mode. */ 892 if ((cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA27X && 893 bus_space_read_4(sc->sc_iot, pxa2x0_clkman_ioh, CLKMAN_CCCR) != 894 (CCCR_A | CCCR_TURBO_X2 | CCCR_RUN_X16)) { 895 #if 0 896 pxa27x_cpu_speed_high(); 897 #else 898 #define CLKCFG_T (1<<0) /* turbo */ 899 #define CLKCFG_F (1<<1) /* frequency change */ 900 #define CLKCFG_B (1<<3) /* fast-bus */ 901 pxa27x_frequency_change(CCCR_A | CCCR_TURBO_X2 | 902 CCCR_RUN_X16, CLKCFG_B | CLKCFG_F | CLKCFG_T, 903 &pxa2x0_memcfg); 904 #endif 905 delay(500000); /* XXX */ 906 } 907 908 suspend_again: 909 /* Clear wake-up status. */ 910 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PEDR, 911 0xffffffff); 912 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PKSR, 913 0xffffffff); 914 915 /* XXX control battery charging in sleep mode. */ 916 917 /* XXX schedule RTC alarm to check the battery, or schedule 918 XXX wake-up shortly before an already programmed alarm? */ 919 920 pxa27x_run_mode(); 921 #define MDREFR_LOW (MDREFR_C3000 | 0x00b) 922 pxa27x_fastbus_run_mode(0, MDREFR_LOW); 923 delay(1); 924 #if 1 925 pxa27x_cpu_speed_91(); 926 #else 927 pxa27x_frequency_change(CCCR_TURBO_X1 | CCCR_RUN_X7, CLKCFG_F, 928 &pxa2x0_memcfg); 929 #endif 930 pxa2x0_pi2c_setvoltage(sc->sc_iot, sc->sc_pm_ioh, PI2C_VOLTAGE_LOW); 931 932 sd.sd_gpdr0 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR0); 933 sd.sd_gpdr1 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR1); 934 sd.sd_gpdr2 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR2); 935 sd.sd_gpdr3 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR3); 936 937 sd.sd_grer0 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER0); 938 sd.sd_grer1 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER1); 939 sd.sd_grer2 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER2); 940 sd.sd_grer3 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER3); 941 942 sd.sd_gfer0 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER0); 943 sd.sd_gfer1 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER1); 944 sd.sd_gfer2 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER2); 945 sd.sd_gfer3 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER3); 946 947 sd.sd_gafr0_l = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR0_L); 948 sd.sd_gafr1_l = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR1_L); 949 sd.sd_gafr2_l = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR2_L); 950 sd.sd_gafr3_l = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR3_L); 951 952 sd.sd_gafr0_u = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR0_U); 953 sd.sd_gafr1_u = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR1_U); 954 sd.sd_gafr2_u = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR2_U); 955 sd.sd_gafr3_u = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR3_U); 956 957 sd.sd_gplr0 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPLR0); 958 sd.sd_gplr1 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPLR1); 959 sd.sd_gplr2 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPLR2); 960 sd.sd_gplr3 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPLR3); 961 962 sd.sd_iclr = read_icu(INTCTL_ICLR); 963 sd.sd_icmr = read_icu(INTCTL_ICMR); 964 sd.sd_iccr = read_icu(INTCTL_ICCR); 965 write_icu(INTCTL_ICMR, 0); 966 967 sd.sd_mecr = bus_space_read_4(sc->sc_iot, pxa2x0_memctl_ioh, 968 MEMCTL_MECR); 969 sd.sd_mcmem0 = bus_space_read_4(sc->sc_iot, pxa2x0_memctl_ioh, 970 MEMCTL_MCMEM(0)); 971 sd.sd_mcmem1 = bus_space_read_4(sc->sc_iot, pxa2x0_memctl_ioh, 972 MEMCTL_MCMEM(1)); 973 sd.sd_mcatt0 = bus_space_read_4(sc->sc_iot, pxa2x0_memctl_ioh, 974 MEMCTL_MCATT(0)); 975 sd.sd_mcatt1 = bus_space_read_4(sc->sc_iot, pxa2x0_memctl_ioh, 976 MEMCTL_MCATT(1)); 977 sd.sd_mcio0 = bus_space_read_4(sc->sc_iot, pxa2x0_memctl_ioh, 978 MEMCTL_MCIO(0)); 979 sd.sd_mcio1 = bus_space_read_4(sc->sc_iot, pxa2x0_memctl_ioh, 980 MEMCTL_MCIO(1)); 981 982 sd.sd_cken = bus_space_read_4(sc->sc_iot, pxa2x0_clkman_ioh, 983 CLKMAN_CKEN); 984 985 /* 986 * Stop clocks to all units except to the memory controller, and 987 * to the keypad controller if it is enabled as a wake-up source. 988 */ 989 rv = CKEN_MEM; 990 if ((sc->sc_wakeon & PXA2X0_WAKEUP_KEYNS_ALL) != 0) 991 rv |= CKEN_KEY; 992 bus_space_write_4(sc->sc_iot, pxa2x0_clkman_ioh, CLKMAN_CKEN, rv); 993 994 /* Disable nRESET_OUT. */ 995 rv = bus_space_read_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PSLR); 996 #define PSLR_SL_ROD (1<<20) 997 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PSLR, 998 rv | PSLR_SL_ROD); 999 1000 /* Clear all reset status flags. */ 1001 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_RCSR, 1002 RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR); 1003 1004 /* Stop 3/13MHz oscillator; do not float PCMCIA and chip-selects. */ 1005 rv = PCFR_OPDE; 1006 if ((cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA27X) 1007 /* Enable nRESET_GPIO as a GPIO reset input. */ 1008 rv |= PCFR_GPR_EN; 1009 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PCFR, rv); 1010 1011 /* XXX C3000 */ 1012 #define GPIO_G0_STROBE_BIT 0x0f800000 1013 #define GPIO_G1_STROBE_BIT 0x00100000 1014 #define GPIO_G2_STROBE_BIT 0x01000000 1015 #define GPIO_G3_STROBE_BIT 0x00041880 1016 #define GPIO_KEY_STROBE0 88 1017 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR0, 1018 0x00144018); 1019 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR1, 1020 0x00ef0000); 1021 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR2, 1022 0x0121c000); 1023 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR3, 1024 0x00600000); 1025 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR0, 1026 0x00144018 & ~GPIO_G0_STROBE_BIT); 1027 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR1, 1028 0x00ef0000 & ~GPIO_G1_STROBE_BIT); 1029 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR2, 1030 0x0121c000 & ~GPIO_G2_STROBE_BIT); 1031 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR3, 1032 0x00600000 & ~GPIO_G3_STROBE_BIT); 1033 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR2, 1034 (0x0121c000 & ~GPIO_G2_STROBE_BIT) | 1035 GPIO_BIT(GPIO_KEY_STROBE0)); 1036 1037 /* C3000 */ 1038 #define GPIO_EXT_BUS_READY 18 1039 pxa2x0_gpio_set_function(GPIO_EXT_BUS_READY, GPIO_SET | GPIO_OUT); 1040 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR0, 0xd01c4418); 1041 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR1, 0xfcefbd21); 1042 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR2, 0x13a5ffff); 1043 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR3, 0x01e3e10c); 1044 1045 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PSPR, 1046 (uint32_t)&pxa2x0_cpu_resume - 0xc0200000 + 0xa0200000); 1047 1048 pxa2x0_cpu_suspend(); 1049 1050 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PSPR, 0); 1051 1052 pxa2x0_clkman_config(CKEN_SSP|CKEN_PWM0|CKEN_PWM1, 1); 1053 pxa2x0_clkman_config(CKEN_KEY, 0); 1054 1055 #if 1 1056 /* Clear all GPIO interrupt sources. */ 1057 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GEDR0, 0xffffffff); 1058 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GEDR1, 0xffffffff); 1059 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GEDR2, 0xffffffff); 1060 #endif 1061 1062 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR0, sd.sd_gpdr0); 1063 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR1, sd.sd_gpdr1); 1064 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR2, sd.sd_gpdr2); 1065 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER0, sd.sd_grer0); 1066 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER1, sd.sd_grer1); 1067 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER2, sd.sd_grer2); 1068 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER0, sd.sd_gfer0); 1069 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER1, sd.sd_gfer1); 1070 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER2, sd.sd_gfer2); 1071 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR0_L, sd.sd_gafr0_l); 1072 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR1_L, sd.sd_gafr1_l); 1073 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR2_L, sd.sd_gafr2_l); 1074 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR0_U, sd.sd_gafr0_u); 1075 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR1_U, sd.sd_gafr1_u); 1076 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR2_U, sd.sd_gafr2_u); 1077 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPSR0, sd.sd_gplr0 & 1078 sd.sd_gpdr0); 1079 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPSR1, sd.sd_gplr1 & 1080 sd.sd_gpdr1); 1081 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPSR2, sd.sd_gplr2 & 1082 sd.sd_gpdr2); 1083 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPCR0, ~sd.sd_gplr0 & 1084 sd.sd_gpdr0); 1085 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPCR1, ~sd.sd_gplr1 & 1086 sd.sd_gpdr1); 1087 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPCR2, ~sd.sd_gplr2 & 1088 sd.sd_gpdr2); 1089 1090 /* PXA27x */ 1091 #if 0 1092 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GEDR3, 0xffffffff); 1093 #endif 1094 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR3, sd.sd_gpdr3); 1095 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER3, sd.sd_grer3); 1096 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER3, sd.sd_gfer3); 1097 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR3_L, sd.sd_gafr3_l); 1098 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR3_U, sd.sd_gafr3_u); 1099 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPSR3, sd.sd_gplr3 & 1100 sd.sd_gpdr3); 1101 bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPCR3, ~sd.sd_gplr3 & 1102 sd.sd_gpdr3); 1103 1104 bus_space_write_4(sc->sc_iot, pxa2x0_memctl_ioh, MEMCTL_MECR, 1105 sd.sd_mecr); 1106 bus_space_write_4(sc->sc_iot, pxa2x0_memctl_ioh, MEMCTL_MCMEM(0), 1107 sd.sd_mcmem0); 1108 bus_space_write_4(sc->sc_iot, pxa2x0_memctl_ioh, MEMCTL_MCMEM(1), 1109 sd.sd_mcmem1); 1110 bus_space_write_4(sc->sc_iot, pxa2x0_memctl_ioh, MEMCTL_MCATT(0), 1111 sd.sd_mcatt0); 1112 bus_space_write_4(sc->sc_iot, pxa2x0_memctl_ioh, MEMCTL_MCATT(1), 1113 sd.sd_mcatt1); 1114 bus_space_write_4(sc->sc_iot, pxa2x0_memctl_ioh, MEMCTL_MCIO(0), 1115 sd.sd_mcio0); 1116 bus_space_write_4(sc->sc_iot, pxa2x0_memctl_ioh, MEMCTL_MCIO(1), 1117 sd.sd_mcio1); 1118 1119 bus_space_write_4(sc->sc_iot, pxa2x0_clkman_ioh, CLKMAN_CKEN, 1120 sd.sd_cken); 1121 1122 write_icu(INTCTL_ICLR, sd.sd_iclr); 1123 write_icu(INTCTL_ICCR, sd.sd_iccr); 1124 write_icu(INTCTL_ICMR, sd.sd_icmr); 1125 1126 if ((read_icu(INTCTL_ICIP) & 0x1) != 0) 1127 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PEDR, 0x1); 1128 1129 bus_space_write_4(sc->sc_iot, ost_ioh, OST_OSMR0, sd.sd_osmr0); 1130 bus_space_write_4(sc->sc_iot, ost_ioh, OST_OSMR1, sd.sd_osmr1); 1131 bus_space_write_4(sc->sc_iot, ost_ioh, OST_OSMR2, sd.sd_osmr2); 1132 bus_space_write_4(sc->sc_iot, ost_ioh, OST_OSMR3, sd.sd_osmr3); 1133 bus_space_write_4(sc->sc_iot, ost_ioh, OST_OSMR4, sd.sd_osmr4); 1134 bus_space_write_4(sc->sc_iot, ost_ioh, OST_OSMR5, sd.sd_osmr5); 1135 bus_space_write_4(sc->sc_iot, ost_ioh, OST_OMCR4, sd.sd_omcr4); 1136 bus_space_write_4(sc->sc_iot, ost_ioh, OST_OMCR5, sd.sd_omcr5); 1137 bus_space_write_4(sc->sc_iot, ost_ioh, OST_OSCR0, sd.sd_oscr0); 1138 bus_space_write_4(sc->sc_iot, ost_ioh, OST_OSCR4, sd.sd_oscr4); 1139 bus_space_write_4(sc->sc_iot, ost_ioh, OST_OIER, sd.sd_oier); 1140 1141 pxa2x0_pi2c_setvoltage(sc->sc_iot, sc->sc_pm_ioh, PI2C_VOLTAGE_HIGH); 1142 1143 /* Change to 208MHz run mode with fast-bus still disabled. */ 1144 pxa27x_frequency_change(CCCR_A | CCCR_TURBO_X2 | CCCR_RUN_X16, 1145 CLKCFG_F, &pxa2x0_memcfg); 1146 delay(1); /* XXX is the delay long enough, and necessary at all? */ 1147 pxa27x_fastbus_run_mode(1, pxa2x0_memcfg.mdrefr_high); 1148 1149 /* Change to 416MHz turbo mode with fast-bus enabled. */ 1150 pxa27x_frequency_change(CCCR_A | CCCR_TURBO_X2 | CCCR_RUN_X16, 1151 CLKCFG_B | CLKCFG_F | CLKCFG_T, &pxa2x0_memcfg); 1152 1153 if (sc->sc_resume != NULL) { 1154 if (!sc->sc_resume(sc)) 1155 goto suspend_again; 1156 } 1157 1158 /* 1159 * Allow immediate entry into deep-sleep mode if power fails. 1160 * Resume from immediate deep-sleep is not implemented yet. 1161 */ 1162 bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PMCR, 0); 1163 1164 1165 restore_interrupts(save); 1166 1167 #if 0 1168 pxa2x0_setperf(perflevel); 1169 #endif 1170 1171 out: 1172 if (ost_ioh != (bus_space_handle_t)0) 1173 bus_space_unmap(sc->sc_iot, ost_ioh, PXA2X0_OST_SIZE); 1174 } 1175 1176 void 1177 pxa2x0_pi2c_open(bus_space_tag_t iot, bus_space_handle_t ioh) 1178 { 1179 uint32_t rv; 1180 1181 /* Enable the I2C unit, and disable automatic voltage change. */ 1182 rv = bus_space_read_4(iot, ioh, POWMAN_PCFR); 1183 bus_space_write_4(iot, ioh, POWMAN_PCFR, rv | PCFR_PI2C_EN); 1184 rv = bus_space_read_4(iot, ioh, POWMAN_PCFR); 1185 bus_space_write_4(iot, ioh, POWMAN_PCFR, rv & ~PCFR_FVC); 1186 delay(1); 1187 1188 /* Enable the clock to the power manager I2C unit. */ 1189 pxa2x0_clkman_config(CKEN_PI2C, 1); 1190 delay(1); 1191 } 1192 1193 void 1194 pxa2x0_pi2c_close(bus_space_tag_t iot, bus_space_handle_t ioh) 1195 { 1196 uint32_t rv; 1197 1198 bus_space_write_4(iot, ioh, POWMAN_PICR, PICR_UR); 1199 bus_space_write_4(iot, ioh, POWMAN_PISAR, 0); 1200 delay(1); 1201 1202 /* Disable the clock to the power manager I2C unit. */ 1203 pxa2x0_clkman_config(CKEN_PI2C, 0); 1204 delay(1); 1205 1206 /* Disable the I2C unit, and disable automatic voltage change. */ 1207 rv = bus_space_read_4(iot, ioh, POWMAN_PCFR); 1208 bus_space_write_4(iot, ioh, POWMAN_PCFR, 1209 rv & ~(PCFR_PI2C_EN | PCFR_FVC)); 1210 delay(1); 1211 } 1212 1213 int 1214 pxa2x0_pi2c_read(bus_space_tag_t iot, bus_space_handle_t ioh, 1215 u_char slave, u_char *valuep) 1216 { 1217 uint32_t rv; 1218 int timeout; 1219 int tries = PI2C_RETRY_COUNT; 1220 1221 retry: 1222 1223 bus_space_write_4(iot, ioh, POWMAN_PICR, PICR_UR); 1224 bus_space_write_4(iot, ioh, POWMAN_PISAR, 0x00); 1225 delay(1); 1226 bus_space_write_4(iot, ioh, POWMAN_PICR, PICR_IUE | PICR_SCLE); 1227 1228 /* Write slave device address. */ 1229 bus_space_write_4(iot, ioh, POWMAN_PIDBR, (slave<<1) | 0x1); 1230 rv = bus_space_read_4(iot, ioh, POWMAN_PICR); 1231 bus_space_write_4(iot, ioh, POWMAN_PICR, rv | PICR_START); 1232 rv = bus_space_read_4(iot, ioh, POWMAN_PICR); 1233 bus_space_write_4(iot, ioh, POWMAN_PICR, rv & ~PICR_STOP); 1234 rv = bus_space_read_4(iot, ioh, POWMAN_PICR); 1235 bus_space_write_4(iot, ioh, POWMAN_PICR, rv | PICR_TB); 1236 1237 timeout = 10000; 1238 while ((bus_space_read_4(iot, ioh, POWMAN_PISR) & PISR_ITE) == 0) { 1239 if (timeout-- == 0) { 1240 bus_space_write_4(iot, ioh, POWMAN_PISR, PISR_ITE); 1241 goto err; 1242 } 1243 delay(1); 1244 } 1245 1246 bus_space_write_4(iot, ioh, POWMAN_PISR, PISR_ITE); 1247 1248 rv = bus_space_read_4(iot, ioh, POWMAN_PICR); 1249 bus_space_write_4(iot, ioh, POWMAN_PICR, rv & ~PICR_START); 1250 1251 /* Read data value. */ 1252 rv = bus_space_read_4(iot, ioh, POWMAN_PICR); 1253 bus_space_write_4(iot, ioh, POWMAN_PICR, rv | 1254 (PICR_STOP | PICR_ACKNAK)); 1255 rv = bus_space_read_4(iot, ioh, POWMAN_PICR); 1256 bus_space_write_4(iot, ioh, POWMAN_PICR, rv | PICR_TB); 1257 1258 timeout = 10000; 1259 while ((bus_space_read_4(iot, ioh, POWMAN_PISR) & PISR_IRF) == 0) { 1260 if (timeout-- == 0) { 1261 bus_space_write_4(iot, ioh, POWMAN_PISR, PISR_IRF); 1262 goto err; 1263 } 1264 delay(1); 1265 } 1266 1267 bus_space_write_4(iot, ioh, POWMAN_PISR, PISR_IRF); 1268 rv = bus_space_read_4(iot, ioh, POWMAN_PIDBR); 1269 *valuep = (u_char)rv; 1270 rv = bus_space_read_4(iot, ioh, POWMAN_PICR); 1271 bus_space_write_4(iot, ioh, POWMAN_PICR, rv & 1272 ~(PICR_STOP | PICR_ACKNAK)); 1273 1274 return (0); 1275 err: 1276 if (tries-- >= 0) 1277 goto retry; 1278 1279 bus_space_write_4(iot, ioh, POWMAN_PICR, PICR_UR); 1280 bus_space_write_4(iot, ioh, POWMAN_PISAR, 0x00); 1281 bus_space_write_4(iot, ioh, POWMAN_PICR, PICR_IUE | PICR_SCLE); 1282 1283 return (-EIO); 1284 } 1285 1286 int 1287 pxa2x0_pi2c_write(bus_space_tag_t iot, bus_space_handle_t ioh, 1288 u_char slave, u_char value) 1289 { 1290 uint32_t rv; 1291 int timeout; 1292 int tries = PI2C_RETRY_COUNT; 1293 1294 retry: 1295 1296 bus_space_write_4(iot, ioh, POWMAN_PICR, PICR_UR); 1297 bus_space_write_4(iot, ioh, POWMAN_PISAR, 0x00); 1298 delay(1); 1299 bus_space_write_4(iot, ioh, POWMAN_PICR, PICR_IUE | PICR_SCLE); 1300 1301 /* Write slave device address. */ 1302 bus_space_write_4(iot, ioh, POWMAN_PIDBR, (slave<<1)); 1303 rv = bus_space_read_4(iot, ioh, POWMAN_PICR); 1304 bus_space_write_4(iot, ioh, POWMAN_PICR, rv | PICR_START); 1305 rv = bus_space_read_4(iot, ioh, POWMAN_PICR); 1306 bus_space_write_4(iot, ioh, POWMAN_PICR, rv & ~PICR_STOP); 1307 rv = bus_space_read_4(iot, ioh, POWMAN_PICR); 1308 bus_space_write_4(iot, ioh, POWMAN_PICR, rv | PICR_TB); 1309 1310 timeout = 10000; 1311 while ((bus_space_read_4(iot, ioh, POWMAN_PISR) & PISR_ITE) == 0) { 1312 if (timeout-- == 0) { 1313 bus_space_write_4(iot, ioh, POWMAN_PISR, PISR_ITE); 1314 goto err; 1315 } 1316 delay(1); 1317 } 1318 if ((bus_space_read_4(iot, ioh, POWMAN_PISR) & PISR_ACKNAK) != 0) 1319 goto err; 1320 bus_space_write_4(iot, ioh, POWMAN_PISR, PISR_ITE); 1321 1322 /* Write data. */ 1323 rv = bus_space_read_4(iot, ioh, POWMAN_PICR); 1324 bus_space_write_4(iot, ioh, POWMAN_PICR, rv & ~PICR_START); 1325 rv = bus_space_read_4(iot, ioh, POWMAN_PICR); 1326 bus_space_write_4(iot, ioh, POWMAN_PICR, rv | PICR_STOP); 1327 bus_space_write_4(iot, ioh, POWMAN_PIDBR, value); 1328 rv = bus_space_read_4(iot, ioh, POWMAN_PICR); 1329 bus_space_write_4(iot, ioh, POWMAN_PICR, rv | PICR_TB); 1330 1331 timeout = 10000; 1332 while ((bus_space_read_4(iot, ioh, POWMAN_PISR) & PISR_ITE) == 0) { 1333 if (timeout-- == 0) { 1334 #if 0 1335 bus_space_write_4(iot, ioh, POWMAN_PISR, PISR_ITE); 1336 #endif 1337 goto err; 1338 } 1339 delay(1); 1340 } 1341 if ((bus_space_read_4(iot, ioh, POWMAN_PISR) & PISR_ACKNAK) != 0) 1342 goto err; 1343 bus_space_write_4(iot, ioh, POWMAN_PISR, PISR_ITE); 1344 1345 rv = bus_space_read_4(iot, ioh, POWMAN_PICR); 1346 bus_space_write_4(iot, ioh, POWMAN_PICR, rv & ~PICR_STOP); 1347 1348 return (0); 1349 err: 1350 bus_space_write_4(iot, ioh, POWMAN_PISR, PISR_ITE); 1351 if (tries-- >= 0) 1352 goto retry; 1353 1354 bus_space_write_4(iot, ioh, POWMAN_PICR, PICR_UR); 1355 bus_space_write_4(iot, ioh, POWMAN_PISAR, 0x00); 1356 bus_space_write_4(iot, ioh, POWMAN_PICR, PICR_IUE | PICR_SCLE); 1357 1358 return (-EIO); 1359 } 1360 1361 int 1362 pxa2x0_pi2c_getvoltage(bus_space_tag_t iot, bus_space_handle_t ioh, 1363 u_char *valuep) 1364 { 1365 int res; 1366 1367 pxa2x0_pi2c_open(iot, ioh); 1368 res = pxa2x0_pi2c_read(iot, ioh, 0x0c, valuep); 1369 pxa2x0_pi2c_close(iot, ioh); 1370 return (res); 1371 } 1372 1373 int 1374 pxa2x0_pi2c_setvoltage(bus_space_tag_t iot, bus_space_handle_t ioh, 1375 u_char value) 1376 { 1377 int res; 1378 1379 pxa2x0_pi2c_open(iot, ioh); 1380 res = pxa2x0_pi2c_write(iot, ioh, 0x0c, value); 1381 pxa2x0_pi2c_close(iot, ioh); 1382 return (res); 1383 } 1384 1385 #if 0 1386 void 1387 pxa2x0_pi2c_print(struct pxa2x0_apm_softc *sc) 1388 { 1389 u_char value = 0; 1390 1391 (void)pxa2x0_pi2c_getvoltage(sc->sc_iot, sc->sc_pm_ioh, &value); 1392 printf("xscale core voltage: %s\n", value == PI2C_VOLTAGE_HIGH ? 1393 "high" : (value == PI2C_VOLTAGE_LOW ? "low" : "unknown")); 1394 } 1395 #endif 1396 1397 struct { 1398 int maxspeed; 1399 int numspeeds; 1400 int hz [6]; 1401 int rate [6]; /* could this be simplified by not having 100% in table? */ 1402 } 1403 speedtables[] = { 1404 { 91, 1, { 91 }, { 100 }}, 1405 { 208, 2, { 91, 208}, {50, 100}}, 1406 { 416, 3, { 91, 208, 416}, {25, 50, 100}}, 1407 { 520, 4, { 91, 208, 416, 520}, {18, 40 ,80, 100}}, 1408 { 624, 5, { 91, 208, 416, 520, 624}, {15, 34, 67, 82, 100}}, 1409 { 0 } 1410 }; 1411 int xscale_maxspeed = 416; /* XXX */ 1412 1413 int speed_to_freq(int speed); 1414 1415 int 1416 speed_to_freq(int speed) 1417 { 1418 int i, j; 1419 int newspeed = 0; 1420 int numspeeds; 1421 for (i = 0; speedtables[i].maxspeed != 0; i++) { 1422 if (speedtables[i].maxspeed != xscale_maxspeed) 1423 continue; 1424 1425 if (speed <= speedtables[i].rate[0]) { 1426 return speedtables[i].hz[0]; 1427 1428 } 1429 numspeeds = speedtables[i].numspeeds; 1430 if (speed == speedtables[i].rate[numspeeds-1]) { 1431 return speedtables[i].hz[numspeeds-1]; 1432 } 1433 for (j = 1; j < numspeeds; j++) { 1434 if (speed < speedtables[i].rate[j]) { 1435 return speedtables[i].hz[j-1]; 1436 } 1437 } 1438 } 1439 return newspeed; 1440 } 1441 1442 1443 void 1444 pxa2x0_setperf(int speed) 1445 { 1446 struct pxa2x0_apm_softc *sc; 1447 int s; 1448 int newfreq; 1449 1450 sc = device_private(zapm_cd.cd_devs[0]); 1451 1452 newfreq = speed_to_freq(speed); 1453 1454 if (newfreq == 0) { 1455 printf("bogus new frequency 0 for rate %d maxclock %d\n", 1456 speed, xscale_maxspeed); 1457 } 1458 1459 DPRINTF(("setperf speed %d newfreq %d, maxfreq %d\n", 1460 speed, newfreq, xscale_maxspeed)); 1461 1462 s = disable_interrupts(I32_bit|F32_bit); 1463 1464 if (newfreq == 91) { 1465 if (freq > 91) { 1466 pxa27x_run_mode(); 1467 pxa27x_fastbus_run_mode(0, MDREFR_LOW); 1468 pxa27x_cpu_speed_91(); 1469 pxa2x0_pi2c_setvoltage(sc->sc_iot, sc->sc_pm_ioh, 1470 PI2C_VOLTAGE_LOW); 1471 freq = 91; 1472 } 1473 } else if (newfreq == 208) { 1474 if (freq < 208) 1475 pxa2x0_pi2c_setvoltage(sc->sc_iot, sc->sc_pm_ioh, 1476 PI2C_VOLTAGE_HIGH); 1477 if (freq != 208) { 1478 pxa27x_frequency_change(CCCR_A | CCCR_TURBO_X2 | 1479 CCCR_RUN_X16, CLKCFG_F, &pxa2x0_memcfg); 1480 pxa27x_fastbus_run_mode(1, pxa2x0_memcfg.mdrefr_high); 1481 freq = 208; 1482 } 1483 } else if (newfreq == 416) { 1484 if (freq < 208) { 1485 pxa2x0_pi2c_setvoltage(sc->sc_iot, sc->sc_pm_ioh, 1486 PI2C_VOLTAGE_HIGH); 1487 pxa27x_frequency_change(CCCR_A | CCCR_TURBO_X2 | 1488 CCCR_RUN_X16, CLKCFG_F, &pxa2x0_memcfg); 1489 pxa27x_fastbus_run_mode(1, pxa2x0_memcfg.mdrefr_high); 1490 } 1491 if (freq != 416) { 1492 pxa27x_frequency_change(CCCR_A | CCCR_TURBO_X2 | 1493 CCCR_RUN_X16, CLKCFG_B | CLKCFG_F | CLKCFG_T, 1494 &pxa2x0_memcfg); 1495 freq = 416; 1496 } 1497 } else if (newfreq == 520) { 1498 if (freq < 208) { 1499 pxa2x0_pi2c_setvoltage(sc->sc_iot, sc->sc_pm_ioh, 1500 PI2C_VOLTAGE_HIGH); 1501 pxa27x_frequency_change(CCCR_A | CCCR_TURBO_X2 | 1502 CCCR_RUN_X16, CLKCFG_F, &pxa2x0_memcfg); 1503 pxa27x_fastbus_run_mode(1, pxa2x0_memcfg.mdrefr_high); 1504 } 1505 if (freq != 520) { 1506 pxa27x_frequency_change(CCCR_A | CCCR_TURBO_X25 | 1507 CCCR_RUN_X16, CLKCFG_B | CLKCFG_F | CLKCFG_T, 1508 &pxa2x0_memcfg); 1509 freq = 520; 1510 } 1511 } else if (newfreq == 624) { 1512 if (freq < 208) { 1513 pxa2x0_pi2c_setvoltage(sc->sc_iot, sc->sc_pm_ioh, 1514 PI2C_VOLTAGE_HIGH); 1515 pxa27x_frequency_change(CCCR_A | CCCR_TURBO_X2 | 1516 CCCR_RUN_X16, CLKCFG_F, &pxa2x0_memcfg); 1517 pxa27x_fastbus_run_mode(1, pxa2x0_memcfg.mdrefr_high); 1518 } 1519 if (freq != 624) { 1520 pxa27x_frequency_change(CCCR_A | CCCR_TURBO_X3 | 1521 CCCR_RUN_X16, CLKCFG_B | CLKCFG_F | CLKCFG_T, 1522 &pxa2x0_memcfg); 1523 freq = 624; 1524 } 1525 } 1526 1527 restore_interrupts(s); 1528 } 1529 1530 int 1531 pxa2x0_cpuspeed(int *freqp) 1532 { 1533 *freqp = freq; 1534 return 0; 1535 } 1536 1537 void pxa2x0_maxspeed(int *speedp); 1538 1539 void 1540 pxa2x0_maxspeed(int *speedp) 1541 { 1542 /* XXX assumes a pxa270 */ 1543 1544 if (*speedp < 207) { 1545 *speedp = 91; 1546 } else if (*speedp < 415) { 1547 *speedp = 208; 1548 } else if (*speedp < 519) { 1549 *speedp = 416; 1550 } else if (*speedp < 624) { 1551 *speedp = 520; 1552 #if 0 1553 } else if (*speedp < 651) { 1554 *speedp = 624; 1555 #endif 1556 } else { 1557 *speedp = 520; /* hope this is safe. */ 1558 } 1559 xscale_maxspeed = *speedp; 1560 #if 0 1561 pxa2x0_setperf(perflevel); 1562 #endif 1563 } 1564
Indexes created Sat Sep 27 14:09:57 GMT 2025