1 /* $NetBSD: cs4280.c,v 1.77 2024/02/08 20:51:24 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.77 2024/02/08 20:51:24 andvar Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/device.h> 64 #include <sys/proc.h> 65 #include <sys/systm.h> 66 #include <sys/audioio.h> 67 #include <sys/bus.h> 68 #include <sys/bswap.h> 69 70 #include <dev/audio/audio_if.h> 71 #include <dev/midi_if.h> 72 73 #include <dev/ic/ac97reg.h> 74 #include <dev/ic/ac97var.h> 75 76 #include <dev/pci/pcidevs.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/cs4280reg.h> 79 #include <dev/pci/cs4280_image.h> 80 #include <dev/pci/cs428xreg.h> 81 #include <dev/pci/cs428x.h> 82 83 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 84 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 85 86 /* IF functions for audio driver */ 87 static int cs4280_match(device_t, cfdata_t, void *); 88 static void cs4280_attach(device_t, device_t, void *); 89 static int cs4280_intr(void *); 90 static int cs4280_query_format(void *, audio_format_query_t *); 91 static int cs4280_set_format(void *, int, 92 const audio_params_t *, const audio_params_t *, 93 audio_filter_reg_t *, audio_filter_reg_t *); 94 static int cs4280_halt_output(void *); 95 static int cs4280_halt_input(void *); 96 static int cs4280_getdev(void *, struct audio_device *); 97 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 98 void *, const audio_params_t *); 99 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 100 void *, const audio_params_t *); 101 static int cs4280_read_codec(void *, u_int8_t, u_int16_t *); 102 static int cs4280_write_codec(void *, u_int8_t, u_int16_t); 103 #if 0 104 static int cs4280_reset_codec(void *); 105 #endif 106 static enum ac97_host_flags cs4280_flags_codec(void *); 107 108 static bool cs4280_resume(device_t, const pmf_qual_t *); 109 static bool cs4280_suspend(device_t, const pmf_qual_t *); 110 111 /* Internal functions */ 112 static const struct cs4280_card_t * cs4280_identify_card( 113 const struct pci_attach_args *); 114 static int cs4280_piix4_match(const struct pci_attach_args *); 115 static void cs4280_clkrun_hack(struct cs428x_softc *, int); 116 static void cs4280_clkrun_hack_init(struct cs428x_softc *); 117 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 118 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 119 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 120 uint32_t); 121 static int cs4280_download_image(struct cs428x_softc *); 122 static void cs4280_reset(void *); 123 static int cs4280_init(struct cs428x_softc *, int); 124 static void cs4280_clear_fifos(struct cs428x_softc *); 125 126 #if CS4280_DEBUG > 10 127 /* Thease two function is only for checking image loading is succeeded or not. */ 128 static int cs4280_check_images(struct cs428x_softc *); 129 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 130 uint32_t); 131 #endif 132 133 /* Special cards */ 134 struct cs4280_card_t 135 { 136 pcireg_t id; 137 enum cs428x_flags flags; 138 }; 139 140 #define _card(vend, prod, flags) \ 141 {PCI_ID_CODE(vend, prod), flags} 142 143 static const struct cs4280_card_t cs4280_cards[] = { 144 #if 0 /* untested, from ALSA driver */ 145 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 146 CS428X_FLAG_INVAC97EAMP), 147 #endif 148 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 149 CS428X_FLAG_INVAC97EAMP), 150 _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO, 151 CS428X_FLAG_CLKRUNHACK) 152 }; 153 154 #undef _card 155 156 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 157 158 static const struct audio_hw_if cs4280_hw_if = { 159 .query_format = cs4280_query_format, 160 .set_format = cs4280_set_format, 161 .round_blocksize = cs428x_round_blocksize, 162 .halt_output = cs4280_halt_output, 163 .halt_input = cs4280_halt_input, 164 .getdev = cs4280_getdev, 165 .set_port = cs428x_mixer_set_port, 166 .get_port = cs428x_mixer_get_port, 167 .query_devinfo = cs428x_query_devinfo, 168 .allocm = cs428x_malloc, 169 .freem = cs428x_free, 170 .round_buffersize = cs428x_round_buffersize, 171 .get_props = cs428x_get_props, 172 .trigger_output = cs4280_trigger_output, 173 .trigger_input = cs4280_trigger_input, 174 .get_locks = cs428x_get_locks, 175 }; 176 177 #if NMIDI > 0 178 /* Midi Interface */ 179 static int cs4280_midi_open(void *, int, void (*)(void *, int), 180 void (*)(void *), void *); 181 static void cs4280_midi_close(void*); 182 static int cs4280_midi_output(void *, int); 183 static void cs4280_midi_getinfo(void *, struct midi_info *); 184 185 static const struct midi_hw_if cs4280_midi_hw_if = { 186 cs4280_midi_open, 187 cs4280_midi_close, 188 cs4280_midi_output, 189 cs4280_midi_getinfo, 190 0, 191 cs428x_get_locks, 192 }; 193 #endif 194 195 CFATTACH_DECL_NEW(clcs, sizeof(struct cs428x_softc), 196 cs4280_match, cs4280_attach, NULL, NULL); 197 198 static struct audio_device cs4280_device = { 199 "CS4280", 200 "", 201 "cs4280" 202 }; 203 204 /* 205 * XXX recording must be 16bit stereo and sample rate range from 206 * 11025Hz to 48000Hz. However, it looks like to work with 8000Hz, 207 * although data sheets say lower limit is 11025Hz. 208 * XXX The combination of available formats is complicated, so I use 209 * a common format only. Please fix it if not suitable. 210 */ 211 static const struct audio_format cs4280_formats[] = { 212 { 213 .mode = AUMODE_PLAY | AUMODE_RECORD, 214 .encoding = AUDIO_ENCODING_SLINEAR_LE, 215 .validbits = 16, 216 .precision = 16, 217 .channels = 2, 218 .channel_mask = AUFMT_STEREO, 219 .frequency_type = 0, 220 .frequency = { 8000, 48000 }, 221 } 222 }; 223 #define CS4280_NFORMATS __arraycount(cs4280_formats) 224 225 static int 226 cs4280_match(device_t parent, cfdata_t match, void *aux) 227 { 228 struct pci_attach_args *pa; 229 230 pa = (struct pci_attach_args *)aux; 231 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 232 return 0; 233 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 234 #if 0 /* I can't confirm */ 235 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 236 #endif 237 ) 238 return 1; 239 return 0; 240 } 241 242 static void 243 cs4280_attach(device_t parent, device_t self, void *aux) 244 { 245 struct cs428x_softc *sc; 246 struct pci_attach_args *pa; 247 pci_chipset_tag_t pc; 248 const struct cs4280_card_t *cs_card; 249 char const *intrstr; 250 pcireg_t reg; 251 uint32_t mem; 252 int error; 253 char vendor[PCI_VENDORSTR_LEN]; 254 char product[PCI_PRODUCTSTR_LEN]; 255 char intrbuf[PCI_INTRSTR_LEN]; 256 257 sc = device_private(self); 258 sc->sc_dev = self; 259 pa = (struct pci_attach_args *)aux; 260 pc = pa->pa_pc; 261 262 pci_aprint_devinfo(pa, "Audio controller"); 263 264 cs_card = cs4280_identify_card(pa); 265 if (cs_card != NULL) { 266 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(cs_card->id)); 267 pci_findproduct(product, sizeof(product), 268 PCI_VENDOR(cs_card->id), PCI_PRODUCT(cs_card->id)); 269 aprint_normal_dev(sc->sc_dev, "%s %s\n", vendor, product); 270 sc->sc_flags = cs_card->flags; 271 } else { 272 sc->sc_flags = CS428X_FLAG_NONE; 273 } 274 275 sc->sc_pc = pa->pa_pc; 276 sc->sc_pt = pa->pa_tag; 277 278 /* Map I/O register */ 279 if (pci_mapreg_map(pa, PCI_BA0, 280 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 281 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 282 aprint_error_dev(sc->sc_dev, "can't map BA0 space\n"); 283 return; 284 } 285 if (pci_mapreg_map(pa, PCI_BA1, 286 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 287 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 288 aprint_error_dev(sc->sc_dev, "can't map BA1 space\n"); 289 return; 290 } 291 292 sc->sc_dmatag = pa->pa_dmat; 293 294 /* power up chip */ 295 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 296 pci_activate_null)) && error != EOPNOTSUPP) { 297 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 298 return; 299 } 300 301 /* Enable the device (set bus master flag) */ 302 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 303 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 304 reg | PCI_COMMAND_MASTER_ENABLE); 305 306 /* LATENCY_TIMER setting */ 307 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 308 if ( PCI_LATTIMER(mem) < 32 ) { 309 mem &= 0xffff00ff; 310 mem |= 0x00002000; 311 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 312 } 313 314 /* CLKRUN hack initialization */ 315 cs4280_clkrun_hack_init(sc); 316 317 /* Map and establish the interrupt. */ 318 if (pci_intr_map(pa, &sc->intrh)) { 319 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 320 return; 321 } 322 intrstr = pci_intr_string(pc, sc->intrh, intrbuf, sizeof(intrbuf)); 323 324 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 325 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 326 327 sc->sc_ih = pci_intr_establish_xname(sc->sc_pc, sc->intrh, IPL_AUDIO, 328 cs4280_intr, sc, device_xname(self)); 329 if (sc->sc_ih == NULL) { 330 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 331 if (intrstr != NULL) 332 aprint_error(" at %s", intrstr); 333 aprint_error("\n"); 334 mutex_destroy(&sc->sc_lock); 335 mutex_destroy(&sc->sc_intr_lock); 336 return; 337 } 338 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 339 340 /* Initialization */ 341 if(cs4280_init(sc, 1) != 0) { 342 mutex_destroy(&sc->sc_lock); 343 mutex_destroy(&sc->sc_intr_lock); 344 return; 345 } 346 347 sc->type = TYPE_CS4280; 348 349 /* setup buffer related parameters */ 350 sc->dma_size = CS4280_DCHUNK; 351 sc->dma_align = CS4280_DALIGN; 352 sc->hw_blocksize = CS4280_ICHUNK; 353 354 /* AC 97 attachment */ 355 sc->host_if.arg = sc; 356 sc->host_if.attach = cs428x_attach_codec; 357 sc->host_if.read = cs4280_read_codec; 358 sc->host_if.write = cs4280_write_codec; 359 #if 0 360 sc->host_if.reset = cs4280_reset_codec; 361 #else 362 sc->host_if.reset = NULL; 363 #endif 364 sc->host_if.flags = cs4280_flags_codec; 365 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { 366 aprint_error_dev(sc->sc_dev, "ac97_attach failed\n"); 367 return; 368 } 369 370 audio_attach_mi(&cs4280_hw_if, sc, sc->sc_dev); 371 372 #if NMIDI > 0 373 midi_attach_mi(&cs4280_midi_hw_if, sc, sc->sc_dev); 374 #endif 375 376 if (!pmf_device_register(self, cs4280_suspend, cs4280_resume)) 377 aprint_error_dev(self, "couldn't establish power handler\n"); 378 } 379 380 /* Interrupt handling function */ 381 static int 382 cs4280_intr(void *p) 383 { 384 /* 385 * XXX 386 * 387 * Since CS4280 has only 4kB DMA buffer and 388 * interrupt occurs every 2kB block, I create dummy buffer 389 * which returns to audio driver and actual DMA buffer 390 * using in DMA transfer. 391 * 392 * 393 * ring buffer in audio.c is pointed by BUFADDR 394 * <------ ring buffer size == 64kB ------> 395 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 396 * |= = = =|= = = =|= = = =|= = = =|= = = =| 397 * | | | | | | <- call audio_intp every 398 * sc->sc_[pr]_count time. 399 * 400 * actual DMA buffer is pointed by KERNADDR 401 * <-> DMA buffer size = 4kB 402 * |= =| 403 * 404 * 405 */ 406 struct cs428x_softc *sc; 407 uint32_t intr, mem; 408 char * empty_dma; 409 int handled; 410 411 sc = p; 412 handled = 0; 413 414 mutex_spin_enter(&sc->sc_intr_lock); 415 416 /* grab interrupt register then clear it */ 417 intr = BA0READ4(sc, CS4280_HISR); 418 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 419 420 /* not for us ? */ 421 if ((intr & HISR_INTENA) == 0) { 422 mutex_spin_exit(&sc->sc_intr_lock); 423 return 0; 424 } 425 426 /* Playback Interrupt */ 427 if (intr & HISR_PINT) { 428 handled = 1; 429 mem = BA1READ4(sc, CS4280_PFIE); 430 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 431 if (sc->sc_prun) { 432 if ((sc->sc_pi%sc->sc_pcount) == 0) 433 sc->sc_pintr(sc->sc_parg); 434 /* copy buffer */ 435 ++sc->sc_pi; 436 empty_dma = sc->sc_pdma->addr; 437 if (sc->sc_pi&1) 438 empty_dma += sc->hw_blocksize; 439 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 440 sc->sc_pn += sc->hw_blocksize; 441 if (sc->sc_pn >= sc->sc_pe) 442 sc->sc_pn = sc->sc_ps; 443 } else { 444 aprint_error_dev(sc->sc_dev, "unexpected play intr\n"); 445 } 446 BA1WRITE4(sc, CS4280_PFIE, mem); 447 } 448 /* Capture Interrupt */ 449 if (intr & HISR_CINT) { 450 handled = 1; 451 mem = BA1READ4(sc, CS4280_CIE); 452 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 453 454 if (sc->sc_rrun) { 455 ++sc->sc_ri; 456 empty_dma = sc->sc_rdma->addr; 457 if ((sc->sc_ri&1) == 0) 458 empty_dma += sc->hw_blocksize; 459 460 /* just copy it */ 461 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 462 sc->sc_rn += sc->hw_blocksize; 463 if (sc->sc_rn >= sc->sc_re) 464 sc->sc_rn = sc->sc_rs; 465 } 466 BA1WRITE4(sc, CS4280_CIE, mem); 467 468 if (sc->sc_rrun) { 469 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 470 sc->sc_rintr(sc->sc_rarg); 471 } else { 472 aprint_error_dev(sc->sc_dev, 473 "unexpected record intr\n"); 474 } 475 } 476 477 #if NMIDI > 0 478 /* Midi port Interrupt */ 479 if (intr & HISR_MIDI) { 480 int data; 481 482 handled = 1; 483 DPRINTF(("i: %d: ", 484 BA0READ4(sc, CS4280_MIDSR))); 485 /* Read the received data */ 486 while ((sc->sc_iintr != NULL) && 487 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 488 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 489 DPRINTF(("r:%x\n",data)); 490 sc->sc_iintr(sc->sc_arg, data); 491 } 492 493 /* Write the data */ 494 #if 1 495 /* XXX: 496 * It seems "Transmit Buffer Full" never activate until EOI 497 * is deliverd. Shall I throw EOI top of this routine ? 498 */ 499 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 500 DPRINTF(("w: ")); 501 if (sc->sc_ointr != NULL) 502 sc->sc_ointr(sc->sc_arg); 503 } 504 #else 505 while ((sc->sc_ointr != NULL) && 506 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 507 DPRINTF(("w: ")); 508 sc->sc_ointr(sc->sc_arg); 509 } 510 #endif 511 DPRINTF(("\n")); 512 } 513 #endif 514 515 mutex_spin_exit(&sc->sc_intr_lock); 516 return handled; 517 } 518 519 static int 520 cs4280_query_format(void *addr, audio_format_query_t *afp) 521 { 522 523 return audio_query_format(cs4280_formats, CS4280_NFORMATS, afp); 524 } 525 526 static int 527 cs4280_set_format(void *addr, int setmode, 528 const audio_params_t *play, const audio_params_t *rec, 529 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil) 530 { 531 struct cs428x_softc *sc; 532 533 sc = addr; 534 /* set sample rate */ 535 cs4280_set_dac_rate(sc, play->sample_rate); 536 cs4280_set_adc_rate(sc, rec->sample_rate); 537 return 0; 538 } 539 540 static int 541 cs4280_halt_output(void *addr) 542 { 543 struct cs428x_softc *sc; 544 uint32_t mem; 545 546 sc = addr; 547 mem = BA1READ4(sc, CS4280_PCTL); 548 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 549 sc->sc_prun = 0; 550 cs4280_clkrun_hack(sc, -1); 551 552 return 0; 553 } 554 555 static int 556 cs4280_halt_input(void *addr) 557 { 558 struct cs428x_softc *sc; 559 uint32_t mem; 560 561 sc = addr; 562 mem = BA1READ4(sc, CS4280_CCTL); 563 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 564 sc->sc_rrun = 0; 565 cs4280_clkrun_hack(sc, -1); 566 567 return 0; 568 } 569 570 static int 571 cs4280_getdev(void *addr, struct audio_device *retp) 572 { 573 574 *retp = cs4280_device; 575 return 0; 576 } 577 578 static int 579 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 580 void (*intr)(void *), void *arg, 581 const audio_params_t *param) 582 { 583 struct cs428x_softc *sc; 584 uint32_t pfie, pctl, pdtc; 585 struct cs428x_dma *p; 586 587 sc = addr; 588 #ifdef DIAGNOSTIC 589 if (sc->sc_prun) 590 printf("cs4280_trigger_output: already running\n"); 591 #endif 592 sc->sc_prun = 1; 593 cs4280_clkrun_hack(sc, 1); 594 595 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 596 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 597 sc->sc_pintr = intr; 598 sc->sc_parg = arg; 599 600 /* stop playback DMA */ 601 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 602 603 /* setup PDTC */ 604 pdtc = BA1READ4(sc, CS4280_PDTC); 605 pdtc &= ~PDTC_MASK; 606 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 607 BA1WRITE4(sc, CS4280_PDTC, pdtc); 608 609 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 610 param->precision, param->channels, param->encoding)); 611 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 612 continue; 613 if (p == NULL) { 614 printf("cs4280_trigger_output: bad addr %p\n", start); 615 return EINVAL; 616 } 617 if (DMAADDR(p) % sc->dma_align != 0 ) { 618 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 619 "4kB align\n", (ulong)DMAADDR(p)); 620 return EINVAL; 621 } 622 623 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 624 sc->sc_ps = (char *)start; 625 sc->sc_pe = (char *)end; 626 sc->sc_pdma = p; 627 sc->sc_pbuf = KERNADDR(p); 628 sc->sc_pi = 0; 629 sc->sc_pn = sc->sc_ps; 630 if (blksize >= sc->dma_size) { 631 sc->sc_pn = sc->sc_ps + sc->dma_size; 632 memcpy(sc->sc_pbuf, start, sc->dma_size); 633 ++sc->sc_pi; 634 } else { 635 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 636 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 637 } 638 639 /* initiate playback DMA */ 640 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 641 642 /* set PFIE */ 643 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 644 if (param->encoding == AUDIO_ENCODING_SLINEAR_BE) 645 pfie |= PFIE_SWAPPED; 646 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 647 648 sc->sc_prate = param->sample_rate; 649 cs4280_set_dac_rate(sc, param->sample_rate); 650 651 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 652 pctl |= sc->pctl; 653 BA1WRITE4(sc, CS4280_PCTL, pctl); 654 return 0; 655 } 656 657 static int 658 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 659 void (*intr)(void *), void *arg, 660 const audio_params_t *param) 661 { 662 struct cs428x_softc *sc; 663 uint32_t cctl, cie; 664 struct cs428x_dma *p; 665 666 sc = addr; 667 #ifdef DIAGNOSTIC 668 if (sc->sc_rrun) 669 printf("cs4280_trigger_input: already running\n"); 670 #endif 671 sc->sc_rrun = 1; 672 cs4280_clkrun_hack(sc, 1); 673 674 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 675 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 676 sc->sc_rintr = intr; 677 sc->sc_rarg = arg; 678 679 /* stop capture DMA */ 680 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 681 682 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 683 continue; 684 if (p == NULL) { 685 printf("cs4280_trigger_input: bad addr %p\n", start); 686 return EINVAL; 687 } 688 if (DMAADDR(p) % sc->dma_align != 0) { 689 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 690 "4kB align\n", (ulong)DMAADDR(p)); 691 return EINVAL; 692 } 693 694 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 695 sc->sc_rs = (char *)start; 696 sc->sc_re = (char *)end; 697 sc->sc_rdma = p; 698 sc->sc_rbuf = KERNADDR(p); 699 sc->sc_ri = 0; 700 sc->sc_rn = sc->sc_rs; 701 702 /* initiate capture DMA */ 703 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 704 705 /* set CIE */ 706 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 707 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 708 709 sc->sc_rrate = param->sample_rate; 710 cs4280_set_adc_rate(sc, param->sample_rate); 711 712 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 713 cctl |= sc->cctl; 714 BA1WRITE4(sc, CS4280_CCTL, cctl); 715 return 0; 716 } 717 718 static bool 719 cs4280_suspend(device_t dv, const pmf_qual_t *qual) 720 { 721 struct cs428x_softc *sc = device_private(dv); 722 723 mutex_exit(&sc->sc_lock); 724 mutex_spin_enter(&sc->sc_intr_lock); 725 726 if (sc->sc_prun) { 727 sc->sc_suspend_state.cs4280.pctl = BA1READ4(sc, CS4280_PCTL); 728 sc->sc_suspend_state.cs4280.pfie = BA1READ4(sc, CS4280_PFIE); 729 sc->sc_suspend_state.cs4280.pba = BA1READ4(sc, CS4280_PBA); 730 sc->sc_suspend_state.cs4280.pdtc = BA1READ4(sc, CS4280_PDTC); 731 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 732 sc->sc_suspend_state.cs4280.pctl, 733 sc->sc_suspend_state.cs4280.pfie, 734 sc->sc_suspend_state.cs4280.pba, 735 sc->sc_suspend_state.cs4280.pdtc)); 736 } 737 738 /* save current capture status */ 739 if (sc->sc_rrun) { 740 sc->sc_suspend_state.cs4280.cctl = BA1READ4(sc, CS4280_CCTL); 741 sc->sc_suspend_state.cs4280.cie = BA1READ4(sc, CS4280_CIE); 742 sc->sc_suspend_state.cs4280.cba = BA1READ4(sc, CS4280_CBA); 743 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 744 sc->sc_suspend_state.cs4280.cctl, 745 sc->sc_suspend_state.cs4280.cie, 746 sc->sc_suspend_state.cs4280.cba)); 747 } 748 749 /* Stop DMA */ 750 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl & ~PCTL_MASK); 751 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 752 753 mutex_spin_exit(&sc->sc_intr_lock); 754 mutex_exit(&sc->sc_lock); 755 756 return true; 757 } 758 759 static bool 760 cs4280_resume(device_t dv, const pmf_qual_t *qual) 761 { 762 struct cs428x_softc *sc = device_private(dv); 763 764 mutex_exit(&sc->sc_lock); 765 mutex_spin_enter(&sc->sc_intr_lock); 766 cs4280_init(sc, 0); 767 #if 0 768 cs4280_reset_codec(sc); 769 #endif 770 771 /* restore DMA related status */ 772 if(sc->sc_prun) { 773 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 774 sc->sc_suspend_state.cs4280.pctl, 775 sc->sc_suspend_state.cs4280.pfie, 776 sc->sc_suspend_state.cs4280.pba, 777 sc->sc_suspend_state.cs4280.pdtc)); 778 cs4280_set_dac_rate(sc, sc->sc_prate); 779 BA1WRITE4(sc, CS4280_PDTC, sc->sc_suspend_state.cs4280.pdtc); 780 BA1WRITE4(sc, CS4280_PBA, sc->sc_suspend_state.cs4280.pba); 781 BA1WRITE4(sc, CS4280_PFIE, sc->sc_suspend_state.cs4280.pfie); 782 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl); 783 } 784 785 if (sc->sc_rrun) { 786 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 787 sc->sc_suspend_state.cs4280.cctl, 788 sc->sc_suspend_state.cs4280.cie, 789 sc->sc_suspend_state.cs4280.cba)); 790 cs4280_set_adc_rate(sc, sc->sc_rrate); 791 BA1WRITE4(sc, CS4280_CBA, sc->sc_suspend_state.cs4280.cba); 792 BA1WRITE4(sc, CS4280_CIE, sc->sc_suspend_state.cs4280.cie); 793 BA1WRITE4(sc, CS4280_CCTL, sc->sc_suspend_state.cs4280.cctl); 794 } 795 796 mutex_spin_exit(&sc->sc_intr_lock); 797 798 /* restore ac97 registers */ 799 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 800 801 mutex_exit(&sc->sc_lock); 802 803 return true; 804 } 805 806 static int 807 cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result) 808 { 809 struct cs428x_softc *sc = addr; 810 int rv; 811 812 cs4280_clkrun_hack(sc, 1); 813 rv = cs428x_read_codec(addr, reg, result); 814 cs4280_clkrun_hack(sc, -1); 815 816 return rv; 817 } 818 819 static int 820 cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data) 821 { 822 struct cs428x_softc *sc = addr; 823 int rv; 824 825 cs4280_clkrun_hack(sc, 1); 826 rv = cs428x_write_codec(addr, reg, data); 827 cs4280_clkrun_hack(sc, -1); 828 829 return rv; 830 } 831 832 #if 0 /* XXX buggy and not required */ 833 /* control AC97 codec */ 834 static int 835 cs4280_reset_codec(void *addr) 836 { 837 struct cs428x_softc *sc; 838 int n; 839 840 sc = addr; 841 842 /* Reset codec */ 843 BA0WRITE4(sc, CS428X_ACCTL, 0); 844 delay(100); /* delay 100us */ 845 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 846 847 /* 848 * It looks like we do the following procedure, too 849 */ 850 851 /* Enable AC-link sync generation */ 852 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 853 delay(50*1000); /* XXX delay 50ms */ 854 855 /* Assert valid frame signal */ 856 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 857 858 /* Wait for valid AC97 input slot */ 859 n = 0; 860 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 861 (ACISV_ISV3 | ACISV_ISV4)) { 862 delay(1000); 863 if (++n > 1000) { 864 printf("reset_codec: AC97 inputs slot ready timeout\n"); 865 return ETIMEDOUT; 866 } 867 } 868 869 return 0; 870 } 871 #endif 872 873 static enum ac97_host_flags 874 cs4280_flags_codec(void *addr) 875 { 876 struct cs428x_softc *sc; 877 878 sc = addr; 879 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 880 return AC97_HOST_INVERTED_EAMP; 881 882 return 0; 883 } 884 885 /* Internal functions */ 886 887 static const struct cs4280_card_t * 888 cs4280_identify_card(const struct pci_attach_args *pa) 889 { 890 pcireg_t idreg; 891 u_int16_t i; 892 893 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 894 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 895 if (idreg == cs4280_cards[i].id) 896 return &cs4280_cards[i]; 897 } 898 899 return NULL; 900 } 901 902 static int 903 cs4280_piix4_match(const struct pci_attach_args *pa) 904 { 905 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 906 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) { 907 return 1; 908 } 909 910 return 0; 911 } 912 913 static void 914 cs4280_clkrun_hack(struct cs428x_softc *sc, int change) 915 { 916 uint16_t control, val; 917 918 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 919 return; 920 921 sc->sc_active += change; 922 val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10); 923 if (!sc->sc_active) 924 val |= 0x2000; 925 else 926 val &= ~0x2000; 927 if (val != control) 928 bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val); 929 } 930 931 static void 932 cs4280_clkrun_hack_init(struct cs428x_softc *sc) 933 { 934 struct pci_attach_args smbuspa; 935 uint16_t reg; 936 pcireg_t port; 937 938 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 939 return; 940 941 if (pci_find_device(&smbuspa, cs4280_piix4_match)) { 942 sc->sc_active = 0; 943 aprint_normal_dev(sc->sc_dev, "enabling CLKRUN hack\n"); 944 945 reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40); 946 port = reg & 0xffc0; 947 aprint_normal_dev(sc->sc_dev, "power management port 0x%x\n", 948 port); 949 950 sc->sc_pm_iot = smbuspa.pa_iot; 951 if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0, 952 &sc->sc_pm_ioh) == 0) 953 return; 954 } 955 956 /* handle error */ 957 sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK; 958 aprint_normal_dev(sc->sc_dev, "disabling CLKRUN hack\n"); 959 } 960 961 static void 962 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 963 { 964 /* calculate capture rate: 965 * 966 * capture_coefficient_increment = -round(rate*128*65536/48000; 967 * capture_phase_increment = floor(48000*65536*1024/rate); 968 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 969 * cy = floor(cx/200); 970 * capture_sample_rate_correction = cx - 200*cy; 971 * capture_delay = ceil(24*48000/rate); 972 * capture_num_triplets = floor(65536*rate/24000); 973 * capture_group_length = 24000/GCD(rate, 24000); 974 * where GCD means "Greatest Common Divisor". 975 * 976 * capture_coefficient_increment, capture_phase_increment and 977 * capture_num_triplets are 32-bit signed quantities. 978 * capture_sample_rate_correction and capture_group_length are 979 * 16-bit signed quantities. 980 * capture_delay is a 14-bit unsigned quantity. 981 */ 982 uint32_t cci, cpi, cnt, cx, cy, tmp1; 983 uint16_t csrc, cgl, cdlay; 984 985 /* XXX 986 * Even though, embedded_audio_spec says capture rate range 11025 to 987 * 48000, dhwiface.cpp says, 988 * 989 * "We can only decimate by up to a factor of 1/9th the hardware rate. 990 * Return an error if an attempt is made to stray outside that limit." 991 * 992 * so assume range as 48000/9 to 48000 993 */ 994 995 if (rate < 8000) 996 rate = 8000; 997 if (rate > 48000) 998 rate = 48000; 999 1000 cx = rate << 16; 1001 cci = cx / 48000; 1002 cx -= cci * 48000; 1003 cx <<= 7; 1004 cci <<= 7; 1005 cci += cx / 48000; 1006 cci = - cci; 1007 1008 cx = 48000 << 16; 1009 cpi = cx / rate; 1010 cx -= cpi * rate; 1011 cx <<= 10; 1012 cpi <<= 10; 1013 cy = cx / rate; 1014 cpi += cy; 1015 cx -= cy * rate; 1016 1017 cy = cx / 200; 1018 csrc = cx - 200*cy; 1019 1020 cdlay = ((48000 * 24) + rate - 1) / rate; 1021 #if 0 1022 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1023 #endif 1024 1025 cnt = rate << 16; 1026 cnt /= 24000; 1027 1028 cgl = 1; 1029 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1030 if (((rate / tmp1) * tmp1) != rate) 1031 cgl *= 2; 1032 } 1033 if (((rate / 3) * 3) != rate) 1034 cgl *= 3; 1035 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1036 if (((rate / tmp1) * tmp1) != rate) 1037 cgl *= 5; 1038 } 1039 #if 0 1040 /* XXX what manual says */ 1041 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1042 tmp1 |= csrc<<16; 1043 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1044 #else 1045 /* suggested by cs461x.c (ALSA driver) */ 1046 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1047 #endif 1048 1049 #if 0 1050 /* I am confused. The sample rate calculation section says 1051 * cci *is* 32-bit signed quantity but in the parameter description 1052 * section, CCI only assigned 16bit. 1053 * I believe size of the variable. 1054 */ 1055 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1056 tmp1 |= cci<<16; 1057 BA1WRITE4(sc, CS4280_CCI, tmp1); 1058 #else 1059 BA1WRITE4(sc, CS4280_CCI, cci); 1060 #endif 1061 1062 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1063 tmp1 |= cdlay <<18; 1064 BA1WRITE4(sc, CS4280_CD, tmp1); 1065 1066 BA1WRITE4(sc, CS4280_CPI, cpi); 1067 1068 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1069 tmp1 |= cgl; 1070 BA1WRITE4(sc, CS4280_CGL, tmp1); 1071 1072 BA1WRITE4(sc, CS4280_CNT, cnt); 1073 1074 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1075 tmp1 |= cgl; 1076 BA1WRITE4(sc, CS4280_CGC, tmp1); 1077 } 1078 1079 static void 1080 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1081 { 1082 /* 1083 * playback rate may range from 8000Hz to 48000Hz 1084 * 1085 * play_phase_increment = floor(rate*65536*1024/48000) 1086 * px = round(rate*65536*1024 - play_phase_increment*48000) 1087 * py=floor(px/200) 1088 * play_sample_rate_correction = px - 200*py 1089 * 1090 * play_phase_increment is a 32bit signed quantity. 1091 * play_sample_rate_correction is a 16bit signed quantity. 1092 */ 1093 int32_t ppi; 1094 int16_t psrc; 1095 uint32_t px, py; 1096 1097 if (rate < 8000) 1098 rate = 8000; 1099 if (rate > 48000) 1100 rate = 48000; 1101 px = rate << 16; 1102 ppi = px/48000; 1103 px -= ppi*48000; 1104 ppi <<= 10; 1105 px <<= 10; 1106 py = px / 48000; 1107 ppi += py; 1108 px -= py*48000; 1109 py = px/200; 1110 px -= py*200; 1111 psrc = px; 1112 #if 0 1113 /* what manual says */ 1114 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1115 BA1WRITE4(sc, CS4280_PSRC, 1116 ( ((psrc<<16) & PSRC_MASK) | px )); 1117 #else 1118 /* suggested by cs461x.c (ALSA driver) */ 1119 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1120 #endif 1121 BA1WRITE4(sc, CS4280_PPI, ppi); 1122 } 1123 1124 /* Download Processor Code and Data image */ 1125 static int 1126 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1127 uint32_t offset, uint32_t len) 1128 { 1129 uint32_t ctr; 1130 #if CS4280_DEBUG > 10 1131 uint32_t con, data; 1132 uint8_t c0, c1, c2, c3; 1133 #endif 1134 if ((offset & 3) || (len & 3)) 1135 return -1; 1136 1137 len /= sizeof(uint32_t); 1138 for (ctr = 0; ctr < len; ctr++) { 1139 /* XXX: 1140 * I cannot confirm this is the right thing or not 1141 * on BIG-ENDIAN machines. 1142 */ 1143 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1144 #if CS4280_DEBUG > 10 1145 data = htole32(*(src+ctr)); 1146 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1147 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1148 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1149 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1150 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1151 if (data != con ) { 1152 printf("0x%06x: write=0x%08x read=0x%08x\n", 1153 offset+ctr*4, data, con); 1154 return -1; 1155 } 1156 #endif 1157 } 1158 return 0; 1159 } 1160 1161 static int 1162 cs4280_download_image(struct cs428x_softc *sc) 1163 { 1164 int idx, err; 1165 uint32_t offset = 0; 1166 1167 err = 0; 1168 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1169 err = cs4280_download(sc, &BA1Struct.map[offset], 1170 BA1Struct.memory[idx].offset, 1171 BA1Struct.memory[idx].size); 1172 if (err != 0) { 1173 aprint_error_dev(sc->sc_dev, 1174 "load_image failed at %d\n", idx); 1175 return -1; 1176 } 1177 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1178 } 1179 return err; 1180 } 1181 1182 /* Processor Soft Reset */ 1183 static void 1184 cs4280_reset(void *sc_) 1185 { 1186 struct cs428x_softc *sc; 1187 1188 sc = sc_; 1189 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1190 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1191 delay(100); 1192 /* Clear RSTSP bit in SPCR */ 1193 BA1WRITE4(sc, CS4280_SPCR, 0); 1194 /* enable DMA request */ 1195 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1196 } 1197 1198 static int 1199 cs4280_init(struct cs428x_softc *sc, int init) 1200 { 1201 int n; 1202 uint32_t mem; 1203 int rv; 1204 1205 rv = 1; 1206 cs4280_clkrun_hack(sc, 1); 1207 1208 /* Start PLL out in known state */ 1209 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1210 /* Start serial ports out in known state */ 1211 BA0WRITE4(sc, CS4280_SERMC1, 0); 1212 1213 /* Specify type of CODEC */ 1214 /* XXX should not be here */ 1215 #define SERACC_CODEC_TYPE_1_03 1216 #ifdef SERACC_CODEC_TYPE_1_03 1217 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1218 #else 1219 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1220 #endif 1221 1222 /* Reset codec */ 1223 BA0WRITE4(sc, CS428X_ACCTL, 0); 1224 delay(100); /* delay 100us */ 1225 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1226 1227 /* Enable AC-link sync generation */ 1228 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1229 delay(50*1000); /* delay 50ms */ 1230 1231 /* Set the serial port timing configuration */ 1232 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1233 1234 /* Setup clock control */ 1235 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1236 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1237 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1238 1239 /* Power up the PLL */ 1240 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1241 delay(50*1000); /* delay 50ms */ 1242 1243 /* Turn on clock */ 1244 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1245 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1246 1247 /* Set the serial port FIFO pointer to the 1248 * first sample in FIFO. (not documented) */ 1249 cs4280_clear_fifos(sc); 1250 1251 #if 0 1252 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1253 BA0WRITE4(sc, CS4280_SERBSP, 0); 1254 #endif 1255 1256 /* Configure the serial port */ 1257 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1258 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1259 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1260 1261 /* Wait for CODEC ready */ 1262 n = 0; 1263 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1264 delay(125); 1265 if (++n > 1000) { 1266 aprint_error_dev(sc->sc_dev, "codec ready timeout\n"); 1267 goto exit; 1268 } 1269 } 1270 1271 /* Assert valid frame signal */ 1272 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1273 1274 /* Wait for valid AC97 input slot */ 1275 n = 0; 1276 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1277 (ACISV_ISV3 | ACISV_ISV4)) { 1278 delay(1000); 1279 if (++n > 1000) { 1280 printf("AC97 inputs slot ready timeout\n"); 1281 goto exit; 1282 } 1283 } 1284 1285 /* Set AC97 output slot valid signals */ 1286 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1287 1288 /* reset the processor */ 1289 cs4280_reset(sc); 1290 1291 /* Download the image to the processor */ 1292 if (cs4280_download_image(sc) != 0) { 1293 aprint_error_dev(sc->sc_dev, "image download error\n"); 1294 goto exit; 1295 } 1296 1297 /* Save playback parameter and then write zero. 1298 * this ensures that DMA doesn't immediately occur upon 1299 * starting the processor core 1300 */ 1301 mem = BA1READ4(sc, CS4280_PCTL); 1302 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1303 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1304 if (init != 0) 1305 sc->sc_prun = 0; 1306 1307 /* Save capture parameter and then write zero. 1308 * this ensures that DMA doesn't immediately occur upon 1309 * starting the processor core 1310 */ 1311 mem = BA1READ4(sc, CS4280_CCTL); 1312 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1313 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1314 if (init != 0) 1315 sc->sc_rrun = 0; 1316 1317 /* Processor Startup Procedure */ 1318 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1319 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1320 1321 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1322 n = 0; 1323 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1324 delay(10); 1325 if (++n > 1000) { 1326 printf("SPCR 1->0 transition timeout\n"); 1327 goto exit; 1328 } 1329 } 1330 1331 n = 0; 1332 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1333 delay(10); 1334 if (++n > 1000) { 1335 printf("SPCS 0->1 transition timeout\n"); 1336 goto exit; 1337 } 1338 } 1339 /* Processor is now running !!! */ 1340 1341 /* Setup volume */ 1342 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1343 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1344 1345 /* Interrupt enable */ 1346 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1347 1348 /* playback interrupt enable */ 1349 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1350 mem |= PFIE_PI_ENABLE; 1351 BA1WRITE4(sc, CS4280_PFIE, mem); 1352 /* capture interrupt enable */ 1353 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1354 mem |= CIE_CI_ENABLE; 1355 BA1WRITE4(sc, CS4280_CIE, mem); 1356 1357 #if NMIDI > 0 1358 /* Reset midi port */ 1359 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1360 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1361 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1362 /* midi interrupt enable */ 1363 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1364 BA0WRITE4(sc, CS4280_MIDCR, mem); 1365 #endif 1366 1367 rv = 0; 1368 1369 exit: 1370 cs4280_clkrun_hack(sc, -1); 1371 return rv; 1372 } 1373 1374 static void 1375 cs4280_clear_fifos(struct cs428x_softc *sc) 1376 { 1377 int pd, cnt, n; 1378 uint32_t mem; 1379 1380 pd = 0; 1381 /* 1382 * If device power down, power up the device and keep power down 1383 * state. 1384 */ 1385 mem = BA0READ4(sc, CS4280_CLKCR1); 1386 if (!(mem & CLKCR1_SWCE)) { 1387 printf("cs4280_clear_fifo: power down found.\n"); 1388 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1389 pd = 1; 1390 } 1391 BA0WRITE4(sc, CS4280_SERBWP, 0); 1392 for (cnt = 0; cnt < 256; cnt++) { 1393 n = 0; 1394 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1395 delay(1000); 1396 if (++n > 1000) { 1397 printf("clear_fifo: first timeout cnt=%d\n", cnt); 1398 break; 1399 } 1400 } 1401 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1402 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1403 } 1404 if (pd) 1405 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1406 } 1407 1408 #if NMIDI > 0 1409 static int 1410 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1411 void (*ointr)(void *), void *arg) 1412 { 1413 struct cs428x_softc *sc; 1414 uint32_t mem; 1415 1416 DPRINTF(("midi_open\n")); 1417 sc = addr; 1418 sc->sc_iintr = iintr; 1419 sc->sc_ointr = ointr; 1420 sc->sc_arg = arg; 1421 1422 /* midi interrupt enable */ 1423 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1424 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1425 BA0WRITE4(sc, CS4280_MIDCR, mem); 1426 #ifdef CS4280_DEBUG 1427 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1428 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1429 return(EINVAL); 1430 } 1431 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1432 #endif 1433 return 0; 1434 } 1435 1436 static void 1437 cs4280_midi_close(void *addr) 1438 { 1439 struct cs428x_softc *sc; 1440 uint32_t mem; 1441 1442 DPRINTF(("midi_close\n")); 1443 sc = addr; 1444 /* give uart a chance to drain */ 1445 kpause("cs0clm", false, hz/10, &sc->sc_intr_lock); 1446 mem = BA0READ4(sc, CS4280_MIDCR); 1447 mem &= ~MIDCR_MASK; 1448 BA0WRITE4(sc, CS4280_MIDCR, mem); 1449 1450 sc->sc_iintr = 0; 1451 sc->sc_ointr = 0; 1452 } 1453 1454 static int 1455 cs4280_midi_output(void *addr, int d) 1456 { 1457 struct cs428x_softc *sc; 1458 uint32_t mem; 1459 int x; 1460 1461 sc = addr; 1462 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1463 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1464 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1465 mem |= d & MIDWP_MASK; 1466 DPRINTFN(5,("midi_output d=0x%08x",d)); 1467 BA0WRITE4(sc, CS4280_MIDWP, mem); 1468 #ifdef DIAGNOSTIC 1469 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1470 DPRINTF(("Bad write data: %d %d", 1471 mem, BA0READ4(sc, CS4280_MIDWP))); 1472 return EIO; 1473 } 1474 #endif 1475 return 0; 1476 } 1477 delay(MIDI_BUSY_DELAY); 1478 } 1479 return EIO; 1480 } 1481 1482 static void 1483 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1484 { 1485 1486 mi->name = "CS4280 MIDI UART"; 1487 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1488 } 1489 1490 #endif /* NMIDI */ 1491 1492 /* DEBUG functions */ 1493 #if CS4280_DEBUG > 10 1494 static int 1495 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1496 uint32_t offset, uint32_t len) 1497 { 1498 uint32_t ctr, data; 1499 int err; 1500 1501 if ((offset & 3) || (len & 3)) 1502 return -1; 1503 1504 err = 0; 1505 len /= sizeof(uint32_t); 1506 for (ctr = 0; ctr < len; ctr++) { 1507 /* I cannot confirm this is the right thing 1508 * on BIG-ENDIAN machines 1509 */ 1510 data = BA1READ4(sc, offset+ctr*4); 1511 if (data != htole32(*(src+ctr))) { 1512 printf("0x%06x: 0x%08x(0x%08x)\n", 1513 offset+ctr*4, data, *(src+ctr)); 1514 *(src+ctr) = data; 1515 ++err; 1516 } 1517 } 1518 return err; 1519 } 1520 1521 static int 1522 cs4280_check_images(struct cs428x_softc *sc) 1523 { 1524 int idx, err; 1525 uint32_t offset; 1526 1527 offset = 0; 1528 err = 0; 1529 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1530 for (idx = 0; idx < 1; ++idx) { 1531 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1532 BA1Struct.memory[idx].offset, 1533 BA1Struct.memory[idx].size); 1534 if (err != 0) { 1535 aprint_error_dev(sc->sc_dev, 1536 "check_image failed at %d\n", idx); 1537 } 1538 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1539 } 1540 return err; 1541 } 1542 1543 #endif /* CS4280_DEBUG */ 1544
Indexes created Sat Sep 27 14:09:57 GMT 2025