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      1 /*	$NetBSD: cs4281.c,v 1.61 2025/01/07 18:27:26 andvar Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2000 Tatoku Ogaito.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *      This product includes software developed by Tatoku Ogaito
     17  *	for the NetBSD Project.
     18  * 4. The name of the author may not be used to endorse or promote products
     19  *    derived from this software without specific prior written permission
     20  *
     21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     31  */
     32 
     33 /*
     34  * Cirrus Logic CS4281 driver.
     35  * Data sheets can be found
     36  * http://www.cirrus.com/ftp/pub/4281.pdf
     37  * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf
     38  *
     39  * TODO:
     40  *   1: midi and FM support
     41  *   2: ...
     42  *
     43  */
     44 
     45 #include <sys/cdefs.h>
     46 __KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.61 2025/01/07 18:27:26 andvar Exp $");
     47 
     48 #include <sys/param.h>
     49 #include <sys/systm.h>
     50 #include <sys/kernel.h>
     51 #include <sys/fcntl.h>
     52 #include <sys/device.h>
     53 #include <sys/systm.h>
     54 
     55 #include <dev/pci/pcidevs.h>
     56 #include <dev/pci/pcivar.h>
     57 #include <dev/pci/cs4281reg.h>
     58 #include <dev/pci/cs428xreg.h>
     59 
     60 #include <sys/audioio.h>
     61 #include <dev/audio/audio_if.h>
     62 #include <dev/midi_if.h>
     63 
     64 #include <dev/ic/ac97reg.h>
     65 #include <dev/ic/ac97var.h>
     66 
     67 #include <dev/pci/cs428x.h>
     68 
     69 #include <sys/bus.h>
     70 
     71 #if defined(ENABLE_SECONDARY_CODEC)
     72 #define MAX_CHANNELS  (4)
     73 #define MAX_FIFO_SIZE 32 /* 128/4channels */
     74 #else
     75 #define MAX_CHANNELS  (2)
     76 #define MAX_FIFO_SIZE 64 /* 128/2channels */
     77 #endif
     78 
     79 /* IF functions for audio driver */
     80 static int	cs4281_match(device_t, cfdata_t, void *);
     81 static void	cs4281_attach(device_t, device_t, void *);
     82 static int	cs4281_intr(void *);
     83 static int	cs4281_query_format(void *, audio_format_query_t *);
     84 static int	cs4281_set_format(void *, int,
     85 				 const audio_params_t *, const audio_params_t *,
     86 				 audio_filter_reg_t *, audio_filter_reg_t *);
     87 static int	cs4281_halt_output(void *);
     88 static int	cs4281_halt_input(void *);
     89 static int	cs4281_getdev(void *, struct audio_device *);
     90 static int	cs4281_trigger_output(void *, void *, void *, int,
     91 				      void (*)(void *), void *,
     92 				      const audio_params_t *);
     93 static int	cs4281_trigger_input(void *, void *, void *, int,
     94 				     void (*)(void *), void *,
     95 				     const audio_params_t *);
     96 
     97 static int	cs4281_reset_codec(void *);
     98 
     99 /* Internal functions */
    100 static uint8_t	cs4281_sr2regval(int);
    101 static void	cs4281_set_dac_rate(struct cs428x_softc *, int);
    102 static void	cs4281_set_adc_rate(struct cs428x_softc *, int);
    103 static int      cs4281_init(struct cs428x_softc *, int);
    104 
    105 /* Power Management */
    106 static bool	cs4281_suspend(device_t, const pmf_qual_t *);
    107 static bool	cs4281_resume(device_t, const pmf_qual_t *);
    108 
    109 static const struct audio_hw_if cs4281_hw_if = {
    110 	.query_format		= cs4281_query_format,
    111 	.set_format		= cs4281_set_format,
    112 	.round_blocksize	= cs428x_round_blocksize,
    113 	.halt_output		= cs4281_halt_output,
    114 	.halt_input		= cs4281_halt_input,
    115 	.getdev			= cs4281_getdev,
    116 	.set_port		= cs428x_mixer_set_port,
    117 	.get_port		= cs428x_mixer_get_port,
    118 	.query_devinfo		= cs428x_query_devinfo,
    119 	.allocm			= cs428x_malloc,
    120 	.freem			= cs428x_free,
    121 	.round_buffersize	= cs428x_round_buffersize,
    122 	.get_props		= cs428x_get_props,
    123 	.trigger_output		= cs4281_trigger_output,
    124 	.trigger_input		= cs4281_trigger_input,
    125 	.get_locks		= cs428x_get_locks,
    126 };
    127 
    128 #if NMIDI > 0 && 0
    129 /* Midi Interface */
    130 static void	cs4281_midi_close(void*);
    131 static void	cs4281_midi_getinfo(void *, struct midi_info *);
    132 static int	cs4281_midi_open(void *, int, void (*)(void *, int),
    133 			 void (*)(void *), void *);
    134 static int	cs4281_midi_output(void *, int);
    135 
    136 static const struct midi_hw_if cs4281_midi_hw_if = {
    137 	cs4281_midi_open,
    138 	cs4281_midi_close,
    139 	cs4281_midi_output,
    140 	cs4281_midi_getinfo,
    141 	0,
    142 	cs428x_get_locks,
    143 };
    144 #endif
    145 
    146 CFATTACH_DECL_NEW(clct, sizeof(struct cs428x_softc),
    147     cs4281_match, cs4281_attach, NULL, NULL);
    148 
    149 static struct audio_device cs4281_device = {
    150 	"CS4281",
    151 	"",
    152 	"cs4281"
    153 };
    154 
    155 static const struct audio_format cs4281_formats[] = {
    156 	{
    157 		.mode		= AUMODE_PLAY | AUMODE_RECORD,
    158 		.encoding	= AUDIO_ENCODING_SLINEAR_NE,
    159 		.validbits	= 16,
    160 		.precision	= 16,
    161 		.channels	= 2,
    162 		.channel_mask	= AUFMT_STEREO,
    163 		.frequency_type	= 6,
    164 		.frequency	= { 8000, 11025, 16000, 22050, 44100, 48000 },
    165 	},
    166 };
    167 #define CS4281_NFORMATS __arraycount(cs4281_formats)
    168 
    169 static int
    170 cs4281_match(device_t parent, cfdata_t match, void *aux)
    171 {
    172 	struct pci_attach_args *pa;
    173 
    174 	pa = (struct pci_attach_args *)aux;
    175 	if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS)
    176 		return 0;
    177 	if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281)
    178 		return 1;
    179 	return 0;
    180 }
    181 
    182 static void
    183 cs4281_attach(device_t parent, device_t self, void *aux)
    184 {
    185 	struct cs428x_softc *sc;
    186 	struct pci_attach_args *pa;
    187 	pci_chipset_tag_t pc;
    188 	char const *intrstr;
    189 	pcireg_t reg;
    190 	int error;
    191 	char intrbuf[PCI_INTRSTR_LEN];
    192 
    193 	sc = device_private(self);
    194 	sc->sc_dev = self;
    195 	pa = (struct pci_attach_args *)aux;
    196 	pc = pa->pa_pc;
    197 
    198 	pci_aprint_devinfo(pa, "Audio controller");
    199 
    200 	sc->sc_pc = pa->pa_pc;
    201 	sc->sc_pt = pa->pa_tag;
    202 
    203 	/* Map I/O register */
    204 	if (pci_mapreg_map(pa, PCI_BA0,
    205 	    PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
    206 	    &sc->ba0t, &sc->ba0h, NULL, NULL)) {
    207 		aprint_error_dev(sc->sc_dev, "can't map BA0 space\n");
    208 		return;
    209 	}
    210 	if (pci_mapreg_map(pa, PCI_BA1,
    211 	    PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
    212 	    &sc->ba1t, &sc->ba1h, NULL, NULL)) {
    213 		aprint_error_dev(sc->sc_dev, "can't map BA1 space\n");
    214 		return;
    215 	}
    216 
    217 	sc->sc_dmatag = pa->pa_dmat;
    218 
    219 	/* power up chip */
    220 	if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self,
    221 	    pci_activate_null)) && error != EOPNOTSUPP) {
    222 		aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error);
    223 		return;
    224 	}
    225 
    226 	/* Enable the device (set bus master flag) */
    227 	reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
    228 	pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
    229 	    reg | PCI_COMMAND_MASTER_ENABLE);
    230 
    231 #if 0
    232 	/* LATENCY_TIMER setting */
    233 	temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
    234 	if (PCI_LATTIMER(temp1) < 32) {
    235 		temp1 &= 0xffff00ff;
    236 		temp1 |= 0x00002000;
    237 		pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1);
    238 	}
    239 #endif
    240 
    241 	/* Map and establish the interrupt. */
    242 	if (pci_intr_map(pa, &sc->intrh)) {
    243 		aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n");
    244 		return;
    245 	}
    246 	intrstr = pci_intr_string(pc, sc->intrh, intrbuf, sizeof(intrbuf));
    247 
    248 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
    249 	mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO);
    250 
    251 	sc->sc_ih = pci_intr_establish_xname(sc->sc_pc, sc->intrh, IPL_AUDIO,
    252 	    cs4281_intr, sc, device_xname(self));
    253 	if (sc->sc_ih == NULL) {
    254 		aprint_error_dev(sc->sc_dev, "couldn't establish interrupt");
    255 		if (intrstr != NULL)
    256 			aprint_error(" at %s", intrstr);
    257 		aprint_error("\n");
    258 		mutex_destroy(&sc->sc_lock);
    259 		mutex_destroy(&sc->sc_intr_lock);
    260 		return;
    261 	}
    262 	aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
    263 
    264 	/*
    265 	 * Sound System start-up
    266 	 */
    267 	if (cs4281_init(sc, 1) != 0) {
    268 		mutex_destroy(&sc->sc_lock);
    269 		mutex_destroy(&sc->sc_intr_lock);
    270 		return;
    271 	}
    272 
    273 	sc->type = TYPE_CS4281;
    274 
    275 	sc->dma_size     = CS4281_BUFFER_SIZE / MAX_CHANNELS;
    276 	sc->dma_align    = 0x10;
    277 	sc->hw_blocksize = sc->dma_size / 2;
    278 
    279 	/* AC 97 attachment */
    280 	sc->host_if.arg = sc;
    281 	sc->host_if.attach = cs428x_attach_codec;
    282 	sc->host_if.read   = cs428x_read_codec;
    283 	sc->host_if.write  = cs428x_write_codec;
    284 	sc->host_if.reset  = cs4281_reset_codec;
    285 	if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) {
    286 		aprint_error_dev(sc->sc_dev, "ac97_attach failed\n");
    287 		mutex_destroy(&sc->sc_lock);
    288 		mutex_destroy(&sc->sc_intr_lock);
    289 		return;
    290 	}
    291 	audio_attach_mi(&cs4281_hw_if, sc, sc->sc_dev);
    292 
    293 #if NMIDI > 0 && 0
    294 	midi_attach_mi(&cs4281_midi_hw_if, sc, sc->sc_dev);
    295 #endif
    296 
    297 	if (!pmf_device_register(self, cs4281_suspend, cs4281_resume))
    298 		aprint_error_dev(self, "couldn't establish power handler\n");
    299 }
    300 
    301 static int
    302 cs4281_intr(void *p)
    303 {
    304 	struct cs428x_softc *sc;
    305 	uint32_t intr, hdsr0, hdsr1;
    306 	char *empty_dma;
    307 	int handled;
    308 
    309 	sc = p;
    310 	handled = 0;
    311 	hdsr0 = 0;
    312 	hdsr1 = 0;
    313 
    314 	mutex_spin_enter(&sc->sc_intr_lock);
    315 
    316 	/* grab interrupt register */
    317 	intr = BA0READ4(sc, CS4281_HISR);
    318 
    319 	DPRINTF(("cs4281_intr:"));
    320 	/* not for me */
    321 	if ((intr & HISR_INTENA) == 0) {
    322 		/* clear the interrupt register */
    323 		BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV);
    324 		mutex_spin_exit(&sc->sc_intr_lock);
    325 		return 0;
    326 	}
    327 
    328 	if (intr & HISR_DMA0)
    329 		hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */
    330 	if (intr & HISR_DMA1)
    331 		hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */
    332 	/* clear the interrupt register */
    333 	BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV);
    334 
    335 #ifdef CS4280_DEBUG
    336 	DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n",
    337 		 intr, hdsr0, hdsr1));
    338 #else
    339 	__USE(hdsr0);
    340 	__USE(hdsr1);
    341 #endif
    342 
    343 	/* Playback Interrupt */
    344 	if (intr & HISR_DMA0) {
    345 		handled = 1;
    346 		if (sc->sc_prun) {
    347 			DPRINTF((" PB DMA 0x%x(%d)",
    348 				(int)BA0READ4(sc, CS4281_DCA0),
    349 				(int)BA0READ4(sc, CS4281_DCC0)));
    350 			if ((sc->sc_pi%sc->sc_pcount) == 0)
    351 				sc->sc_pintr(sc->sc_parg);
    352 			/* copy buffer */
    353 			++sc->sc_pi;
    354 			empty_dma = sc->sc_pdma->addr;
    355 			if (sc->sc_pi&1)
    356 				empty_dma += sc->hw_blocksize;
    357 			memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize);
    358 			sc->sc_pn += sc->hw_blocksize;
    359 			if (sc->sc_pn >= sc->sc_pe)
    360 				sc->sc_pn = sc->sc_ps;
    361 		} else {
    362 			aprint_error_dev(sc->sc_dev, "unexpected play intr\n");
    363 		}
    364 	}
    365 	if (intr & HISR_DMA1) {
    366 		handled = 1;
    367 		if (sc->sc_rrun) {
    368 			/* copy from DMA */
    369 			DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1),
    370 				(int)BA0READ4(sc, CS4281_DCC1)));
    371 			++sc->sc_ri;
    372 			empty_dma = sc->sc_rdma->addr;
    373 			if ((sc->sc_ri & 1) == 0)
    374 				empty_dma += sc->hw_blocksize;
    375 			memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize);
    376 			sc->sc_rn += sc->hw_blocksize;
    377 			if (sc->sc_rn >= sc->sc_re)
    378 				sc->sc_rn = sc->sc_rs;
    379 			if ((sc->sc_ri % sc->sc_rcount) == 0)
    380 				sc->sc_rintr(sc->sc_rarg);
    381 		} else {
    382 			aprint_error_dev(sc->sc_dev,
    383 			    "unexpected record intr\n");
    384 		}
    385 	}
    386 	DPRINTF(("\n"));
    387 
    388 	mutex_spin_exit(&sc->sc_intr_lock);
    389 
    390 	return handled;
    391 }
    392 
    393 static int
    394 cs4281_query_format(void *addr, audio_format_query_t *afp)
    395 {
    396 
    397 	return audio_query_format(cs4281_formats, CS4281_NFORMATS, afp);
    398 }
    399 
    400 static int
    401 cs4281_set_format(void *addr, int setmode,
    402     const audio_params_t *play, const audio_params_t *rec,
    403     audio_filter_reg_t *pfil, audio_filter_reg_t *rfil)
    404 {
    405 	struct cs428x_softc *sc;
    406 
    407 	sc = addr;
    408 	/* set sample rate */
    409 	cs4281_set_dac_rate(sc, play->sample_rate);
    410 	cs4281_set_adc_rate(sc, rec->sample_rate);
    411 	return 0;
    412 }
    413 
    414 static int
    415 cs4281_halt_output(void *addr)
    416 {
    417 	struct cs428x_softc *sc;
    418 
    419 	sc = addr;
    420 	BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK);
    421 	sc->sc_prun = 0;
    422 	return 0;
    423 }
    424 
    425 static int
    426 cs4281_halt_input(void *addr)
    427 {
    428 	struct cs428x_softc *sc;
    429 
    430 	sc = addr;
    431 	BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK);
    432 	sc->sc_rrun = 0;
    433 	return 0;
    434 }
    435 
    436 static int
    437 cs4281_getdev(void *addr, struct audio_device *retp)
    438 {
    439 
    440 	*retp = cs4281_device;
    441 	return 0;
    442 }
    443 
    444 static int
    445 cs4281_trigger_output(void *addr, void *start, void *end, int blksize,
    446 		      void (*intr)(void *), void *arg,
    447 		      const audio_params_t *param)
    448 {
    449 	struct cs428x_softc *sc;
    450 	uint32_t fmt;
    451 	struct cs428x_dma *p;
    452 	int dma_count;
    453 
    454 	sc = addr;
    455 	fmt = 0;
    456 #ifdef DIAGNOSTIC
    457 	if (sc->sc_prun)
    458 		printf("cs4281_trigger_output: already running\n");
    459 #endif
    460 	sc->sc_prun = 1;
    461 
    462 	DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p "
    463 		 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg));
    464 	sc->sc_pintr = intr;
    465 	sc->sc_parg  = arg;
    466 
    467 	/* stop playback DMA */
    468 	BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK);
    469 
    470 	DPRINTF(("param: precision=%d channels=%d encoding=%d\n",
    471 	       param->precision, param->channels, param->encoding));
    472 	for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next)
    473 		continue;
    474 	if (p == NULL) {
    475 		printf("cs4281_trigger_output: bad addr %p\n", start);
    476 		return EINVAL;
    477 	}
    478 
    479 	sc->sc_pcount = blksize / sc->hw_blocksize;
    480 	sc->sc_ps = (char *)start;
    481 	sc->sc_pe = (char *)end;
    482 	sc->sc_pdma = p;
    483 	sc->sc_pbuf = KERNADDR(p);
    484 	sc->sc_pi = 0;
    485 	sc->sc_pn = sc->sc_ps;
    486 	if (blksize >= sc->dma_size) {
    487 		sc->sc_pn = sc->sc_ps + sc->dma_size;
    488 		memcpy(sc->sc_pbuf, start, sc->dma_size);
    489 		++sc->sc_pi;
    490 	} else {
    491 		sc->sc_pn = sc->sc_ps + sc->hw_blocksize;
    492 		memcpy(sc->sc_pbuf, start, sc->hw_blocksize);
    493 	}
    494 
    495 	dma_count = sc->dma_size;
    496 	if (param->precision != 8)
    497 		dma_count /= 2;   /* 16 bit */
    498 	if (param->channels > 1)
    499 		dma_count /= 2;   /* Stereo */
    500 
    501 	DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n",
    502 		 (int)DMAADDR(p), dma_count));
    503 	BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p));
    504 	BA0WRITE4(sc, CS4281_DBC0, dma_count-1);
    505 
    506 	/* set playback format */
    507 	fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK;
    508 	if (param->encoding == AUDIO_ENCODING_SLINEAR_BE)
    509 		fmt |= DMRn_BEND;
    510 	BA0WRITE4(sc, CS4281_DMR0, fmt);
    511 
    512 	/* set sample rate */
    513 	sc->sc_prate = param->sample_rate;
    514 	cs4281_set_dac_rate(sc, param->sample_rate);
    515 
    516 	/* start DMA */
    517 	BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK);
    518 	/* Enable interrupts */
    519 	BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM);
    520 
    521 	DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR)));
    522 	DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR)));
    523 	DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0)));
    524 	DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0)));
    525 	DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0)));
    526 	DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n",
    527 		 BA0READ4(sc, CS4281_DACSR)));
    528 	DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA)));
    529 	DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n",
    530 		 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN));
    531 
    532 	return 0;
    533 }
    534 
    535 static int
    536 cs4281_trigger_input(void *addr, void *start, void *end, int blksize,
    537 		     void (*intr)(void *), void *arg,
    538 		     const audio_params_t *param)
    539 {
    540 	struct cs428x_softc *sc;
    541 	struct cs428x_dma *p;
    542 	uint32_t fmt;
    543 	int dma_count;
    544 
    545 	sc = addr;
    546 	fmt = 0;
    547 #ifdef DIAGNOSTIC
    548 	if (sc->sc_rrun)
    549 		printf("cs4281_trigger_input: already running\n");
    550 #endif
    551 	sc->sc_rrun = 1;
    552 	DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p "
    553 	    "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg));
    554 	sc->sc_rintr = intr;
    555 	sc->sc_rarg  = arg;
    556 
    557 	/* stop recording DMA */
    558 	BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK);
    559 
    560 	for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next)
    561 		continue;
    562 	if (!p) {
    563 		printf("cs4281_trigger_input: bad addr %p\n", start);
    564 		return EINVAL;
    565 	}
    566 
    567 	sc->sc_rcount = blksize / sc->hw_blocksize;
    568 	sc->sc_rs = (char *)start;
    569 	sc->sc_re = (char *)end;
    570 	sc->sc_rdma = p;
    571 	sc->sc_rbuf = KERNADDR(p);
    572 	sc->sc_ri = 0;
    573 	sc->sc_rn = sc->sc_rs;
    574 
    575 	dma_count = sc->dma_size;
    576 	if (param->precision != 8)
    577 		dma_count /= 2;
    578 	if (param->channels > 1)
    579 		dma_count /= 2;
    580 
    581 	DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n",
    582 		 (int)DMAADDR(p), dma_count));
    583 	BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p));
    584 	BA0WRITE4(sc, CS4281_DBC1, dma_count-1);
    585 
    586 	/* set recording format */
    587 	fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK;
    588 	if (param->encoding == AUDIO_ENCODING_SLINEAR_BE)
    589 		fmt |= DMRn_BEND;
    590 	BA0WRITE4(sc, CS4281_DMR1, fmt);
    591 
    592 	/* set sample rate */
    593 	sc->sc_rrate = param->sample_rate;
    594 	cs4281_set_adc_rate(sc, param->sample_rate);
    595 
    596 	/* Start DMA */
    597 	BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK);
    598 	/* Enable interrupts */
    599 	BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM);
    600 
    601 	DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR)));
    602 	DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR)));
    603 	DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1)));
    604 	DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1)));
    605 
    606 	return 0;
    607 }
    608 
    609 static bool
    610 cs4281_suspend(device_t dv, const pmf_qual_t *qual)
    611 {
    612 	struct cs428x_softc *sc = device_private(dv);
    613 
    614 	mutex_enter(&sc->sc_lock);
    615 	mutex_spin_enter(&sc->sc_intr_lock);
    616 
    617 	/* save current playback status */
    618 	if (sc->sc_prun) {
    619 		sc->sc_suspend_state.cs4281.dcr0 = BA0READ4(sc, CS4281_DCR0);
    620 		sc->sc_suspend_state.cs4281.dmr0 = BA0READ4(sc, CS4281_DMR0);
    621 		sc->sc_suspend_state.cs4281.dbc0 = BA0READ4(sc, CS4281_DBC0);
    622 		sc->sc_suspend_state.cs4281.dba0 = BA0READ4(sc, CS4281_DBA0);
    623 	}
    624 
    625 	/* save current capture status */
    626 	if (sc->sc_rrun) {
    627 		sc->sc_suspend_state.cs4281.dcr1 = BA0READ4(sc, CS4281_DCR1);
    628 		sc->sc_suspend_state.cs4281.dmr1 = BA0READ4(sc, CS4281_DMR1);
    629 		sc->sc_suspend_state.cs4281.dbc1 = BA0READ4(sc, CS4281_DBC1);
    630 		sc->sc_suspend_state.cs4281.dba1 = BA0READ4(sc, CS4281_DBA1);
    631 	}
    632 	/* Stop DMA */
    633 	BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK);
    634 	BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK);
    635 
    636 	mutex_spin_exit(&sc->sc_intr_lock);
    637 	mutex_exit(&sc->sc_lock);
    638 
    639 	return true;
    640 }
    641 
    642 static bool
    643 cs4281_resume(device_t dv, const pmf_qual_t *qual)
    644 {
    645 	struct cs428x_softc *sc = device_private(dv);
    646 
    647 	mutex_enter(&sc->sc_lock);
    648 	mutex_spin_enter(&sc->sc_intr_lock);
    649 
    650 	cs4281_init(sc, 0);
    651 	cs4281_reset_codec(sc);
    652 
    653 	/* restore ac97 registers */
    654 	mutex_spin_exit(&sc->sc_intr_lock);
    655 	(*sc->codec_if->vtbl->restore_ports)(sc->codec_if);
    656 	mutex_spin_enter(&sc->sc_intr_lock);
    657 
    658 	/* restore DMA related status */
    659 	if (sc->sc_prun) {
    660 		cs4281_set_dac_rate(sc, sc->sc_prate);
    661 		BA0WRITE4(sc, CS4281_DBA0, sc->sc_suspend_state.cs4281.dba0);
    662 		BA0WRITE4(sc, CS4281_DBC0, sc->sc_suspend_state.cs4281.dbc0);
    663 		BA0WRITE4(sc, CS4281_DMR0, sc->sc_suspend_state.cs4281.dmr0);
    664 		BA0WRITE4(sc, CS4281_DCR0, sc->sc_suspend_state.cs4281.dcr0);
    665 	}
    666 	if (sc->sc_rrun) {
    667 		cs4281_set_adc_rate(sc, sc->sc_rrate);
    668 		BA0WRITE4(sc, CS4281_DBA1, sc->sc_suspend_state.cs4281.dba1);
    669 		BA0WRITE4(sc, CS4281_DBC1, sc->sc_suspend_state.cs4281.dbc1);
    670 		BA0WRITE4(sc, CS4281_DMR1, sc->sc_suspend_state.cs4281.dmr1);
    671 		BA0WRITE4(sc, CS4281_DCR1, sc->sc_suspend_state.cs4281.dcr1);
    672 	}
    673 	/* enable interrupts */
    674 	if (sc->sc_prun || sc->sc_rrun)
    675 		BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM);
    676 
    677 	mutex_spin_exit(&sc->sc_intr_lock);
    678 	mutex_exit(&sc->sc_lock);
    679 
    680 	return true;
    681 }
    682 
    683 /* control AC97 codec */
    684 static int
    685 cs4281_reset_codec(void *addr)
    686 {
    687 	struct cs428x_softc *sc;
    688 	uint16_t data;
    689 	uint32_t dat32;
    690 	int n;
    691 
    692 	sc = addr;
    693 
    694 	DPRINTFN(3, ("cs4281_reset_codec\n"));
    695 
    696 	/* Reset codec */
    697 	BA0WRITE4(sc, CS428X_ACCTL, 0);
    698 	delay(50);    /* delay 50us */
    699 
    700 	BA0WRITE4(sc, CS4281_SPMC, 0);
    701 	delay(100);	/* delay 100us */
    702 	BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN);
    703 #if defined(ENABLE_SECONDARY_CODEC)
    704 	BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E);
    705 	BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID);
    706 #endif
    707 	delay(50000);   /* XXX: delay 50ms */
    708 
    709 	/* Enable ASYNC generation */
    710 	BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN);
    711 
    712 	/* Wait for codec ready. Linux driver waits 50ms here */
    713 	n = 0;
    714 	while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) {
    715 		delay(100);
    716 		if (++n > 1000) {
    717 			printf("reset_codec: AC97 codec ready timeout\n");
    718 			return ETIMEDOUT;
    719 		}
    720 	}
    721 #if defined(ENABLE_SECONDARY_CODEC)
    722 	/* secondary codec ready*/
    723 	n = 0;
    724 	while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) {
    725 		delay(100);
    726 		if (++n > 1000)
    727 			return 0;
    728 	}
    729 #endif
    730 	/* Set the serial timing configuration */
    731 	/* XXX: undocumented but the Linux driver do this */
    732 	BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97);
    733 
    734 	/* Wait for codec ready signal */
    735 	n = 0;
    736 	do {
    737 		delay(1000);
    738 		if (++n > 1000) {
    739 			aprint_error_dev(sc->sc_dev,
    740 			    "timeout waiting for codec ready\n");
    741 			return ETIMEDOUT;
    742 		}
    743 		dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY;
    744 	} while (dat32 == 0);
    745 
    746 	/* Enable Valid Frame output on ASDOUT */
    747 	BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM);
    748 
    749 	/* Wait until codec calibration is finished. Codec register 26h */
    750 	n = 0;
    751 	do {
    752 		delay(1);
    753 		if (++n > 1000) {
    754 			aprint_error_dev(sc->sc_dev,
    755 			    "timeout waiting for codec calibration\n");
    756 			return ETIMEDOUT;
    757 		}
    758 		cs428x_read_codec(sc, AC97_REG_POWER, &data);
    759 	} while ((data & 0x0f) != 0x0f);
    760 
    761 	/* Set the serial timing configuration again */
    762 	/* XXX: undocumented but the Linux driver do this */
    763 	BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97);
    764 
    765 	/* Wait until we've sampled input slots 3 & 4 as valid */
    766 	n = 0;
    767 	do {
    768 		delay(1000);
    769 		if (++n > 1000) {
    770 			aprint_error_dev(sc->sc_dev, "timeout waiting for "
    771 			    "sampled input slots as valid\n");
    772 			return ETIMEDOUT;
    773 		}
    774 		dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ;
    775 	} while (dat32 != (ACISV_ISV3 | ACISV_ISV4));
    776 
    777 	/* Start digital data transfer of audio data to the codec */
    778 	BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4));
    779 	return 0;
    780 }
    781 
    782 
    783 /* Internal functions */
    784 
    785 /* convert sample rate to register value */
    786 static uint8_t
    787 cs4281_sr2regval(int rate)
    788 {
    789 	uint8_t retval;
    790 
    791 	/* We don't have to change here. but anyway ... */
    792 	if (rate > 48000)
    793 		rate = 48000;
    794 	if (rate < 6023)
    795 		rate = 6023;
    796 
    797 	switch (rate) {
    798 	case 8000:
    799 		retval = 5;
    800 		break;
    801 	case 11025:
    802 		retval = 4;
    803 		break;
    804 	case 16000:
    805 		retval = 3;
    806 		break;
    807 	case 22050:
    808 		retval = 2;
    809 		break;
    810 	case 44100:
    811 		retval = 1;
    812 		break;
    813 	case 48000:
    814 		retval = 0;
    815 		break;
    816 	default:
    817 		retval = 1536000/rate; /* == 24576000/(rate*16) */
    818 	}
    819 	return retval;
    820 }
    821 
    822 static void
    823 cs4281_set_adc_rate(struct cs428x_softc *sc, int rate)
    824 {
    825 
    826 	BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate));
    827 }
    828 
    829 static void
    830 cs4281_set_dac_rate(struct cs428x_softc *sc, int rate)
    831 {
    832 
    833 	BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate));
    834 }
    835 
    836 static int
    837 cs4281_init(struct cs428x_softc *sc, int init)
    838 {
    839 	int n;
    840 	uint16_t data;
    841 	uint32_t dat32;
    842 
    843 	/* set "Configuration Write Protect" register to
    844 	 * 0x4281 to allow to write */
    845 	BA0WRITE4(sc, CS4281_CWPR, 0x4281);
    846 
    847 	/*
    848 	 * Unset "Full Power-Down bit of Extended PCI Power Management
    849 	 * Control" register to release the reset state.
    850 	 */
    851 	dat32 = BA0READ4(sc, CS4281_EPPMC);
    852 	if (dat32 & EPPMC_FPDN) {
    853 		BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN);
    854 	}
    855 
    856 	/* Start PLL out in known state */
    857 	BA0WRITE4(sc, CS4281_CLKCR1, 0);
    858 	/* Start serial ports out in known state */
    859 	BA0WRITE4(sc, CS4281_SERMC, 0);
    860 
    861 	/* Reset codec */
    862 	BA0WRITE4(sc, CS428X_ACCTL, 0);
    863 	delay(50);	/* delay 50us */
    864 
    865 	BA0WRITE4(sc, CS4281_SPMC, 0);
    866 	delay(100);	/* delay 100us */
    867 	BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN);
    868 #if defined(ENABLE_SECONDARY_CODEC)
    869 	BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E);
    870 	BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID);
    871 #endif
    872 	delay(50000);   /* XXX: delay 50ms */
    873 
    874 	/* Turn on Sound System clocks based on ABITCLK */
    875 	BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP);
    876 	delay(50000);   /* XXX: delay 50ms */
    877 	BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP);
    878 
    879 	/* Set enables for sections that are needed in the SSPM registers */
    880 	BA0WRITE4(sc, CS4281_SSPM,
    881 		  SSPM_MIXEN |		/* Mixer */
    882 		  SSPM_CSRCEN |		/* Capture SRC */
    883 		  SSPM_PSRCEN |		/* Playback SRC */
    884 		  SSPM_JSEN |		/* Joystick */
    885 		  SSPM_ACLEN |		/* AC LINK */
    886 		  SSPM_FMEN		/* FM */
    887 		  );
    888 
    889 	/* Wait for clock stabilization */
    890 	n = 0;
    891 #if 1
    892 	/* what document says */
    893 	while ((BA0READ4(sc, CS4281_CLKCR1) & (CLKCR1_DLLRDY | CLKCR1_CLKON))
    894 		 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) {
    895 		delay(100);
    896 		if (++n > 1000) {
    897 			aprint_error_dev(sc->sc_dev,
    898 			    "timeout waiting for clock stabilization\n");
    899 			return -1;
    900 		}
    901 	}
    902 #else
    903 	/* Cirrus driver for Linux does */
    904 	while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) {
    905 		delay(1000);
    906 		if (++n > 1000) {
    907 			aprint_error_dev(sc->sc_dev,
    908 			    "timeout waiting for clock stabilization\n");
    909 			return -1;
    910 		}
    911 	}
    912 #endif
    913 
    914 	/* Enable ASYNC generation */
    915 	BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN);
    916 
    917 	/* Wait for codec ready. Linux driver waits 50ms here */
    918 	n = 0;
    919 	while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) {
    920 		delay(100);
    921 		if (++n > 1000) {
    922 			aprint_error_dev(sc->sc_dev,
    923 			    "timeout waiting for codec ready\n");
    924 			return -1;
    925 		}
    926 	}
    927 
    928 #if defined(ENABLE_SECONDARY_CODEC)
    929 	/* secondary codec ready*/
    930 	n = 0;
    931 	while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) {
    932 		delay(100);
    933 		if (++n > 1000) {
    934 			aprint_error_dev(sc->sc_dev,
    935 			    "timeout waiting for secondary codec ready\n");
    936 			return -1;
    937 		}
    938 	}
    939 #endif
    940 
    941 	/* Set the serial timing configuration */
    942 	/* XXX: undocumented but the Linux driver do this */
    943 	BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97);
    944 
    945 	/* Wait for codec ready signal */
    946 	n = 0;
    947 	do {
    948 		delay(1000);
    949 		if (++n > 1000) {
    950 			aprint_error_dev(sc->sc_dev,
    951 			    "timeout waiting for codec ready\n");
    952 			return -1;
    953 		}
    954 		dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY;
    955 	} while (dat32 == 0);
    956 
    957 	/* Enable Valid Frame output on ASDOUT */
    958 	BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM);
    959 
    960 	/* Wait until codec calibration is finished. codec register 26h */
    961 	n = 0;
    962 	do {
    963 		delay(1);
    964 		if (++n > 1000) {
    965 			aprint_error_dev(sc->sc_dev,
    966 			    "timeout waiting for codec calibration\n");
    967 			return -1;
    968 		}
    969 		cs428x_read_codec(sc, AC97_REG_POWER, &data);
    970 	} while ((data & 0x0f) != 0x0f);
    971 
    972 	/* Set the serial timing configuration again */
    973 	/* XXX: undocumented but the Linux driver do this */
    974 	BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97);
    975 
    976 	/* Wait until we've sampled input slots 3 & 4 as valid */
    977 	n = 0;
    978 	do {
    979 		delay(1000);
    980 		if (++n > 1000) {
    981 			aprint_error_dev(sc->sc_dev, "timeout waiting for "
    982 			    "sampled input slots as valid\n");
    983 			return -1;
    984 		}
    985 		dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4);
    986 	} while (dat32 != (ACISV_ISV3 | ACISV_ISV4));
    987 
    988 	/* Start digital data transfer of audio data to the codec */
    989 	BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4));
    990 
    991 	cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0);
    992 	cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0);
    993 
    994 	/* Power on the DAC */
    995 	cs428x_read_codec(sc, AC97_REG_POWER, &data);
    996 	cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff);
    997 
    998 	/* Wait until we sample a DAC ready state.
    999 	 * Not documented, but Linux driver does.
   1000 	 */
   1001 	for (n = 0; n < 32; ++n) {
   1002 		delay(1000);
   1003 		cs428x_read_codec(sc, AC97_REG_POWER, &data);
   1004 		if (data & 0x02)
   1005 			break;
   1006 	}
   1007 
   1008 	/* Power on the ADC */
   1009 	cs428x_read_codec(sc, AC97_REG_POWER, &data);
   1010 	cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff);
   1011 
   1012 	/* Wait until we sample ADC ready state.
   1013 	 * Not documented, but Linux driver does.
   1014 	 */
   1015 	for (n = 0; n < 32; ++n) {
   1016 		delay(1000);
   1017 		cs428x_read_codec(sc, AC97_REG_POWER, &data);
   1018 		if (data & 0x01)
   1019 			break;
   1020 	}
   1021 
   1022 #if 0
   1023 	/* Initialize AC-Link features */
   1024 	/* variable sample-rate support */
   1025 	mem = BA0READ4(sc, CS4281_SERMC);
   1026 	mem |=  (SERMC_ODSEN1 | SERMC_ODSEN2);
   1027 	BA0WRITE4(sc, CS4281_SERMC, mem);
   1028 	/* XXX: more... */
   1029 
   1030 	/* Initialize SSCR register features */
   1031 	/* XXX: hardware volume setting */
   1032 	BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */
   1033 #endif
   1034 
   1035 	/* disable Sound Blaster Pro emulation */
   1036 	/* XXX:
   1037 	 * Cannot set since the documents does not describe which bit is
   1038 	 * correspond to SSCR_SB. Since the reset value of SSCR is 0,
   1039 	 * we can ignore it.*/
   1040 #if 0
   1041 	BA0WRITE4(sc, CS4281_SSCR, SSCR_SB);
   1042 #endif
   1043 
   1044 	/* map AC97 PCM playback to DMA Channel 0 */
   1045 	/* Reset FEN bit to setup first */
   1046 	BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN));
   1047 	/*
   1048 	 *| RS[4:0]/|        |
   1049 	 *| LS[4:0] |  AC97  | Slot Function
   1050 	 *|---------+--------+--------------------
   1051 	 *|     0   |    3   | Left PCM Playback
   1052 	 *|     1   |    4   | Right PCM Playback
   1053 	 *|     2   |    5   | Phone Line 1 DAC
   1054 	 *|     3   |    6   | Center PCM Playback
   1055 	 *....
   1056 	 *  quoted from Table 29(p109)
   1057 	 */
   1058 	dat32 = 0x01 << 24 |   /* RS[4:0] =  1 see above */
   1059 		0x00 << 16 |   /* LS[4:0] =  0 see above */
   1060 		0x0f <<  8 |   /* SZ[6:0] = 15 size of buffer */
   1061 		0x00 <<  0 ;   /* OF[6:0] =  0 offset */
   1062 	BA0WRITE4(sc, CS4281_FCR0, dat32);
   1063 	BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN);
   1064 
   1065 	/* map AC97 PCM record to DMA Channel 1 */
   1066 	/* Reset FEN bit to setup first */
   1067 	BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN));
   1068 	/*
   1069 	 *| RS[4:0]/|
   1070 	 *| LS[4:0] | AC97 | Slot Function
   1071 	 *|---------+------+-------------------
   1072 	 *|   10    |   3  | Left PCM Record
   1073 	 *|   11    |   4  | Right PCM Record
   1074 	 *|   12    |   5  | Phone Line 1 ADC
   1075 	 *|   13    |   6  | Mic ADC
   1076 	 *....
   1077 	 * quoted from Table 30(p109)
   1078 	 */
   1079 	dat32 = 0x0b << 24 |    /* RS[4:0] = 11 See above */
   1080 		0x0a << 16 |    /* LS[4:0] = 10 See above */
   1081 		0x0f <<  8 |    /* SZ[6:0] = 15 Size of buffer */
   1082 		0x10 <<  0 ;    /* OF[6:0] = 16 offset */
   1083 
   1084 	/* XXX: I cannot understand why FCRn_PSH is needed here. */
   1085 	BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH);
   1086 	BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN);
   1087 
   1088 #if 0
   1089 	/* Disable DMA Channel 2, 3 */
   1090 	BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN));
   1091 	BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN));
   1092 #endif
   1093 
   1094 	/* Set the SRC Slot Assignment accordingly */
   1095 	/*| PLSS[4:0]/
   1096 	 *| PRSS[4:0] | AC97 | Slot Function
   1097 	 *|-----------+------+----------------
   1098 	 *|     0     |  3   | Left PCM Playback
   1099 	 *|     1     |  4   | Right PCM Playback
   1100 	 *|     2     |  5   | phone line 1 DAC
   1101 	 *|     3     |  6   | Center PCM Playback
   1102 	 *|     4     |  7   | Left Surround PCM Playback
   1103 	 *|     5     |  8   | Right Surround PCM Playback
   1104 	 *......
   1105 	 *
   1106 	 *| CLSS[4:0]/
   1107 	 *| CRSS[4:0] | AC97 | Codec |Slot Function
   1108 	 *|-----------+------+-------+-----------------
   1109 	 *|    10     |   3  |Primary| Left PCM Record
   1110 	 *|    11     |   4  |Primary| Right PCM Record
   1111 	 *|    12     |   5  |Primary| Phone Line 1 ADC
   1112 	 *|    13     |   6  |Primary| Mic ADC
   1113 	 *|.....
   1114 	 *|    20     |   3  |  Sec. | Left PCM Record
   1115 	 *|    21     |   4  |  Sec. | Right PCM Record
   1116 	 *|    22     |   5  |  Sec. | Phone Line 1 ADC
   1117 	 *|    23     |   6  |  Sec. | Mic ADC
   1118 	 */
   1119 	dat32 = 0x0b << 24 |   /* CRSS[4:0] Right PCM Record(primary) */
   1120 		0x0a << 16 |   /* CLSS[4:0] Left  PCM Record(primary) */
   1121 		0x01 <<  8 |   /* PRSS[4:0] Right PCM Playback */
   1122 		0x00 <<  0;    /* PLSS[4:0] Left  PCM Playback */
   1123 	BA0WRITE4(sc, CS4281_SRCSA, dat32);
   1124 
   1125 	/* Set interrupt to occurred at Half and Full terminal
   1126 	 * count interrupt enable for DMA channel 0 and 1.
   1127 	 * To keep DMA stop, set MSK.
   1128 	 */
   1129 	dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK;
   1130 	BA0WRITE4(sc, CS4281_DCR0, dat32);
   1131 	BA0WRITE4(sc, CS4281_DCR1, dat32);
   1132 
   1133 	/* Set Auto-Initialize Control enable */
   1134 	BA0WRITE4(sc, CS4281_DMR0,
   1135 		  DMRn_DMA | DMRn_AUTO | DMRn_TR_READ);
   1136 	BA0WRITE4(sc, CS4281_DMR1,
   1137 		  DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE);
   1138 
   1139 	/* Clear DMA Mask in HIMR */
   1140 	dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM;
   1141 	BA0WRITE4(sc, CS4281_HIMR,
   1142 		  BA0READ4(sc, CS4281_HIMR) & dat32);
   1143 
   1144 	/* set current status */
   1145 	if (init != 0) {
   1146 		sc->sc_prun = 0;
   1147 		sc->sc_rrun = 0;
   1148 	}
   1149 
   1150 	/* setup playback volume */
   1151 	BA0WRITE4(sc, CS4281_PPRVC, 7);
   1152 	BA0WRITE4(sc, CS4281_PPLVC, 7);
   1153 
   1154 	return 0;
   1155 }
   1156