1 /* $NetBSD: zsvar.h,v 1.7 2022/01/17 20:56:02 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)zsvar.h 8.1 (Berkeley) 6/11/93 41 */ 42 43 /* 44 * Register layout is machine-dependent... 45 */ 46 47 struct zschan { 48 volatile uint8_t zc_csr; /* ctrl,status, and indirect access */ 49 uint8_t zc_xxx0; 50 volatile uint8_t zc_data; /* data */ 51 uint8_t zc_xxx1; 52 }; 53 54 struct zsdevice { 55 struct zschan zs_chan[2]; 56 }; 57 58 /* 59 * Software state, per zs channel. 60 * 61 * The zs chip has insufficient buffering, so we provide a software 62 * buffer using a two-level interrupt scheme. The hardware (high priority) 63 * interrupt simply grabs the `cause' of the interrupt and stuffs it into 64 * a ring buffer. It then schedules a software interrupt; the latter 65 * empties the ring as fast as it can, hoping to avoid overflow. 66 * 67 * Interrupts can happen because of: 68 * - received data; 69 * - transmit pseudo-DMA done; and 70 * - status change. 71 * These are all stored together in the (single) ring. The size of the 72 * ring is a power of two, to make % operations fast. Since we need two 73 * bits to distinguish the interrupt type, and up to 16 for the received 74 * data plus RR1 status, we use 32 bits per ring entry. 75 * 76 * When the value is a character + RR1 status, the character is in the 77 * upper 8 bits of the RR1 status. 78 */ 79 80 /* 0 is reserved (means "no interrupt") */ 81 #define ZRING_RINT 1 /* receive data interrupt */ 82 #define ZRING_XINT 2 /* transmit done interrupt */ 83 #define ZRING_SINT 3 /* status change interrupt */ 84 85 #define ZRING_TYPE(x) ((x) & 3) 86 #define ZRING_VALUE(x) ((x) >> 8) 87 #define ZRING_MAKE(t, v) ((t) | (v) << 8) 88 89 /* forward decl */ 90 struct zs_softc; 91 92 struct zs_chanstate { 93 struct zs_chanstate *cs_next; /* linked list for zshard() */ 94 struct zs_softc *cs_sc; /* pointer to softc */ 95 volatile struct zschan *cs_zc; /* points to hardware regs */ 96 struct tty *cs_ttyp; /* ### */ 97 int cs_unit; /* unit number */ 98 99 /* 100 * We must keep a copy of the write registers as they are 101 * mostly write-only and we sometimes need to set and clear 102 * individual bits (e.g., in WR3). Not all of these are 103 * needed but 16 bytes is cheap and this makes the addressing 104 * simpler. Unfortunately, we can only write to some registers 105 * when the chip is not actually transmitting, so whenever 106 * we are expecting a `transmit done' interrupt the preg array 107 * is allowed to `get ahead' of the current values. In a 108 * few places we must change the current value of a register, 109 * rather than (or in addition to) the pending value; for these 110 * cs_creg[] contains the current value. 111 */ 112 uint8_t cs_creg[16]; /* current values */ 113 uint8_t cs_preg[16]; /* pending values */ 114 uint8_t cs_heldchange; /* change pending (creg != preg) */ 115 uint8_t cs_rr0; /* last rr0 processed */ 116 117 /* pure software data, per channel */ 118 char cs_softcar; /* software carrier */ 119 char cs_conk; /* is console keyboard, decode L1-A */ 120 char cs_brkabort; /* abort (as if via L1-A) on BREAK */ 121 char cs_kgdb; /* enter debugger on frame char */ 122 char cs_consio; /* port does /dev/console I/O */ 123 char cs_xxx; /* (spare) */ 124 int cs_speed; /* default baud rate (from ROM) */ 125 126 /* 127 * The transmit byte count and address are used for pseudo-DMA 128 * output in the hardware interrupt code. PDMA can be suspended 129 * to get pending changes done; heldtbc is used for this. It can 130 * also be stopped for ^S; this sets TS_TTSTOP in tp->t_state. 131 */ 132 int cs_tbc; /* transmit byte count */ 133 int cs_heldtbc; /* held tbc while xmission stopped */ 134 void * cs_tba; /* transmit buffer address */ 135 136 /* 137 * Printing an overrun error message often takes long enough to 138 * cause another overrun, so we only print one per second. 139 */ 140 long cs_rotime; /* time of last ring overrun */ 141 long cs_fotime; /* time of last fifo overrun */ 142 143 /* 144 * The ring buffer. 145 */ 146 u_int cs_rbget; /* ring buffer `get' index */ 147 volatile u_int cs_rbput; /* ring buffer `put' index */ 148 u_int cs_ringmask; /* mask, reflecting size of `rbuf' */ 149 int *cs_rbuf; /* type, value pairs */ 150 }; 151 152 /* 153 * N.B.: the keyboard is channel 1, the mouse channel 0; ttyb is 1, ttya 154 * is 0. In other words, the things are BACKWARDS. 155 */ 156 #define ZS_CHAN_A 1 157 #define ZS_CHAN_B 0 158 159 /* 160 * Macros to read and write individual registers (except 0) in a channel. 161 * 162 * On the SparcStation the 1.6 microsecond recovery time is 163 * handled in hardware. On the older Sun4 machine it isn't, and 164 * software must deal with the problem. 165 * 166 * However, it *is* a problem on some Sun4m's (i.e. the SS20) (XXX: why?). 167 * Thus we leave in the delay. 168 * 169 * XXX: (ABB) Think about this more. 170 */ 171 #if 0 172 173 #define ZS_READ(c, r) zs_read(c, r) 174 #define ZS_WRITE(c, r, v) zs_write(c, r, v) 175 /*#define ZS_DELAY() (CPU_ISSUN4C ? (0) : delay(1))*/ 176 #define ZS_DELAY() (delay(1)) 177 178 #else /* SUN4 */ 179 180 #define ZS_READ(c, r) ((c)->zc_csr = (r), (c)->zc_csr) 181 #define ZS_WRITE(c, r, v) ((c)->zc_csr = (r), (c)->zc_csr = (v)) 182 /* #define ZS_DELAY() (CPU_ISSUN4M ? delay(1) : 0) */ 183 #define ZS_DELAY() (0) 184 185 #endif /* SUN4 */ 186
Indexes created Fri Sep 26 08:10:20 GMT 2025