1 /* $NetBSD: satalink.c,v 1.59 2026/06/14 15:06:19 rkujawa Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: satalink.c,v 1.59 2026/06/14 15:06:19 rkujawa Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_sii3112_reg.h> 43 44 #include <dev/ata/satareg.h> 45 #include <dev/ata/satavar.h> 46 #include <dev/ata/atareg.h> 47 48 /* 49 * Register map for BA5 register space, indexed by channel. 50 */ 51 static const struct { 52 bus_addr_t ba5_IDEDMA_CMD; 53 bus_addr_t ba5_IDEDMA_CTL; 54 bus_addr_t ba5_IDEDMA_TBL; 55 bus_addr_t ba5_IDEDMA_CMD2; 56 bus_addr_t ba5_IDEDMA_CTL2; 57 bus_addr_t ba5_IDE_TF0; 58 bus_addr_t ba5_IDE_TF1; 59 bus_addr_t ba5_IDE_TF2; 60 bus_addr_t ba5_IDE_TF3; 61 bus_addr_t ba5_IDE_TF4; 62 bus_addr_t ba5_IDE_TF5; 63 bus_addr_t ba5_IDE_TF6; 64 bus_addr_t ba5_IDE_TF7; 65 bus_addr_t ba5_IDE_TF8; 66 bus_addr_t ba5_IDE_RAD; 67 bus_addr_t ba5_IDE_TF9; 68 bus_addr_t ba5_IDE_TF10; 69 bus_addr_t ba5_IDE_TF11; 70 bus_addr_t ba5_IDE_TF12; 71 bus_addr_t ba5_IDE_TF13; 72 bus_addr_t ba5_IDE_TF14; 73 bus_addr_t ba5_IDE_TF15; 74 bus_addr_t ba5_IDE_TF16; 75 bus_addr_t ba5_IDE_TF17; 76 bus_addr_t ba5_IDE_TF18; 77 bus_addr_t ba5_IDE_TF19; 78 bus_addr_t ba5_IDE_RABC; 79 bus_addr_t ba5_IDE_CMD_STS; 80 bus_addr_t ba5_IDE_CFG_STS; 81 bus_addr_t ba5_IDE_DTM; 82 bus_addr_t ba5_SControl; 83 bus_addr_t ba5_SStatus; 84 bus_addr_t ba5_SError; 85 bus_addr_t ba5_SActive; /* 3114 */ 86 bus_addr_t ba5_SMisc; 87 bus_addr_t ba5_PHY_CONFIG; 88 bus_addr_t ba5_SIEN; 89 bus_addr_t ba5_SFISCfg; 90 } satalink_ba5_regmap[] = { 91 { /* Channel 0 */ 92 .ba5_IDEDMA_CMD = 0x000, 93 .ba5_IDEDMA_CTL = 0x002, 94 .ba5_IDEDMA_TBL = 0x004, 95 .ba5_IDEDMA_CMD2 = 0x010, 96 .ba5_IDEDMA_CTL2 = 0x012, 97 .ba5_IDE_TF0 = 0x080, /* wd_data */ 98 .ba5_IDE_TF1 = 0x081, /* wd_error */ 99 .ba5_IDE_TF2 = 0x082, /* wd_seccnt */ 100 .ba5_IDE_TF3 = 0x083, /* wd_sector */ 101 .ba5_IDE_TF4 = 0x084, /* wd_cyl_lo */ 102 .ba5_IDE_TF5 = 0x085, /* wd_cyl_hi */ 103 .ba5_IDE_TF6 = 0x086, /* wd_sdh */ 104 .ba5_IDE_TF7 = 0x087, /* wd_command */ 105 .ba5_IDE_TF8 = 0x08a, /* wd_altsts */ 106 .ba5_IDE_RAD = 0x08c, 107 .ba5_IDE_TF9 = 0x091, /* Features 2 */ 108 .ba5_IDE_TF10 = 0x092, /* Sector Count 2 */ 109 .ba5_IDE_TF11 = 0x093, /* Start Sector 2 */ 110 .ba5_IDE_TF12 = 0x094, /* Cylinder Low 2 */ 111 .ba5_IDE_TF13 = 0x095, /* Cylinder High 2 */ 112 .ba5_IDE_TF14 = 0x096, /* Device/Head 2 */ 113 .ba5_IDE_TF15 = 0x097, /* Cmd Sts 2 */ 114 .ba5_IDE_TF16 = 0x098, /* Sector Count 2 ext */ 115 .ba5_IDE_TF17 = 0x099, /* Start Sector 2 ext */ 116 .ba5_IDE_TF18 = 0x09a, /* Cyl Low 2 ext */ 117 .ba5_IDE_TF19 = 0x09b, /* Cyl High 2 ext */ 118 .ba5_IDE_RABC = 0x09c, 119 .ba5_IDE_CMD_STS = 0x0a0, 120 .ba5_IDE_CFG_STS = 0x0a1, 121 .ba5_IDE_DTM = 0x0b4, 122 .ba5_SControl = 0x100, 123 .ba5_SStatus = 0x104, 124 .ba5_SError = 0x108, 125 .ba5_SActive = 0x10c, 126 .ba5_SMisc = 0x140, 127 .ba5_PHY_CONFIG = 0x144, 128 .ba5_SIEN = 0x148, 129 .ba5_SFISCfg = 0x14c, 130 }, 131 { /* Channel 1 */ 132 .ba5_IDEDMA_CMD = 0x008, 133 .ba5_IDEDMA_CTL = 0x00a, 134 .ba5_IDEDMA_TBL = 0x00c, 135 .ba5_IDEDMA_CMD2 = 0x018, 136 .ba5_IDEDMA_CTL2 = 0x01a, 137 .ba5_IDE_TF0 = 0x0c0, /* wd_data */ 138 .ba5_IDE_TF1 = 0x0c1, /* wd_error */ 139 .ba5_IDE_TF2 = 0x0c2, /* wd_seccnt */ 140 .ba5_IDE_TF3 = 0x0c3, /* wd_sector */ 141 .ba5_IDE_TF4 = 0x0c4, /* wd_cyl_lo */ 142 .ba5_IDE_TF5 = 0x0c5, /* wd_cyl_hi */ 143 .ba5_IDE_TF6 = 0x0c6, /* wd_sdh */ 144 .ba5_IDE_TF7 = 0x0c7, /* wd_command */ 145 .ba5_IDE_TF8 = 0x0ca, /* wd_altsts */ 146 .ba5_IDE_RAD = 0x0cc, 147 .ba5_IDE_TF9 = 0x0d1, /* Features 2 */ 148 .ba5_IDE_TF10 = 0x0d2, /* Sector Count 2 */ 149 .ba5_IDE_TF11 = 0x0d3, /* Start Sector 2 */ 150 .ba5_IDE_TF12 = 0x0d4, /* Cylinder Low 2 */ 151 .ba5_IDE_TF13 = 0x0d5, /* Cylinder High 2 */ 152 .ba5_IDE_TF14 = 0x0d6, /* Device/Head 2 */ 153 .ba5_IDE_TF15 = 0x0d7, /* Cmd Sts 2 */ 154 .ba5_IDE_TF16 = 0x0d8, /* Sector Count 2 ext */ 155 .ba5_IDE_TF17 = 0x0d9, /* Start Sector 2 ext */ 156 .ba5_IDE_TF18 = 0x0da, /* Cyl Low 2 ext */ 157 .ba5_IDE_TF19 = 0x0db, /* Cyl High 2 ext */ 158 .ba5_IDE_RABC = 0x0dc, 159 .ba5_IDE_CMD_STS = 0x0e0, 160 .ba5_IDE_CFG_STS = 0x0e1, 161 .ba5_IDE_DTM = 0x0f4, 162 .ba5_SControl = 0x180, 163 .ba5_SStatus = 0x184, 164 .ba5_SError = 0x188, 165 .ba5_SActive = 0x18c, 166 .ba5_SMisc = 0x1c0, 167 .ba5_PHY_CONFIG = 0x1c4, 168 .ba5_SIEN = 0x1c8, 169 .ba5_SFISCfg = 0x1cc, 170 }, 171 { /* Channel 2 (3114) */ 172 .ba5_IDEDMA_CMD = 0x200, 173 .ba5_IDEDMA_CTL = 0x202, 174 .ba5_IDEDMA_TBL = 0x204, 175 .ba5_IDEDMA_CMD2 = 0x210, 176 .ba5_IDEDMA_CTL2 = 0x212, 177 .ba5_IDE_TF0 = 0x280, /* wd_data */ 178 .ba5_IDE_TF1 = 0x281, /* wd_error */ 179 .ba5_IDE_TF2 = 0x282, /* wd_seccnt */ 180 .ba5_IDE_TF3 = 0x283, /* wd_sector */ 181 .ba5_IDE_TF4 = 0x284, /* wd_cyl_lo */ 182 .ba5_IDE_TF5 = 0x285, /* wd_cyl_hi */ 183 .ba5_IDE_TF6 = 0x286, /* wd_sdh */ 184 .ba5_IDE_TF7 = 0x287, /* wd_command */ 185 .ba5_IDE_TF8 = 0x28a, /* wd_altsts */ 186 .ba5_IDE_RAD = 0x28c, 187 .ba5_IDE_TF9 = 0x291, /* Features 2 */ 188 .ba5_IDE_TF10 = 0x292, /* Sector Count 2 */ 189 .ba5_IDE_TF11 = 0x293, /* Start Sector 2 */ 190 .ba5_IDE_TF12 = 0x294, /* Cylinder Low 2 */ 191 .ba5_IDE_TF13 = 0x295, /* Cylinder High 2 */ 192 .ba5_IDE_TF14 = 0x296, /* Device/Head 2 */ 193 .ba5_IDE_TF15 = 0x297, /* Cmd Sts 2 */ 194 .ba5_IDE_TF16 = 0x298, /* Sector Count 2 ext */ 195 .ba5_IDE_TF17 = 0x299, /* Start Sector 2 ext */ 196 .ba5_IDE_TF18 = 0x29a, /* Cyl Low 2 ext */ 197 .ba5_IDE_TF19 = 0x29b, /* Cyl High 2 ext */ 198 .ba5_IDE_RABC = 0x29c, 199 .ba5_IDE_CMD_STS = 0x2a0, 200 .ba5_IDE_CFG_STS = 0x2a1, 201 .ba5_IDE_DTM = 0x2b4, 202 .ba5_SControl = 0x300, 203 .ba5_SStatus = 0x304, 204 .ba5_SError = 0x308, 205 .ba5_SActive = 0x30c, 206 .ba5_SMisc = 0x340, 207 .ba5_PHY_CONFIG = 0x344, 208 .ba5_SIEN = 0x348, 209 .ba5_SFISCfg = 0x34c, 210 }, 211 { /* Channel 3 (3114) */ 212 .ba5_IDEDMA_CMD = 0x208, 213 .ba5_IDEDMA_CTL = 0x20a, 214 .ba5_IDEDMA_TBL = 0x20c, 215 .ba5_IDEDMA_CMD2 = 0x218, 216 .ba5_IDEDMA_CTL2 = 0x21a, 217 .ba5_IDE_TF0 = 0x2c0, /* wd_data */ 218 .ba5_IDE_TF1 = 0x2c1, /* wd_error */ 219 .ba5_IDE_TF2 = 0x2c2, /* wd_seccnt */ 220 .ba5_IDE_TF3 = 0x2c3, /* wd_sector */ 221 .ba5_IDE_TF4 = 0x2c4, /* wd_cyl_lo */ 222 .ba5_IDE_TF5 = 0x2c5, /* wd_cyl_hi */ 223 .ba5_IDE_TF6 = 0x2c6, /* wd_sdh */ 224 .ba5_IDE_TF7 = 0x2c7, /* wd_command */ 225 .ba5_IDE_TF8 = 0x2ca, /* wd_altsts */ 226 .ba5_IDE_RAD = 0x2cc, 227 .ba5_IDE_TF9 = 0x2d1, /* Features 2 */ 228 .ba5_IDE_TF10 = 0x2d2, /* Sector Count 2 */ 229 .ba5_IDE_TF11 = 0x2d3, /* Start Sector 2 */ 230 .ba5_IDE_TF12 = 0x2d4, /* Cylinder Low 2 */ 231 .ba5_IDE_TF13 = 0x2d5, /* Cylinder High 2 */ 232 .ba5_IDE_TF14 = 0x2d6, /* Device/Head 2 */ 233 .ba5_IDE_TF15 = 0x2d7, /* Cmd Sts 2 */ 234 .ba5_IDE_TF16 = 0x2d8, /* Sector Count 2 ext */ 235 .ba5_IDE_TF17 = 0x2d9, /* Start Sector 2 ext */ 236 .ba5_IDE_TF18 = 0x2da, /* Cyl Low 2 ext */ 237 .ba5_IDE_TF19 = 0x2db, /* Cyl High 2 ext */ 238 .ba5_IDE_RABC = 0x2dc, 239 .ba5_IDE_CMD_STS = 0x2e0, 240 .ba5_IDE_CFG_STS = 0x2e1, 241 .ba5_IDE_DTM = 0x2f4, 242 .ba5_SControl = 0x380, 243 .ba5_SStatus = 0x384, 244 .ba5_SError = 0x388, 245 .ba5_SActive = 0x38c, 246 .ba5_SMisc = 0x3c0, 247 .ba5_PHY_CONFIG = 0x3c4, 248 .ba5_SIEN = 0x3c8, 249 .ba5_SFISCfg = 0x3cc, 250 }, 251 }; 252 253 #define ba5_SIS 0x214 /* summary interrupt status */ 254 255 /* Interrupt steering bit in BA5[0x200]. */ 256 #define IDEDMA_CMD_INT_STEER (1U << 1) 257 258 static int satalink_match(device_t, cfdata_t, void *); 259 static void satalink_attach(device_t, device_t, void *); 260 261 CFATTACH_DECL_NEW(satalink, sizeof(struct pciide_softc), 262 satalink_match, satalink_attach, pciide_detach, NULL); 263 264 static void sii3112_chip_map(struct pciide_softc*, 265 const struct pci_attach_args*); 266 static void sii3114_chip_map(struct pciide_softc*, 267 const struct pci_attach_args*); 268 static void sii3112_drv_probe(struct ata_channel*); 269 static void sii3112_setup_channel(struct ata_channel*); 270 271 static const struct pciide_product_desc pciide_satalink_products[] = { 272 { PCI_PRODUCT_CMDTECH_3112, 273 0, 274 "Silicon Image SATALink 3112", 275 sii3112_chip_map, 276 }, 277 { PCI_PRODUCT_CMDTECH_3512, 278 0, 279 "Silicon Image SATALink 3512", 280 sii3112_chip_map, 281 }, 282 { PCI_PRODUCT_CMDTECH_AAR_1210SA, 283 0, 284 "Adaptec AAR-1210SA serial ATA RAID controller", 285 sii3112_chip_map, 286 }, 287 { PCI_PRODUCT_CMDTECH_3114, 288 0, 289 "Silicon Image SATALink 3114", 290 sii3114_chip_map, 291 }, 292 { PCI_PRODUCT_ATI_IXP_SATA_300, 293 0, 294 "ATI IXP 300 SATA", 295 sii3112_chip_map, 296 }, 297 { 0, 298 0, 299 NULL, 300 NULL 301 } 302 }; 303 304 static int 305 satalink_match(device_t parent, cfdata_t match, void *aux) 306 { 307 struct pci_attach_args *pa = aux; 308 309 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 310 if (pciide_lookup_product(pa->pa_id, pciide_satalink_products)) 311 return (2); 312 } 313 return (0); 314 } 315 316 static void 317 satalink_attach(device_t parent, device_t self, void *aux) 318 { 319 struct pci_attach_args *pa = aux; 320 struct pciide_softc *sc = device_private(self); 321 322 sc->sc_wdcdev.sc_atac.atac_dev = self; 323 324 pciide_common_attach(sc, pa, 325 pciide_lookup_product(pa->pa_id, pciide_satalink_products)); 326 327 } 328 329 static inline uint32_t 330 ba5_read_4_ind(struct pciide_softc *sc, bus_addr_t reg) 331 { 332 uint32_t rv; 333 int s; 334 335 s = splbio(); 336 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 337 rv = pci_conf_read(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA); 338 splx(s); 339 340 return (rv); 341 } 342 343 static inline uint32_t 344 ba5_read_4(struct pciide_softc *sc, bus_addr_t reg) 345 { 346 347 if (__predict_true(sc->sc_ba5_en != 0)) 348 return (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg)); 349 350 return (ba5_read_4_ind(sc, reg)); 351 } 352 353 #define BA5_READ_4(sc, chan, reg) \ 354 ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg) 355 356 static inline void 357 ba5_write_4_ind(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 358 { 359 int s; 360 361 s = splbio(); 362 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 363 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA, val); 364 splx(s); 365 } 366 367 static inline void 368 ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 369 { 370 371 if (__predict_true(sc->sc_ba5_en != 0)) 372 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg, val); 373 else 374 ba5_write_4_ind(sc, reg, val); 375 } 376 377 #define BA5_WRITE_4(sc, chan, reg, val) \ 378 ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val)) 379 380 /* 381 * When the Silicon Image 3112 retries a PCI memory read command, 382 * it may retry it as a memory read multiple command under some 383 * circumstances. This can totally confuse some PCI controllers, 384 * so ensure that it will never do this by making sure that the 385 * Read Threshold (FIFO Read Request Control) field of the FIFO 386 * Valid Byte Count and Control registers for both channels (BA5 387 * offset 0x40 and 0x44) are set to be at least as large as the 388 * cacheline size register. 389 * This may also happen on the 3114 (ragge 050527) 390 */ 391 static void 392 sii_fixup_cacheline(struct pciide_softc *sc, const struct pci_attach_args *pa, 393 int n) 394 { 395 pcireg_t cls, reg; 396 int i; 397 static bus_addr_t addr[] = { 0x40, 0x44, 0x240, 0x244 }; 398 399 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 400 cls = (cls >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK; 401 cls *= 4; 402 if (cls > 224) { 403 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 404 cls &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 405 cls |= ((224/4) << PCI_CACHELINE_SHIFT); 406 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, cls); 407 cls = 224; 408 } 409 if (cls < 32) 410 cls = 32; 411 cls = (cls + 31) / 32; 412 for (i = 0; i < n; i++) { 413 reg = ba5_read_4(sc, addr[i]); 414 if ((reg & 0x7) < cls) 415 ba5_write_4(sc, addr[i], (reg & 0x07) | cls); 416 } 417 } 418 419 static void 420 sii3112_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 421 { 422 struct pciide_channel *cp; 423 pcireg_t interface, scs_cmd, cfgctl; 424 int channel; 425 426 if (pciide_chipen(sc, pa) == 0) 427 return; 428 429 #define SII3112_RESET_BITS \ 430 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 431 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 432 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET) 433 434 /* 435 * Reset everything and then unblock all of the interrupts. 436 */ 437 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 438 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 439 scs_cmd | SII3112_RESET_BITS); 440 delay(50 * 1000); 441 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 442 scs_cmd & SCS_CMD_BA5_EN); 443 delay(50 * 1000); 444 445 if (scs_cmd & SCS_CMD_BA5_EN) { 446 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 447 "SATALink BA5 register space enabled\n"); 448 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 449 PCI_MAPREG_TYPE_MEM| 450 PCI_MAPREG_MEM_TYPE_32BIT, 0, 451 &sc->sc_ba5_st, &sc->sc_ba5_sh, 452 NULL, &sc->sc_ba5_ss) != 0) 453 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 454 "unable to map SATALink BA5 register space\n"); 455 else 456 sc->sc_ba5_en = 1; 457 #if 0 458 /* 459 * qemu workaround: BA5 enable is not set, although... 460 * BAR5 is mappable anyway 461 */ 462 } else if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 463 PCI_MAPREG_TYPE_MEM| 464 PCI_MAPREG_MEM_TYPE_32BIT, 0, 465 &sc->sc_ba5_st, &sc->sc_ba5_sh, 466 NULL, &sc->sc_ba5_ss) == 0) { 467 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 468 "SATALink BA5 register space mapped\n"); 469 sc->sc_ba5_en = 1; 470 #endif 471 } else { 472 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 473 "SATALink BA5 register space disabled\n"); 474 475 cfgctl = pci_conf_read(pa->pa_pc, pa->pa_tag, 476 SII3112_PCI_CFGCTL); 477 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_PCI_CFGCTL, 478 cfgctl | CFGCTL_BA5INDEN); 479 } 480 481 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 482 "bus-master DMA support present"); 483 pciide_mapreg_dma(sc, pa); 484 aprint_verbose("\n"); 485 486 /* 487 * Rev. <= 0x01 of the 3112 have a bug that can cause data 488 * corruption if DMA transfers cross an 8K boundary. This is 489 * apparently hard to tickle, but we'll go ahead and play it 490 * safe. 491 */ 492 if ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMDTECH_3112 || 493 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMDTECH_AAR_1210SA) && 494 PCI_REVISION(pa->pa_class) <= 0x01) { 495 sc->sc_dma_maxsegsz = 8192; 496 sc->sc_dma_boundary = 8192; 497 } 498 499 sii_fixup_cacheline(sc, pa, 2); 500 501 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 502 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 503 if (sc->sc_dma_ok) { 504 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 505 sc->sc_wdcdev.irqack = pciide_irqack; 506 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 507 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 508 } 509 sc->sc_wdcdev.sc_atac.atac_set_modes = sii3112_setup_channel; 510 511 /* We can use SControl and SStatus to probe for drives. */ 512 sc->sc_wdcdev.sc_atac.atac_probe = sii3112_drv_probe; 513 514 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 515 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 516 sc->sc_wdcdev.wdc_maxdrives = 1; 517 518 wdc_allocate_regs(&sc->sc_wdcdev); 519 520 /* 521 * The 3112 either identifies itself as a RAID storage device 522 * or a Misc storage device. Fake up the interface bits for 523 * what our driver expects. 524 */ 525 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 526 interface = PCI_INTERFACE(pa->pa_class); 527 } else { 528 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 529 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 530 } 531 532 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 533 channel++) { 534 cp = &sc->pciide_channels[channel]; 535 if (pciide_chansetup(sc, channel, interface) == 0) 536 continue; 537 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 538 } 539 } 540 541 static void 542 sii3114_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 543 { 544 struct pciide_channel *pc; 545 int chan, reg; 546 bus_size_t size; 547 548 sc->sc_wdcdev.dma_arg = sc; 549 sc->sc_wdcdev.dma_init = pciide_dma_init; 550 sc->sc_wdcdev.dma_start = pciide_dma_start; 551 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 552 553 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 554 PCIIDE_OPTIONS_NODMA) { 555 aprint_verbose( 556 ", but unused (forced off by config file)"); 557 sc->sc_dma_ok = 0; 558 return; 559 } 560 561 /* 562 * Slice off a subregion of BA5 for each of the channel's DMA 563 * registers. 564 */ 565 566 sc->sc_dma_iot = sc->sc_ba5_st; 567 for (chan = 0; chan < 4; chan++) { 568 pc = &sc->pciide_channels[chan]; 569 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 570 size = 4; 571 if (size > (IDEDMA_SCH_OFFSET - reg)) 572 size = IDEDMA_SCH_OFFSET - reg; 573 if (bus_space_subregion(sc->sc_ba5_st, 574 sc->sc_ba5_sh, 575 satalink_ba5_regmap[chan].ba5_IDEDMA_CMD + reg, 576 size, &pc->dma_iohs[reg]) != 0) { 577 sc->sc_dma_ok = 0; 578 aprint_verbose(", but can't subregion offset " 579 "%lu size %lu", 580 (u_long) satalink_ba5_regmap[ 581 chan].ba5_IDEDMA_CMD + reg, 582 (u_long) size); 583 return; 584 } 585 } 586 } 587 588 /* DMA registers all set up! */ 589 sc->sc_dmat = pa->pa_dmat; 590 sc->sc_dma_ok = 1; 591 } 592 593 static int 594 sii3114_chansetup(struct pciide_softc *sc, int channel) 595 { 596 static const char *channel_names[] = { 597 "port 0", 598 "port 1", 599 "port 2", 600 "port 3", 601 }; 602 struct pciide_channel *cp = &sc->pciide_channels[channel]; 603 604 sc->wdc_chanarray[channel] = &cp->ata_channel; 605 606 /* 607 * We must always keep the Interrupt Steering bit set in channel 2's 608 * IDEDMA_CMD register. 609 */ 610 if (channel == 2) 611 cp->idedma_cmd = IDEDMA_CMD_INT_STEER; 612 613 cp->name = channel_names[channel]; 614 cp->ata_channel.ch_channel = channel; 615 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 616 617 return (1); 618 } 619 620 static void 621 sii3114_mapchan(struct pciide_channel *cp) 622 { 623 struct ata_channel *wdc_cp = &cp->ata_channel; 624 struct pciide_softc *sc = CHAN_TO_PCIIDE(wdc_cp); 625 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 626 int i; 627 628 cp->compat = 0; 629 cp->ih = sc->sc_pci_ih; 630 631 wdr->cmd_iot = sc->sc_ba5_st; 632 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 633 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF0, 634 9, &wdr->cmd_baseioh) != 0) { 635 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 636 "couldn't subregion %s cmd base\n", cp->name); 637 goto bad; 638 } 639 640 wdr->ctl_iot = sc->sc_ba5_st; 641 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 642 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF8, 643 1, &cp->ctl_baseioh) != 0) { 644 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 645 "couldn't subregion %s ctl base\n", cp->name); 646 goto bad; 647 } 648 wdr->ctl_ioh = cp->ctl_baseioh; 649 650 for (i = 0; i < WDC_NREG; i++) { 651 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 652 i, i == 0 ? 4 : 1, 653 &wdr->cmd_iohs[i]) != 0) { 654 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 655 "couldn't subregion %s channel cmd regs\n", 656 cp->name); 657 goto bad; 658 } 659 } 660 wdc_init_shadow_regs(wdr); 661 wdr->data32iot = wdr->cmd_iot; 662 wdr->data32ioh = wdr->cmd_iohs[0]; 663 wdcattach(wdc_cp); 664 return; 665 666 bad: 667 cp->ata_channel.ch_flags |= ATACH_DISABLED; 668 } 669 670 static void 671 sii3114_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 672 { 673 struct pciide_channel *cp; 674 pcireg_t scs_cmd; 675 pci_intr_handle_t intrhandle; 676 const char *intrstr; 677 int channel; 678 char intrbuf[PCI_INTRSTR_LEN]; 679 680 if (pciide_chipen(sc, pa) == 0) 681 return; 682 683 #define SII3114_RESET_BITS \ 684 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 685 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 686 SCS_CMD_FF3_RESET | SCS_CMD_FF2_RESET | \ 687 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET | \ 688 SCS_CMD_IDE3_RESET | SCS_CMD_IDE2_RESET) 689 690 /* 691 * Reset everything and then unblock all of the interrupts. 692 */ 693 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 694 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 695 scs_cmd | SII3114_RESET_BITS); 696 delay(50 * 1000); 697 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 698 scs_cmd & SCS_CMD_M66EN); 699 delay(50 * 1000); 700 701 /* 702 * On the 3114, the BA5 register space is always enabled. In 703 * order to use the 3114 in any sane way, we must use this BA5 704 * register space, and so we consider it an error if we cannot 705 * map it. 706 * 707 * As a consequence of using BA5, our register mapping is different 708 * from a normal PCI IDE controller's, and so we are unable to use 709 * most of the common PCI IDE register mapping functions. 710 */ 711 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 712 PCI_MAPREG_TYPE_MEM| 713 PCI_MAPREG_MEM_TYPE_32BIT, 0, 714 &sc->sc_ba5_st, &sc->sc_ba5_sh, 715 NULL, &sc->sc_ba5_ss) != 0) { 716 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 717 "unable to map SATALink BA5 register space\n"); 718 return; 719 } 720 sc->sc_ba5_en = 1; 721 722 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 723 "%dMHz PCI bus\n", (scs_cmd & SCS_CMD_M66EN) ? 66 : 33); 724 725 /* 726 * Set the Interrupt Steering bit in the IDEDMA_CMD register of 727 * channel 2. This is required at all times for proper operation 728 * when using the BA5 register space (otherwise interrupts from 729 * all 4 channels won't work). 730 */ 731 BA5_WRITE_4(sc, 2, ba5_IDEDMA_CMD, IDEDMA_CMD_INT_STEER); 732 733 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 734 "bus-master DMA support present"); 735 sii3114_mapreg_dma(sc, pa); 736 aprint_verbose("\n"); 737 738 sii_fixup_cacheline(sc, pa, 4); 739 740 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 741 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 742 if (sc->sc_dma_ok) { 743 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 744 sc->sc_wdcdev.irqack = pciide_irqack; 745 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 746 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 747 } 748 sc->sc_wdcdev.sc_atac.atac_set_modes = sii3112_setup_channel; 749 750 /* We can use SControl and SStatus to probe for drives. */ 751 sc->sc_wdcdev.sc_atac.atac_probe = sii3112_drv_probe; 752 753 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 754 sc->sc_wdcdev.sc_atac.atac_nchannels = 4; 755 sc->sc_wdcdev.wdc_maxdrives = 1; 756 757 wdc_allocate_regs(&sc->sc_wdcdev); 758 759 /* Map and establish the interrupt handler. */ 760 if (pci_intr_map(pa, &intrhandle) != 0) { 761 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 762 "couldn't map native-PCI interrupt\n"); 763 return; 764 } 765 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); 766 sc->sc_pci_ih = pci_intr_establish_xname(pa->pa_pc, intrhandle, IPL_BIO, 767 /* XXX */ 768 pciide_pci_intr, sc, device_xname(sc->sc_wdcdev.sc_atac.atac_dev)); 769 if (sc->sc_pci_ih != NULL) { 770 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 771 "using %s for native-PCI interrupt\n", 772 intrstr ? intrstr : "unknown interrupt"); 773 } else { 774 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 775 "couldn't establish native-PCI interrupt"); 776 if (intrstr != NULL) 777 aprint_error(" at %s", intrstr); 778 aprint_error("\n"); 779 return; 780 } 781 782 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 783 channel++) { 784 cp = &sc->pciide_channels[channel]; 785 if (sii3114_chansetup(sc, channel) == 0) 786 continue; 787 sii3114_mapchan(cp); 788 } 789 } 790 791 /* Probe the drives using SATA registers. 792 * Note we can't use wdc_sataprobe as we may not be able to map ba5 793 */ 794 static void 795 sii3112_drv_probe(struct ata_channel *chp) 796 { 797 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 798 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 799 uint32_t scontrol, sstatus; 800 uint8_t /* scnt, sn, */ cl, ch; 801 int s; 802 803 ata_channel_lock(chp); 804 /* 805 * The 3112 is a 2-port part, and only has one drive per channel 806 * (each port emulates a master drive). 807 * 808 * The 3114 is similar, but has 4 channels. 809 */ 810 811 /* 812 * Request communication initialization sequence, any speed. 813 * Performing this is the equivalent of an ATA Reset. 814 */ 815 scontrol = SControl_DET_INIT | SControl_SPD_ANY; 816 817 /* 818 * XXX We don't yet support SATA power management; disable all 819 * power management state transitions. 820 */ 821 scontrol |= SControl_IPM_NONE; 822 823 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol); 824 delay(50 * 1000); 825 scontrol &= ~SControl_DET_INIT; 826 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol); 827 delay(50 * 1000); 828 829 sstatus = BA5_READ_4(sc, chp->ch_channel, ba5_SStatus); 830 #if 0 831 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 832 "port %d: SStatus=0x%08x, SControl=0x%08x\n", 833 chp->ch_channel, sstatus, 834 BA5_READ_4(sc, chp->ch_channel, ba5_SControl)); 835 #endif 836 switch (sstatus & SStatus_DET_mask) { 837 case SStatus_DET_NODEV: 838 /* No device; be silent. */ 839 break; 840 841 case SStatus_DET_DEV_NE: 842 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 843 "port %d: device connected, but " 844 "communication not established\n", chp->ch_channel); 845 break; 846 847 case SStatus_DET_OFFLINE: 848 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 849 "port %d: PHY offline\n", chp->ch_channel); 850 break; 851 852 case SStatus_DET_DEV: 853 /* 854 * XXX ATAPI detection doesn't currently work. Don't 855 * XXX know why. But, it's not like the standard method 856 * XXX can detect an ATAPI device connected via a SATA/PATA 857 * XXX bridge, so at least this is no worse. --thorpej 858 */ 859 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 860 WDSD_IBM | (0 << 4)); 861 delay(10); /* 400ns delay */ 862 /* Save register contents. */ 863 #if 0 864 scnt = bus_space_read_1(wdr->cmd_iot, 865 wdr->cmd_iohs[wd_seccnt], 0); 866 sn = bus_space_read_1(wdr->cmd_iot, 867 wdr->cmd_iohs[wd_sector], 0); 868 #endif 869 cl = bus_space_read_1(wdr->cmd_iot, 870 wdr->cmd_iohs[wd_cyl_lo], 0); 871 ch = bus_space_read_1(wdr->cmd_iot, 872 wdr->cmd_iohs[wd_cyl_hi], 0); 873 #if 0 874 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 875 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), chp->ch_channel, 876 scnt, sn, cl, ch); 877 #endif 878 if (atabus_alloc_drives(chp, 1) != 0) { 879 ata_channel_unlock(chp); 880 return; 881 } 882 /* 883 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 884 * cases we get wrong values here, so ignore it. 885 */ 886 s = splbio(); 887 if (cl == 0x14 && ch == 0xeb) 888 chp->ch_drive[0].drive_type = ATA_DRIVET_ATAPI; 889 else 890 chp->ch_drive[0].drive_type = ATA_DRIVET_ATA; 891 splx(s); 892 893 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 894 "port %d: device present, speed: %s\n", 895 chp->ch_channel, 896 sata_speed(sstatus)); 897 break; 898 899 default: 900 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 901 "port %d: unknown SStatus: 0x%08x\n", 902 chp->ch_channel, sstatus); 903 } 904 ata_channel_unlock(chp); 905 } 906 907 static void 908 sii3112_setup_channel(struct ata_channel *chp) 909 { 910 struct ata_drive_datas *drvp; 911 int drive, s; 912 u_int32_t idedma_ctl, dtm; 913 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 914 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 915 916 /* setup DMA if needed */ 917 pciide_channel_dma_setup(cp); 918 919 idedma_ctl = 0; 920 dtm = 0; 921 922 for (drive = 0; drive < 2; drive++) { 923 drvp = &chp->ch_drive[drive]; 924 /* If no drive, skip */ 925 if (drvp->drive_type == ATA_DRIVET_NONE) 926 continue; 927 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 928 /* use Ultra/DMA */ 929 s = splbio(); 930 drvp->drive_flags &= ~ATA_DRIVE_DMA; 931 splx(s); 932 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 933 dtm |= DTM_IDEx_DMA; 934 } else if (drvp->drive_flags & ATA_DRIVE_DMA) { 935 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 936 dtm |= DTM_IDEx_DMA; 937 } else { 938 dtm |= DTM_IDEx_PIO; 939 } 940 } 941 942 /* 943 * Nothing to do to setup modes; it is meaningless in S-ATA 944 * (but many S-ATA drives still want to get the SET_FEATURE 945 * command). 946 */ 947 if (idedma_ctl != 0) { 948 /* Add software bits in status register */ 949 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 950 idedma_ctl); 951 } 952 BA5_WRITE_4(sc, chp->ch_channel, ba5_IDE_DTM, dtm); 953 } 954
Indexes created Sun Oct 25 00:26:45 UTC 2026