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    Searched defs:ctl (Results 1 - 25 of 131) sorted by relevancy

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  /src/sys/arch/x68k/usr.bin/tvctrl/
tvctrl.c 19 unsigned char ctl; local
31 ctl = num;
32 if (ioctl(0, ITETVCTRL, &ctl))
  /src/sys/modules/examples/executor/
executor.c 54 static once_t ctl; variable
55 static ONCE_DECL(ctl);
77 RUN_ONCE(&ctl, runonce_example);
  /src/sys/arch/mips/alchemy/
au_timer.c 75 uint32_t ctl, ctr, octr; local
79 ctl = bus_space_read_4(st, sh, PC_COUNTER_CONTROL);
80 if ((ctl & (CC_EO | CC_EN1)) != (CC_EO | CC_EN1))
81 SET_PC_REG(PC_COUNTER_CONTROL, 0, ctl | CC_EO | CC_EN1);
109 if ((ctl & (CC_EO | CC_EN1)) != (CC_EO | CC_EN1))
110 SET_PC_REG(PC_COUNTER_CONTROL, 0, ctl);
  /src/sys/arch/mips/include/
sysarch.h 46 int ctl; member in struct:mips_cachectl_args
netbsd32_machdep.h 81 int ctl; member in struct:mips_cachectl_args32
  /src/sys/arch/mvme68k/stand/sboot/
console.c 38 volatile u_char ctl; member in struct:zs_hw
55 zs->ctl = 1; rr1 = zs->ctl;
56 zs->ctl = 0;
57 if ((rr1 & 0x1) == 1 && (zs->ctl & 0x4) == 4)
60 zs->ctl = 9;
61 zs->ctl = 0x00; /* clear interrupt */
62 zs->ctl = 4;
63 zs->ctl = 0x44; /* 16x clk, 1 stop bit */
64 zs->ctl = 5
    [all...]
  /src/sys/arch/newsmips/apbus/
apbus_subr.c 74 struct apbus_ctl *ctl; local
79 ctl = apbus_dev->apbd_ctl;
80 if (ctl == NULL)
83 return (void *)ctl->apbc_hwbase;
143 printf("ctl: 0x%08x\n", (unsigned int)apdev->apbd_ctl);
  /src/sys/dev/ic/
rng200.c 53 uint32_t ctl, rng, rbg; local
56 ctl = READ4(sc, RNG200_CONTROL);
57 ctl &= ~RNG200_RBG_MASK;
58 WRITE4(sc, RNG200_CONTROL, ctl);
72 WRITE4(sc, RNG200_CONTROL, ctl | RNG200_RBG_ENABLE);
  /src/sys/external/bsd/drm2/dist/drm/
drm_irq.c 263 struct drm_control *ctl = data; local
278 switch (ctl->func) {
281 irq = ctl->irq;
287 ctl->irq != irq)
  /src/sbin/mount_portal/
activate.c 112 void *ctl = NULL; local
138 ctl = malloc(cmsgsize);
139 if (ctl == NULL) {
143 memset(ctl, 0, cmsgsize);
145 cmsg = (struct cmsghdr *) ctl;
153 msg.msg_control = ctl;
176 if (ctl != NULL)
177 free(ctl);
  /src/sys/arch/alpha/pci/
dwlpx.c 80 uint32_t ctl; local
91 if (badaddr(KV(PCIA_CTL(1) + ls), sizeof (ctl)) != 0) {
184 uint32_t ctl; local
199 sizeof (ctl)) != 0) {
225 ctl = REGVAL(PCIA_PRESENT + ccp->cc_sysbase);
234 } else if ((ctl >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK) {
266 ctl = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase);
267 ctl &= 0x0fffffff;
268 ctl &= ~(PCIA_CTL_MHAE(0x1f) | PCIA_CTL_IHAE(0x1f));
273 ctl |= PCIA_CTL_RMMENA | PCIA_CTL_RMMARB
    [all...]
mcpcia.c 132 uint32_t ctl; local
163 ctl = REGVAL(MCPCIA_PCI_REV(ccp));
166 " CAP Revision %d\n", HORSE_REV(ctl),
167 (SADDLE_TYPE(ctl) & 1)? "Right": "Left", SADDLE_REV(ctl),
168 CAP_REV(ctl));
244 uint32_t ctl; local
272 ctl = REGVAL(MCPCIA_WHOAMI(ccp));
273 mcbus_primary.mcbus_cpu_mid = MCBUS_CPU_MID(ctl);
274 if ((MCBUS_CPU_INFO(ctl) & CPU_Fill_Err) == 0 &
300 volatile uint32_t ctl; local
    [all...]
  /src/sys/arch/news68k/dev/
dmac_0266.h 30 volatile uint32_t ctl; /* Control Register */ member in struct:dma_regs
  /src/sys/arch/arc/include/
pccons.h 20 #define KB_CTL 0x0010 /* control shift -- allows ctl function */
34 char ctl[KB_CODE_SIZE]; member in struct:__anon989
  /src/sys/arch/evbppc/walnut/dev/
ds1743.c 211 u_char octl, ctl; local
214 ctl = octl | (mode & DS_CTL_RW);
215 ds1743_write(sc, DS_CENTURY, ctl); /* Lock RTC for both reading and writing */
222 int ctl; local
224 ctl = ds1743_read(sc, DS_CENTURY);
225 ctl = (ctl & 0x3f) | (key & DS_CTL_RW);
226 ds1743_write(sc, DS_CENTURY, ctl); /* Enable updates */
  /src/sys/arch/luna68k/dev/
if_le.c 212 * accessible 4bit-wise by ctl register operation. The register is
220 volatile struct { uint32_t ctl; } *ds1220; member in struct:__anon1554
243 ds1220->ctl = (loc) << 16;
244 u = 0xf0 & (ds1220->ctl >> 12);
245 ds1220->ctl = (loc + 1) << 16;
246 l = 0x0f & (ds1220->ctl >> 16);
249 ds1220->ctl = (loc + 2) << 16;
250 u = 0xf0 & (ds1220->ctl >> 12);
251 ds1220->ctl = (loc + 3) << 16;
252 l = 0x0f & (ds1220->ctl >> 16)
    [all...]
  /src/sys/compat/common/
uipc_syscalls_43.c 307 struct mbuf *ctl; local
321 ctl = m_get(M_WAIT, MT_CONTROL);
322 ctl->m_len = clen;
323 cmsg = mtod(ctl, struct cmsghdr *);
330 m_free(ctl);
334 msg->msg_control = ctl;
  /src/sys/dev/pci/
nside.c 95 pcireg_t interface, ctl; local
133 ctl = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1);
135 ctl &= ~NATSEMI_CTRL1_INTAMASK;
137 ctl |= NATSEMI_CTRL1_INTAMASK;
138 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1, ctl);
universe_pci.c 172 u_int32_t ctl = 0x80000000; local
176 ctl |= 0x00020000;
179 ctl |= 0x00010000;
187 ctl |= 0x00001000;
189 ctl |= 0x00004000;
191 ctl |= 0x00800000;
193 ctl |= 0x00400000;
198 printf("%s: wnd %d, map VME %x-%x to %x, ctl=%x\n",
199 d->devname, wnd, vmebase, vmebase + len, pcibase, ctl);
205 write_pcislv(d, wnd, lsi_ctl, ctl);
222 u_int32_t ctl = 0x80000000; local
    [all...]
  /src/usr.sbin/bthcid/
client.c 90 int ctl; local
101 ctl = socket(PF_LOCAL, SOCK_STREAM, 0);
102 if (ctl < 0)
109 if (bind(ctl, (struct sockaddr *)&un, sizeof(un)) < 0) {
110 close(ctl);
115 close(ctl);
120 if (listen(ctl, 10) < 0) {
121 close(ctl);
126 event_set(&control_ev, ctl, EV_READ | EV_PERSIST, process_control, NULL);
128 close(ctl);
    [all...]
  /src/external/bsd/libpcap/dist/
pcap-enet.c 153 struct eniocb ctl; local
173 if (ioctl(if_fd, EIOCGETP, (char *)&ctl) == -1) {
181 ctl.en_rtout = 1 * ctl.en_hz;
182 ctl.en_tr_etherhead = 1;
183 ctl.en_tap_network = 1;
184 ctl.en_multi_packet = 1;
185 ctl.en_maxlen = BUFSPACE;
187 ctl.en_rtout = 64; /* randomly picked value for HZ */
189 if (ioctl(if_fd, EIOCSETP, &ctl) == -1)
    [all...]
  /src/external/gpl3/gdb/dist/sim/bfin/
dv-bfin_pfmon.c 35 bu32 ctl; member in struct:bfin_pfmon
39 #define mmr_base() offsetof(struct bfin_pfmon, ctl)
69 case mmr_offset(ctl):
102 case mmr_offset(ctl):
  /src/external/gpl3/gdb.old/dist/sim/bfin/
dv-bfin_pfmon.c 35 bu32 ctl; member in struct:bfin_pfmon
39 #define mmr_base() offsetof(struct bfin_pfmon, ctl)
69 case mmr_offset(ctl):
102 case mmr_offset(ctl):
  /src/sys/arch/arm/cortex/
a9tmr.c 194 uint32_t ctl = a9tmr_global_read(sc, TMR_GBL_CTL); local
195 if (ctl & TMR_GBL_CTL_CMP_ENABLE) {
197 ctl & ~TMR_GBL_CTL_CMP_ENABLE);
211 ctl |= TMR_GBL_CTL_CMP_ENABLE | TMR_GBL_CTL_INT_ENABLE |
213 a9tmr_global_write(sc, TMR_GBL_CTL, ctl);
215 printf("%s: %s: ctl %#x autoinc %u cmp %#x%08x now %#"PRIx64"\n",
gtmr.c 254 uint64_t ctl; local
286 ctl = gtmr_read_ctl(sc);
287 ctl &= ~CNTCTL_IMASK;
288 ctl |= CNTCTL_ENABLE;
289 gtmr_write_ctl(sc, ctl);
353 const uint32_t ctl = gtmr_read_ctl(sc); local
354 if ((ctl & (CNTCTL_ENABLE|CNTCTL_ISTATUS)) != (CNTCTL_ENABLE|CNTCTL_ISTATUS)) {
355 aprint_debug_dev(ci->ci_dev, "spurious timer interrupt (ctl=%#x)\n", ctl);

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