| /src/sys/arch/sgimips/hpc/ |
| if_sq.c | 935 uint32_t ctl_reg; local in function:sq_rxintr
947 ctl_reg =
950 ctl_reg =
953 if (ctl_reg) {
|
| /src/sys/arch/mips/cavium/dev/ |
| octeon_gmx.c | 1011 uint64_t ctl_reg, status, timer_count; local in function:octgmx_sgmii_enable
1031 ctl_reg = PCS_READ_8(sc, PCS_MR_CONTROL);
1032 SET(ctl_reg, PCS_MR_CONTROL_RESET);
1033 PCS_WRITE_8(sc, PCS_MR_CONTROL, ctl_reg);
1038 ctl_reg = PCS_READ_8(sc, PCS_MR_CONTROL);
1039 if (!ISSET(ctl_reg, PCS_MR_CONTROL_RESET)) {
1050 SET(ctl_reg, PCS_MR_CONTROL_AN_EN);
1051 SET(ctl_reg, PCS_MR_CONTROL_RST_AN);
1052 CLR(ctl_reg, PCS_MR_CONTROL_PWR_DN);
1053 PCS_WRITE_8(sc, PCS_MR_CONTROL, ctl_reg);
[all...] |
| /src/sys/arch/arm/sunxi/ |
| sun4i_emac.c | 620 bus_size_t const ctl_reg = EMAC_TX_CTL_REG(slot); local in function:sun4i_emac_tx_enqueue
623 sun4i_emac_clear_set(sc, ctl_reg, 0, EMAC_TX_CTL_START);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_hdmi.c | 524 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); local in function:hsw_write_infoframe
527 u32 val = I915_READ(ctl_reg);
534 I915_WRITE(ctl_reg, val);
547 I915_WRITE(ctl_reg, val);
548 POSTING_READ(ctl_reg);
|
