1 /* $NetBSD: pci.h,v 1.58 2024/05/19 17:36:08 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2013 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Taylor R. Campbell. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _LINUX_PCI_H_ 33 #define _LINUX_PCI_H_ 34 35 #ifdef _KERNEL_OPT 36 #include "acpica.h" 37 #endif 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/bus.h> 42 #include <sys/cdefs.h> 43 #include <sys/kmem.h> 44 #include <sys/systm.h> 45 46 #include <machine/limits.h> 47 48 #include <dev/pci/pcidevs.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/agpvar.h> 52 #include <dev/pci/ppbvar.h> 53 54 #include <linux/device.h> 55 #include <linux/dma-mapping.h> 56 #include <linux/errno.h> 57 #include <linux/io.h> 58 #include <linux/interrupt.h> 59 #include <linux/ioport.h> 60 #include <linux/kernel.h> 61 62 struct acpi_devnode; 63 struct pci_driver; 64 struct pci_dev; 65 struct pci_bus; 66 67 struct pci_device_id { 68 uint32_t vendor; 69 uint32_t device; 70 uint32_t subvendor; 71 uint32_t subdevice; 72 uint32_t class; 73 uint32_t class_mask; 74 unsigned long driver_data; 75 }; 76 77 #define PCI_DEVICE(VENDOR, DEVICE) \ 78 .vendor = (VENDOR), \ 79 .device = (DEVICE) 80 81 #define PCI_ANY_ID (~0) 82 83 #define PCI_BASE_CLASS_DISPLAY PCI_CLASS_DISPLAY 84 85 #define PCI_CLASS_DISPLAY_VGA \ 86 ((PCI_CLASS_DISPLAY << 8) | PCI_SUBCLASS_DISPLAY_VGA) 87 CTASSERT(PCI_CLASS_DISPLAY_VGA == 0x0300); 88 89 #define PCI_CLASS_DISPLAY_OTHER \ 90 ((PCI_CLASS_DISPLAY << 8) | PCI_SUBCLASS_DISPLAY_MISC) 91 CTASSERT(PCI_CLASS_DISPLAY_OTHER == 0x0380); 92 93 #define PCI_CLASS_DISPLAY_3D \ 94 ((PCI_CLASS_DISPLAY << 8) | PCI_SUBCLASS_DISPLAY_3D) 95 CTASSERT(PCI_CLASS_DISPLAY_3D == 0x0302); 96 97 #define PCI_CLASS_BRIDGE_ISA \ 98 ((PCI_CLASS_BRIDGE << 8) | PCI_SUBCLASS_BRIDGE_ISA) 99 CTASSERT(PCI_CLASS_BRIDGE_ISA == 0x0601); 100 101 /* XXX This is getting silly... */ 102 #define PCI_VENDOR_ID_APPLE PCI_VENDOR_APPLE 103 #define PCI_VENDOR_ID_ASUSTEK PCI_VENDOR_ASUSTEK 104 #define PCI_VENDOR_ID_ATI PCI_VENDOR_ATI 105 #define PCI_VENDOR_ID_DELL PCI_VENDOR_DELL 106 #define PCI_VENDOR_ID_IBM PCI_VENDOR_IBM 107 #define PCI_VENDOR_ID_HP PCI_VENDOR_HP 108 #define PCI_VENDOR_ID_INTEL PCI_VENDOR_INTEL 109 #define PCI_VENDOR_ID_NVIDIA PCI_VENDOR_NVIDIA 110 #define PCI_VENDOR_ID_SI PCI_VENDOR_SIS 111 #define PCI_VENDOR_ID_SONY PCI_VENDOR_SONY 112 #define PCI_VENDOR_ID_VIA PCI_VENDOR_VIATECH 113 114 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 115 116 #define PCI_DEVICE_ID_ATI_RADEON_QY PCI_PRODUCT_ATI_RADEON_RV100_QY 117 118 #define PCI_SUBDEVICE_ID_QEMU 0x1100 119 120 #define PCI_DEVFN(DEV, FN) \ 121 (__SHIFTIN((DEV), __BITS(3, 7)) | __SHIFTIN((FN), __BITS(0, 2))) 122 #define PCI_SLOT(DEVFN) ((int)__SHIFTOUT((DEVFN), __BITS(3, 7))) 123 #define PCI_FUNC(DEVFN) ((int)__SHIFTOUT((DEVFN), __BITS(0, 2))) 124 125 #define PCI_DEVID(BUS, DEVFN) \ 126 (__SHIFTIN((BUS), __BITS(15, 8)) | __SHIFTIN((DEVFN), __BITS(7, 0))) 127 #define PCI_BUS_NUM(DEVID) ((int)__SHIFTOUT((DEVID), __BITS(15,8))) 128 129 #define PCI_NUM_RESOURCES ((PCI_MAPREG_END - PCI_MAPREG_START) / 4) 130 #define DEVICE_COUNT_RESOURCE PCI_NUM_RESOURCES 131 132 #define PCI_CAP_ID_AGP PCI_CAP_AGP 133 134 #define PCI_EXP_LNKCTL PCIE_LCSR 135 #define PCI_EXP_LNKCTL_HAWD PCIE_LCSR_HAWD 136 #define PCI_EXP_DEVSTA (PCIE_DCSR + 2) 137 #define PCI_EXP_DEVSTA_TRPND (PCIE_DCSR_TRANSACTION_PND >> 16) 138 #define PCI_EXP_LNKCTL2 PCIE_LCAP2 139 #define PCI_EXP_LNKCTL2_ENTER_COMP PCIE_LCSR2_ENT_COMPL 140 #define PCI_EXP_LNKCTL2_TX_MARGIN PCIE_LCSR2_TX_MARGIN 141 #define PCI_EXP_LNKCTL2_TLS PCIE_LCSR2_TGT_LSPEED 142 #define PCI_EXP_LNKCTL2_TLS_2_5GT PCIE_LCSR2_TGT_LSPEED_2_5G 143 #define PCI_EXP_LNKCTL2_TLS_5_0GT PCIE_LCSR2_TGT_LSPEED_5G 144 #define PCI_EXP_LNKCTL2_TLS_8_0GT PCIE_LCSR2_TGT_LSPEED_8G 145 #define PCI_EXP_LNKCAP PCIE_LCAP 146 #define PCI_EXP_LNKCAP_CLKPM PCIE_LCAP_CLOCK_PM 147 #define PCI_EXP_DEVCAP2_ATOMIC_COMP32 PCIE_DCAP2_32ATOM 148 #define PCI_EXP_DEVCAP2_ATOMIC_COMP64 PCIE_DCAP2_64ATOM 149 150 151 typedef int pci_power_t; 152 153 #define PCI_D0 0 154 #define PCI_D1 1 155 #define PCI_D2 2 156 #define PCI_D3hot 3 157 #define PCI_D3cold 4 158 159 #define __pci_iomem 160 161 struct pci_dev { 162 struct pci_attach_args pd_pa; 163 int pd_kludges; /* Gotta lose 'em... */ 164 #define NBPCI_KLUDGE_GET_MUMBLE 0x01 165 #define NBPCI_KLUDGE_MAP_ROM 0x02 166 bus_space_tag_t pd_rom_bst; 167 bus_space_handle_t pd_rom_bsh; 168 bus_size_t pd_rom_size; 169 bus_space_handle_t pd_rom_found_bsh; 170 bus_size_t pd_rom_found_size; 171 void *pd_rom_vaddr; 172 device_t pd_dev; 173 void *pd_drvdata; 174 struct { 175 pcireg_t type; 176 bus_addr_t addr; 177 bus_size_t size; 178 int flags; 179 bus_space_tag_t bst; 180 bus_space_handle_t bsh; 181 void __pci_iomem *kva; 182 bool mapped; 183 } pd_resources[PCI_NUM_RESOURCES]; 184 struct pci_conf_state *pd_saved_state; 185 struct acpi_devnode *pd_ad; 186 pci_intr_handle_t *pd_intr_handles; 187 unsigned pd_enablecnt; 188 189 /* Linx API only below */ 190 struct pci_bus *bus; 191 uint32_t devfn; 192 uint16_t vendor; 193 uint16_t device; 194 uint16_t subsystem_vendor; 195 uint16_t subsystem_device; 196 uint8_t revision; 197 uint32_t class; 198 bool msi_enabled; 199 bool no_64bit_msi; 200 }; 201 202 enum pci_bus_speed { 203 PCI_SPEED_UNKNOWN, 204 PCIE_SPEED_2_5GT, 205 PCIE_SPEED_5_0GT, 206 PCIE_SPEED_8_0GT, 207 PCIE_SPEED_16_0GT, 208 PCIE_SPEED_32_0GT, 209 PCIE_SPEED_64_0GT, 210 }; 211 212 /* 213 * Actually values from the Link Status register, bits 16-19. Don't use 214 * these as a bit-mask -- these are the only known, valid values. 215 */ 216 enum pcie_link_width { 217 PCIE_LNK_WIDTH_RESRV = 0, 218 PCIE_LNK_X1 = __BIT(0), 219 PCIE_LNK_X2 = __BIT(1), 220 PCIE_LNK_X4 = __BIT(2), 221 PCIE_LNK_X8 = __BIT(3), 222 PCIE_LNK_X12 = __BITS(2,3), 223 PCIE_LNK_X16 = __BIT(4), 224 PCIE_LNK_X32 = __BIT(5), 225 PCIE_LNK_WIDTH_UNKNOWN = __BITS(0, 7), 226 }; 227 228 #define PCIBIOS_MIN_MEM 0x100000 /* XXX bogus x86 kludge bollocks */ 229 230 #define __pci_rom_iomem 231 232 struct pci_bus { 233 /* NetBSD private members */ 234 pci_chipset_tag_t pb_pc; 235 device_t pb_dev; 236 237 /* Linux API */ 238 u_int number; 239 enum pci_bus_speed max_bus_speed; 240 241 struct pci_dev *self; 242 }; 243 244 /* Namespace. */ 245 #define pci_bus_alloc_resource linux_pci_bus_alloc_resource 246 #define pci_bus_read_config_byte linux_pci_bus_read_config_byte 247 #define pci_bus_read_config_dword linux_pci_bus_read_config_dword 248 #define pci_bus_read_config_word linux_pci_bus_read_config_word 249 #define pci_bus_write_config_byte linux_pci_bus_write_config_byte 250 #define pci_bus_write_config_dword linux_pci_bus_write_config_dword 251 #define pci_bus_write_config_word linux_pci_bus_write_config_word 252 #define pci_clear_master linux_pci_clear_master 253 #define pci_dev_dev linux_pci_dev_dev 254 #define pci_dev_present linux_pci_dev_present 255 #define pci_dev_put linux_pci_dev_put 256 #define pci_disable_msi linux_pci_disable_msi 257 #define pci_disable_rom linux_pci_disable_rom 258 #define pci_dma_supported linux_pci_dma_supported 259 #define pci_domain_nr linux_pci_domain_nr 260 #define pci_enable_msi linux_pci_enable_msi 261 #define pci_enable_rom linux_pci_enable_rom 262 #define pci_find_capability linux_pci_find_capability 263 #define pci_get_class linux_pci_get_class 264 #define pci_get_domain_bus_and_slot linux_pci_get_domain_bus_and_slot 265 #define pci_get_drvdata linux_pci_get_drvdata 266 #define pci_iomap linux_pci_iomap 267 #define pci_iounmap linux_pci_iounmap 268 #define pci_is_pcie linux_pci_is_pcie 269 #define pci_is_root_bus linux_pci_is_root_bus 270 #define pci_is_thunderbolt_attached linux_pci_is_thunderbolt_attached 271 #define pci_map_rom linux_pci_map_rom 272 #define pci_name linux_pci_name 273 #define pci_platform_rom linux_pci_platform_rom 274 #define pci_read_config_byte linux_pci_read_config_byte 275 #define pci_read_config_dword linux_pci_read_config_dword 276 #define pci_read_config_word linux_pci_read_config_word 277 #define pci_release_region linux_pci_release_region 278 #define pci_release_regions linux_pci_release_regions 279 #define pci_request_region linux_pci_request_region 280 #define pci_request_regions linux_pci_request_regions 281 #define pci_resource_end linux_pci_resource_end 282 #define pci_resource_flags linux_pci_resource_flags 283 #define pci_resource_len linux_pci_resource_len 284 #define pci_resource_start linux_pci_resource_start 285 #define pci_restore_state linux_pci_restore_state 286 #define pci_save_state linux_pci_save_state 287 #define pci_set_drvdata linux_pci_set_drvdata 288 #define pci_set_master linux_pci_set_master 289 #define pci_unmap_rom linux_pci_unmap_rom 290 #define pci_write_config_byte linux_pci_write_config_byte 291 #define pci_write_config_dword linux_pci_write_config_dword 292 #define pci_write_config_word linux_pci_write_config_word 293 #define pcibios_align_resource linux_pcibios_align_resource 294 #define pcie_get_speed_cap linux_pcie_get_speed_cap 295 #define pcie_bandwidth_available linux_pcie_bandwidth_available 296 #define pcie_read_config_dword linux_pcie_capability_read_dword 297 #define pcie_read_config_word linux_pcie_capability_read_word 298 #define pcie_write_config_dword linux_pcie_capability_write_dword 299 #define pcie_write_config_word linux_pcie_capability_write_word 300 #define pci_enable_atomic_ops_to_root linux_pci_enable_atomic_ops_to_root 301 302 /* NetBSD local additions. */ 303 void linux_pci_dev_init(struct pci_dev *, device_t, device_t, 304 const struct pci_attach_args *, int); 305 void linux_pci_dev_destroy(struct pci_dev *); 306 307 /* NetBSD no-renames because use requires review. */ 308 int linux_pci_enable_device(struct pci_dev *); 309 void linux_pci_disable_device(struct pci_dev *); 310 311 bool pci_is_root_bus(struct pci_bus *); 312 int pci_domain_nr(struct pci_bus *); 313 314 device_t pci_dev_dev(struct pci_dev *); 315 void pci_set_drvdata(struct pci_dev *, void *); 316 void * pci_get_drvdata(struct pci_dev *); 317 const char * pci_name(struct pci_dev *); 318 319 int pci_find_capability(struct pci_dev *, int); 320 bool pci_is_pcie(struct pci_dev *); 321 bool pci_dma_supported(struct pci_dev *, uintmax_t); 322 bool pci_is_thunderbolt_attached(struct pci_dev *); 323 324 int pci_read_config_dword(struct pci_dev *, int, uint32_t *); 325 int pci_read_config_word(struct pci_dev *, int, uint16_t *); 326 int pci_read_config_byte(struct pci_dev *, int, uint8_t *); 327 int pci_write_config_dword(struct pci_dev *, int, uint32_t); 328 int pci_write_config_word(struct pci_dev *, int, uint16_t); 329 int pci_write_config_byte(struct pci_dev *, int, uint8_t); 330 331 int pcie_capability_read_dword(struct pci_dev *, int, uint32_t *); 332 int pcie_capability_read_word(struct pci_dev *, int, uint16_t *); 333 int pcie_capability_write_dword(struct pci_dev *, int, uint32_t); 334 int pcie_capability_write_word(struct pci_dev *, int, uint16_t); 335 336 int pci_bus_read_config_dword(struct pci_bus *, unsigned, int, 337 uint32_t *); 338 int pci_bus_read_config_word(struct pci_bus *, unsigned, int, 339 uint16_t *); 340 int pci_bus_read_config_byte(struct pci_bus *, unsigned, int, 341 uint8_t *); 342 int pci_bus_write_config_dword(struct pci_bus *, unsigned, int, 343 uint32_t); 344 int pci_bus_write_config_word(struct pci_bus *, unsigned, int, 345 uint16_t); 346 int pci_bus_write_config_byte(struct pci_bus *, unsigned, int, 347 uint8_t); 348 349 int pci_enable_msi(struct pci_dev *); 350 void pci_disable_msi(struct pci_dev *); 351 void pci_set_master(struct pci_dev *); 352 void pci_clear_master(struct pci_dev *); 353 354 int pcie_get_readrq(struct pci_dev *); 355 int pcie_set_readrq(struct pci_dev *, int); 356 357 bus_addr_t pcibios_align_resource(void *, const struct resource *, 358 bus_addr_t, bus_size_t); 359 int pci_bus_alloc_resource(struct pci_bus *, struct resource *, 360 bus_size_t, bus_size_t, bus_addr_t, int, 361 bus_addr_t (*)(void *, const struct resource *, bus_addr_t, 362 bus_size_t), struct pci_dev *); 363 364 /* XXX Kludges only -- do not use without checking the implementation! */ 365 struct pci_dev *pci_get_domain_bus_and_slot(int, int, int); 366 struct pci_dev *pci_get_class(uint32_t, struct pci_dev *); /* i915 kludge */ 367 int pci_dev_present(const struct pci_device_id *); 368 void pci_dev_put(struct pci_dev *); 369 370 void __pci_rom_iomem * 371 pci_map_rom(struct pci_dev *, size_t *); 372 void __pci_rom_iomem * 373 pci_platform_rom(struct pci_dev *, size_t *); 374 void pci_unmap_rom(struct pci_dev *, void __pci_rom_iomem *); 375 int pci_enable_rom(struct pci_dev *); 376 void pci_disable_rom(struct pci_dev *); 377 378 int pci_request_regions(struct pci_dev *, const char *); 379 void pci_release_regions(struct pci_dev *); 380 int pci_request_region(struct pci_dev *, int, const char *); 381 void pci_release_region(struct pci_dev *, int); 382 383 bus_addr_t pci_resource_start(struct pci_dev *, unsigned); 384 bus_size_t pci_resource_len(struct pci_dev *, unsigned); 385 bus_addr_t pci_resource_end(struct pci_dev *, unsigned); 386 int pci_resource_flags(struct pci_dev *, unsigned); 387 388 void __pci_iomem * 389 pci_iomap(struct pci_dev *, unsigned, bus_size_t); 390 void pci_iounmap(struct pci_dev *, void __pci_iomem *); 391 392 void pci_save_state(struct pci_dev *); 393 void pci_restore_state(struct pci_dev *); 394 395 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 396 unsigned pcie_bandwidth_available(struct pci_dev *dev, 397 struct pci_dev **limiting_dev, 398 enum pci_bus_speed *speed, 399 enum pcie_link_width *width); 400 401 static inline bool 402 dev_is_pci(struct device *dev) 403 { 404 struct device *parent = device_parent(dev); 405 406 return parent && device_is_a(parent, "pci"); 407 } 408 409 static inline int 410 pci_enable_atomic_ops_to_root(struct pci_dev *dev, uint32_t cap_mask) 411 { 412 413 return -EINVAL; 414 } 415 416 #endif /* _LINUX_PCI_H_ */ 417
Indexes created Sun Sep 21 20:09:37 GMT 2025