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  /src/lib/libc/arch/i386/stdlib/
div.S 1 /* $NetBSD: div.S,v 1.10 2014/05/23 02:34:19 uebayasi Exp $ */
10 RCSID("$NetBSD: div.S,v 1.10 2014/05/23 02:34:19 uebayasi Exp $")
13 ENTRY(div) function
25 END(div)
  /src/lib/libc/arch/x86_64/stdlib/
div.S 1 /* $NetBSD: div.S,v 1.2 2014/05/22 15:01:56 uebayasi Exp $ */
10 RCSID("$NetBSD: div.S,v 1.2 2014/05/22 15:01:56 uebayasi Exp $")
13 ENTRY(div) function
20 END(div)
  /src/lib/libc/stdlib/
Lint_div.c 12 div(int num, int denom) function
div.c 1 /* $NetBSD: div.c,v 1.8 2012/06/25 22:32:45 abs Exp $ */
38 static char sccsid[] = "@(#)div.c 8.1 (Berkeley) 6/4/93";
40 __RCSID("$NetBSD: div.c,v 1.8 2012/06/25 22:32:45 abs Exp $");
47 div(int num, int denom) function
  /src/sys/compat/linux/common/
linux_statfs.h 98 int i, div; local
113 div = bsp->f_frsize ? (bsp->f_bsize / bsp->f_frsize) : 1;
114 if (div == 0)
115 div = 1;
118 lsp->l_fblocks = bsp->f_blocks / div;
119 lsp->l_fbfree = bsp->f_bfree / div;
120 lsp->l_fbavail = bsp->f_bavail / div;
122 lsp->l_fffree = bsp->f_ffree / div;
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_afmt.c 59 unsigned long div, mul; local
66 div = gcd(n, cts);
68 n /= div;
69 cts /= div;
  /src/sys/arch/arm/amlogic/
meson_clk_div.c 43 struct meson_clk_div *div = &clk->u.div; local
60 val = CLK_READ(sc, div->reg);
63 if (div->div)
64 ratio = __SHIFTOUT(val, div->div);
68 if (div->flags & MESON_CLK_DIV_POWER_OF_TWO) {
70 } else if (div->flags & MESON_CLK_DIV_CPU_SCALE_TABLE) {
83 struct meson_clk_div *div = &clk->u.div local
143 struct meson_clk_div *div = &clk->u.div; local
    [all...]
meson_clk_mpll.c 71 const uint64_t div = (SDM_DEN * n2) + sdm; local
72 if (div == 0)
75 return (u_int)howmany(parent_rate * SDM_DEN, div);
  /src/sys/arch/arm/imx/
imxi2c.c 42 int div; member in struct:clk_div
88 if (freq / imxi2c_clk_div[index].div < speed) {
imxpwm.c 94 const int div = __SHIFTOUT(cr, PWM_CR_PRESCALER) + 1; local
96 const uint64_t rate = sc->sc_freq / div;
117 int div = 0; local
119 div++;
120 rate = sc->sc_freq / div;
127 cr |= __SHIFTIN(div - 1, PWM_CR_PRESCALER);
imxspi.c 131 uint32_t div; local
134 div = (sc->sc_freq + (speed - 1)) / speed;
135 div = div - 1;
136 for (div_cnt = 0; div > 0; div_cnt++)
137 div >>= 1;
181 uint32_t div; local
185 div = (sc->sc_freq + (speed - 1)) / speed;
186 for (div_cnt = 0; div > 0; div_cnt++)
187 div >>= 1
    [all...]
  /src/sys/arch/arm/nxp/
imx_ccm_div.c 45 struct imx_ccm_div *div = &clk->u.div; local
59 const uint32_t val = CCM_READ(sc, clk->regidx, div->reg);
60 const u_int n = __SHIFTOUT(val, div->mask);
69 struct imx_ccm_div *div = &clk->u.div; local
82 if ((div->flags & IMX_DIV_SET_RATE_PARENT) != 0)
89 for (n = 0; n < __SHIFTOUT_MASK(div->mask); n++) {
92 if ((div->flags & IMX_DIV_ROUND_DOWN) != 0) {
107 val = CCM_READ(sc, clk->regidx, div->reg)
119 struct imx_ccm_div *div = &clk->u.div; local
    [all...]
imx_ccm_pll.c 92 const u_int div = __SHIFTOUT(val, pll->div_mask); local
95 return prate * div / 2;
99 return div == 1 ? 528000000 : 480000000;
  /src/sys/arch/arm/sunxi/
sunxi_ccu_prediv.c 45 u_int rate, pre, div, sel; local
64 if (prediv->div)
65 div = __SHIFTOUT(val, prediv->div);
67 div = 0;
71 div = 1 << div;
73 div++;
84 return rate / pre / div;
86 return rate / div;
    [all...]
sunxi_ccu_div.c 43 struct sunxi_ccu_div *div = &clk->u.div; local
48 if (!div->enable)
51 val = CCU_READ(sc, div->reg);
53 val |= div->enable;
55 val &= ~div->enable;
56 CCU_WRITE(sc, div->reg, val);
65 struct sunxi_ccu_div *div = &clk->u.div; local
81 val = CCU_READ(sc, div->reg)
105 struct sunxi_ccu_div *div = &clk->u.div; local
137 struct sunxi_ccu_div *div = &clk->u.div; local
187 struct sunxi_ccu_div *div = &clk->u.div; local
216 struct sunxi_ccu_div *div = &clk->u.div; local
    [all...]
sun8i_a23_apbclk.c 175 const u_int div = __SHIFTOUT(val, APB0_DIV); local
177 return clk_get_rate(clk_parent) / (div + 1);
  /src/sys/external/bsd/drm2/dist/drm/nouveau/
nouveau_led.c 47 u32 div, duty; local
49 div = nvif_rd32(device, 0x61c880) & 0x00ffffff;
52 if (div > 0)
53 return duty * LED_FULL / div;
67 u32 div, duty; local
69 div = input_clk / freq;
70 duty = value * div / LED_FULL;
77 nvif_wr32(device, 0x61c880, div);
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/
nouveau_nvkm_engine_disp_sornv50.c 37 const int div = sor->asy.link == 3; local
39 nvkm_mask(device, 0x614300 + soff, 0x00000707, (div << 8) | div);
  /src/sys/arch/arm/broadcom/
bcm53xx_mdio.c 95 uint32_t div = __SHIFTOUT(miimgt, MIIMGT_MDCDIV); local
96 if (div == 0) {
97 div = 33; // divisor to get 2MHz
99 miimgt |= __SHIFTIN(div, MIIMGT_MDCDIV);
102 uint32_t freq = 66000000 / div;
  /src/sys/arch/arm/rockchip/
rk_cru_arm.c 58 const u_int div = __SHIFTOUT(val, arm->divs[0].mask) + 1; local
60 return fref / div;
96 const u_int parent_rate = arm_rate->rate / arm_rate->div;
107 const uint32_t write_val = __SHIFTIN(arm_rate->div - 1,
rk_cru_composite.c 86 u_int div; local
89 div = 1U << __SHIFTOUT(val, composite->div_mask);
91 div = __SHIFTOUT(val, composite->div_mask) * 2 + 3;
92 return ((uint64_t)prate * 2 + div - 1) / div;
94 div = (composite->div_mask != 0)
97 return prate / div;
183 for (u_int div = 1; div <= __SHIFTOUT_MASK(composite->div_mask) + 1; div++)
    [all...]
  /src/sys/dev/fdt/
fixedfactorclock.c 64 u_int div; member in struct:fixedfactorclock_clk
106 of_getprop_uint32(phandle, "clock-div", &sc->sc_clk.div);
109 if (sc->sc_clk.div == 0 || sc->sc_clk.mult == 0) {
124 sc->sc_clk.mult, sc->sc_clk.div);
170 return (clk_get_rate(clkp_parent) * fclk->mult) / fclk->div;
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/volt/
nouveau_nvkm_subdev_volt_gk104.c 48 u32 div, duty; local
50 div = nvkm_rd32(device, 0x20340);
53 return bios->base + bios->pwm_range * duty / div;
61 u32 div, duty; local
64 div = 27648000 / bios->pwm_freq;
65 duty = DIV_ROUND_UP((uv - bios->base) * div, bios->pwm_range);
67 nvkm_wr32(device, 0x20340, div);
  /src/sys/arch/arm/nvidia/
tegra_clock.h 46 u_int div; member in struct:tegra_fixed_div_clk
85 struct tegra_div_clk div; member in union:tegra_clk::__anon1099
  /src/sys/arch/arm/samsung/
exynos_clock.h 80 struct exynos_div_clk div; member in union:exynos_clk::__anon1147

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