| /src/external/gpl3/gdb/dist/sim/testsuite/or1k/ |
| fpu.S | 124 div0: lf.div.s r2, r8, r0 label
125 REPORT_EXCEPTION div0
|
| fpu64a32.S | 167 div0: lf.div.d r2,r3, r12,r13, r0,r1 label
168 REPORT_EXCEPTION div0
|
| /src/external/gpl3/gdb.old/dist/sim/testsuite/or1k/ |
| fpu.S | 124 div0: lf.div.s r2, r8, r0 label
125 REPORT_EXCEPTION div0
|
| fpu64a32.S | 167 div0: lf.div.d r2,r3, r12,r13, r0,r1 label
168 REPORT_EXCEPTION div0
|
| /src/external/gpl3/gcc/dist/libgcc/config/sh/ |
| lib1funcs.S | 1095 bt div0
1171 div0: rts label
|
| /src/external/gpl3/gcc.old/dist/libgcc/config/sh/ |
| lib1funcs.S | 1095 bt div0
1171 div0: rts label
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/ |
| nouveau_nvkm_subdev_clk_gf100.c | 283 u32 src0, div0, div1D, div1P = 0; local
291 clk0 = calc_src(clk, idx, freq, &src0, &div0);
306 if (div0) {
308 info->ddiv |= div0 << 8;
309 info->ddiv |= div0;
|
| nouveau_nvkm_subdev_clk_gk104.c | 297 u32 src0, div0, div1D, div1P = 0; local
305 clk0 = calc_src(clk, idx, freq, &src0, &div0);
320 if (div0) {
322 info->ddiv |= div0;
|
| /src/sys/dev/pci/ |
| radeonfb.c | 2144 uint32_t data, refdiv, div0, r2xxref; local
2169 div0 = GETPLL(sc, RADEON_PPLL_DIV_0);
2170 DPRINTF(("div0 %08x\n", div0));
2171 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK |
2173 div0 |= pbit;
2174 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK);
2175 DPRINTF(("div0 %08x\n", div0));
2178 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0)))
[all...] |
