| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/ |
| nouveau_nvkm_engine_disp_sorgf119.c | 130 u32 div2 = sor->asy.link == 3; local in function:gf119_sor_clock
135 div2 = 1;
137 nvkm_mask(device, 0x612300 + soff, 0x00000707, (div2 << 8) | div1);
|
| /src/sys/arch/mips/atheros/ |
| ar5315.c | 171 const uint32_t div2 = (AR5315_PLLC_DIV_2(pllc) + 1) * 2; /* results in 2 or 4 */ local in function:ar5315_get_freqs
176 freqs->freq_pll = (freqs->freq_ref / refdiv) * div2 * fbdiv;
|
| /src/sys/dev/i2c/ |
| adm1026.c | 288 uint8_t div1, div2; local in function:adm1026_setup_fans
305 adm1026_read_reg(sc, ADM1026_FAN_DIV2, &div2)) != 0) {
311 div2 = div2_val;
312 sc->sc_fandiv[4] = 1 << ADM1026_FAN4_DIV(div2);
313 sc->sc_fandiv[5] = 1 << ADM1026_FAN5_DIV(div2);
314 sc->sc_fandiv[6] = 1 << ADM1026_FAN6_DIV(div2);
315 sc->sc_fandiv[7] = 1 << ADM1026_FAN7_DIV(div2);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_ddi.c | 1458 u32 m1, m2_int, m2_frac, div1, div2, ref_clock; local in function:icl_calc_mg_pll_link
1507 div2 = (pll_state->mg_clktop2_hsclkctl &
1511 /* div2 value of 0 is same as 1 means no div */
1512 if (div2 == 0)
1513 div2 = 1;
1521 tmp = div_u64(tmp, 5 * div1 * div2);
|
| intel_dpll_mgr.c | 2679 int div2; local in function:icl_mg_pll_find_divisors
2687 for (div2 = 10; div2 > 0; div2--) {
2688 int dco = div1 * div2 * clock_khz * 5;
2695 if (div2 >= 2) {
2738 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2);
|
