| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/therm/ |
| nouveau_nvkm_subdev_therm_fanpwm.c | 49 u32 divs, duty; local in function:nvkm_fanpwm_get
52 ret = therm->func->pwm_get(therm, fan->func.line, &divs, &duty);
53 if (ret == 0 && divs) {
54 divs = max(divs, duty);
56 duty = divs - duty;
57 return (duty * 100) / divs;
68 u32 divs, duty; local in function:nvkm_fanpwm_set
71 divs = fan->base.perf.pwm_divisor;
73 divs = 1
96 u32 divs, duty; local in function:nvkm_fanpwm_create
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/ |
| nouveau_nvkm_subdev_clk_mcp77.c | 217 int divs = 0; local in function:mcp77_clk_calc
221 out = calc_P(nvkm_clk_read(&clk->base, nv_clk_src_hclkm4), core, &divs);
228 clk->cctrl = divs << 16;
252 out = calc_P((core << 1), shader, &divs);
256 (divs + P2) <= 7) {
258 clk->sctrl = (divs + P2) << 16;
267 out = calc_P(core, vdec, &divs);
271 clk->vdiv = divs << 16;
|
| /src/sys/arch/arm/rockchip/ |
| rk_cru.h | 161 struct rk_regmaskval divs[4]; member in struct:rk_cru_cpu_rate
176 struct rk_regmask divs[4]; member in struct:rk_cru_arm
202 .u.arm.divs[0].reg = (_reg), \
203 .u.arm.divs[0].mask = (_div_mask), \
236 .u.arm.divs[0].reg = (_div_reg), \
237 .u.arm.divs[0].mask = (_div_mask), \
248 .u.arm.divs[0].reg = (_div0_reg), \
249 .u.arm.divs[0].mask = (_div0_mask), \
250 .u.arm.divs[1].reg = (_div1_reg), \
251 .u.arm.divs[1].mask = (_div1_mask),
[all...] |
| /src/sys/arch/sgimips/dev/ |
| scn.c | 358 } divs[] = { variable in typeref:typename:const struct __anon283617d60108[]
365 #define DIVS (sizeof(divs)/sizeof(divs[0]))
492 #ifdef DIVS
496 for (i = 0; i < DIVS && divs[i].speed <= dp->counter; i++) {
497 if (divs[i].speed == dp->counter) {
498 div = divs[i].div;
|
