| /src/sys/dev/dmover/ |
| dmover_backend.c | 81 dmover_backend_register(struct dmover_backend *dmb)
89 LIST_INIT(&dmb->dmb_sessions);
90 dmb->dmb_nsessions = 0;
92 TAILQ_INIT(&dmb->dmb_pendreqs);
93 dmb->dmb_npendreqs = 0;
96 TAILQ_INSERT_TAIL(&dmover_backend_list, dmb, dmb_list);
106 dmover_backend_unregister(struct dmover_backend *dmb)
112 if (dmb->dmb_nsessions)
116 TAILQ_REMOVE(&dmover_backend_list, dmb, dmb_list);
128 struct dmover_backend *dmb, *best_dmb = NULL local
215 struct dmover_backend *dmb; local
[all...] |
| dmover_process.c | 86 struct dmover_backend *dmb; local
105 dmb = das->das_backend;
109 dmover_backend_insque(dmb, dreq);
116 (*dmb->dmb_process)(das->das_backend);
|
| swdmover.c | 77 swdmover_process(struct dmover_backend *dmb)
88 if (TAILQ_EMPTY(&dmb->dmb_pendreqs) == 0)
102 struct dmover_backend *dmb = arg; local
111 dreq = TAILQ_FIRST(&dmb->dmb_pendreqs);
118 dmover_backend_remque(dmb, dreq);
|
| /src/sys/arch/arm/xscale/ |
| iopaau.c | 113 struct dmover_backend *dmb = &sc->sc_dmb; local
122 dreq = TAILQ_FIRST(&dmb->dmb_pendreqs);
126 dmover_backend_remque(dmb, dreq);
209 iopaau_process(struct dmover_backend *dmb)
211 struct iopaau_softc *sc = dmb->dmb_cookie;
|
| /src/sys/arch/arm/include/ |
| cpufunc.h | 47 * Options for DMB and DSB:
62 #define dmb(opt) __asm __volatile("dmb " __STRING(opt) : : : "memory") macro
70 #define dmb(opt) \ macro
|
| /src/sys/dev/marvell/ |
| gtidmac.c | 729 gtidmac_process(struct dmover_backend *dmb)
731 struct gtidmac_softc *sc = dmb->dmb_cookie;
737 gtidmac_dmover_run(dmb);
742 gtidmac_dmover_run(struct dmover_backend *dmb)
744 struct gtidmac_softc *sc = dmb->dmb_cookie;
754 dreq = TAILQ_FIRST(&dmb->dmb_pendreqs);
763 dmover_backend_remque(dmb, dreq);
854 struct dmover_backend *dmb; local
861 dmb = dreq->dreq_assignment->das_backend;
864 sc = dmb->dmb_cookie
[all...] |
| /src/external/gpl3/gdb/dist/sim/aarch64/ |
| simulator.c | 13502 dmb (sim_cpu *cpu) function
14138 /* We are interested in HINT, DSB, DMB and ISB
14144 DSB, DMB, ISB are data store barrier, data memory barrier and
14148 op2 : DSB ==> 100, DMB ==> 101, ISB ==> 110
14186 case 5: dmb (cpu); return;
|
| /src/external/gpl3/gdb.old/dist/sim/aarch64/ |
| simulator.c | 13502 dmb (sim_cpu *cpu) function
14138 /* We are interested in HINT, DSB, DMB and ISB
14144 DSB, DMB, ISB are data store barrier, data memory barrier and
14148 op2 : DSB ==> 100, DMB ==> 101, ISB ==> 110
14186 case 5: dmb (cpu); return;
|
