1 /* $NetBSD: dpclock.c,v 1.9 2025/09/07 21:45:14 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Erik Reid 5 * Copyright (c) 2001 Rafal K. Boni 6 * Copyright (c) 2001 Christopher Sekiya 7 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 8 * All rights reserved. 9 * 10 * Portions of this code are derived from software contributed to The 11 * NetBSD Foundation by Jason R. Thorpe of the Numerical Aerospace 12 * Simulation Facility, NASA Ames Research Center. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/kernel.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 42 #include <sys/bus.h> 43 #include <machine/autoconf.h> 44 #include <machine/sysconf.h> 45 #include <machine/machtype.h> 46 47 #include <dev/clock_subr.h> 48 #include <sgimips/dev/dp8573areg.h> 49 50 #include <sgimips/sgimips/clockvar.h> 51 52 struct dpclock_softc { 53 device_t sc_dev; 54 struct todr_chip_handle sc_todrch; 55 56 /* RTC registers */ 57 bus_space_tag_t sc_rtct; 58 bus_space_handle_t sc_rtch; 59 int sc_offset; 60 }; 61 62 static int dpclock_match(device_t, cfdata_t, void *); 63 static void dpclock_attach(device_t, device_t, void *); 64 static int dpclock_gettime_ymdhms(struct todr_chip_handle *, 65 struct clock_ymdhms *); 66 static int dpclock_settime_ymdhms(struct todr_chip_handle *, 67 struct clock_ymdhms *); 68 69 CFATTACH_DECL_NEW(dpclock, sizeof(struct dpclock_softc), 70 dpclock_match, dpclock_attach, NULL, NULL); 71 72 static int 73 dpclock_match(device_t parent, cfdata_t cf, void *aux) 74 { 75 struct mainbus_attach_args *ma = aux; 76 77 switch (mach_type) { 78 case MACH_SGI_IP6 | MACH_SGI_IP10: 79 if (ma->ma_addr == 0x1fbc0000) 80 return (1); 81 break; 82 83 case MACH_SGI_IP12: 84 case MACH_SGI_IP20: 85 if (ma->ma_addr == 0x1fb80e00) 86 return (1); 87 break; 88 } 89 90 return (0); 91 } 92 93 static void 94 writereg(struct dpclock_softc *sc, uint32_t reg, uint8_t val) 95 { 96 bus_space_write_1(sc->sc_rtct, sc->sc_rtch, 97 (reg << 2) + sc->sc_offset, val); 98 } 99 100 static uint8_t 101 readreg(struct dpclock_softc *sc, uint32_t reg) 102 { 103 return bus_space_read_1(sc->sc_rtct, sc->sc_rtch, 104 (reg << 2) + sc->sc_offset); 105 } 106 107 static void 108 dpclock_attach(device_t parent, device_t self, void *aux) 109 { 110 struct dpclock_softc *sc = device_private(self); 111 struct mainbus_attach_args *ma = aux; 112 int err; 113 114 printf("\n"); 115 116 sc->sc_dev = self; 117 sc->sc_rtct = normal_memt; 118 /* 119 * All machines have one byte register per word. IP6/IP10 use 120 * the MSB, others the LSB. 121 */ 122 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20) 123 sc->sc_offset = 3; 124 else 125 sc->sc_offset = 0; 126 127 if ((err = bus_space_map(sc->sc_rtct, ma->ma_addr, 0x1ffff, 128 BUS_SPACE_MAP_LINEAR, &sc->sc_rtch)) != 0) { 129 printf(": unable to map RTC registers, error = %d\n", err); 130 return; 131 } 132 133 sc->sc_todrch.todr_dev = self; 134 sc->sc_todrch.todr_gettime_ymdhms = dpclock_gettime_ymdhms; 135 sc->sc_todrch.todr_settime_ymdhms = dpclock_settime_ymdhms; 136 137 todr_attach(&sc->sc_todrch); 138 } 139 140 /* 141 * Get the time of day, based on the clock's value and/or the base value. 142 */ 143 static int 144 dpclock_gettime_ymdhms(struct todr_chip_handle *todrch, struct clock_ymdhms *dt) 145 { 146 struct dpclock_softc *sc = device_private(todrch->todr_dev); 147 int s; 148 u_int8_t i, j; 149 u_int8_t regs[32]; 150 151 s = splhigh(); 152 i = readreg(sc, DP8573A_TIMESAVE_CTL); 153 j = i | DP8573A_TIMESAVE_CTL_EN; 154 writereg(sc, DP8573A_TIMESAVE_CTL, j); 155 writereg(sc, DP8573A_TIMESAVE_CTL, i); 156 splx(s); 157 158 for (i = 0; i < 32; i++) 159 regs[i] = readreg(sc, i); 160 161 dt->dt_sec = bcdtobin(regs[DP8573A_SAVE_SEC]); 162 dt->dt_min = bcdtobin(regs[DP8573A_SAVE_MIN]); 163 164 if (regs[DP8573A_RT_MODE] & DP8573A_RT_MODE_1224) { 165 dt->dt_hour = bcdtobin(regs[DP8573A_SAVE_HOUR] & 166 DP8573A_HOUR_12HR_MASK) + 167 ((regs[DP8573A_SAVE_HOUR] & DP8573A_RT_MODE_1224) ? 0 : 12); 168 169 /* 170 * In AM/PM mode, hour range is 01-12, so adding in 12 hours 171 * for PM gives us 01-24, whereas we want 00-23, so map hour 172 * 24 to hour 0. 173 */ 174 175 if (dt->dt_hour == 24) 176 dt->dt_hour = 0; 177 } else { 178 dt->dt_hour = bcdtobin(regs[DP8573A_SAVE_HOUR] & 179 DP8573A_HOUR_24HR_MASK); 180 } 181 182 dt->dt_wday = bcdtobin(regs[DP8573A_DOW]); /* Not from time saved */ 183 dt->dt_day = bcdtobin(regs[DP8573A_SAVE_DOM]); 184 dt->dt_mon = bcdtobin(regs[DP8573A_SAVE_MONTH]); 185 dt->dt_year = FROM_IRIX_YEAR(bcdtobin(regs[DP8573A_YEAR])); 186 187 return (0); 188 } 189 190 /* 191 * Reset the TODR based on the time value. 192 */ 193 static int 194 dpclock_settime_ymdhms(struct todr_chip_handle *todrch, struct clock_ymdhms *dt) 195 { 196 struct dpclock_softc *sc = device_private(todrch->todr_dev); 197 int s; 198 u_int8_t i, j; 199 u_int8_t regs[32]; 200 201 s = splhigh(); 202 i = readreg(sc, DP8573A_TIMESAVE_CTL); 203 j = i | DP8573A_TIMESAVE_CTL_EN; 204 writereg(sc, DP8573A_TIMESAVE_CTL, j); 205 writereg(sc, DP8573A_TIMESAVE_CTL, i); 206 splx(s); 207 208 for (i = 0; i < 32; i++) 209 regs[i] = readreg(sc, i); 210 211 regs[DP8573A_SUBSECOND] = 0; 212 regs[DP8573A_SECOND] = bintobcd(dt->dt_sec); 213 regs[DP8573A_MINUTE] = bintobcd(dt->dt_min); 214 regs[DP8573A_HOUR] = bintobcd(dt->dt_hour) & DP8573A_HOUR_24HR_MASK; 215 regs[DP8573A_DOW] = bintobcd(dt->dt_wday); 216 regs[DP8573A_DOM] = bintobcd(dt->dt_day); 217 regs[DP8573A_MONTH] = bintobcd(dt->dt_mon); 218 regs[DP8573A_YEAR] = bintobcd(TO_IRIX_YEAR(dt->dt_year)); 219 220 s = splhigh(); 221 i = readreg(sc, DP8573A_RT_MODE); 222 j = i & ~DP8573A_RT_MODE_CLKSS; 223 writereg(sc, DP8573A_RT_MODE, j); 224 225 for (i = 0; i < 10; i++) 226 writereg(sc, DP8573A_COUNTERS +i, regs[DP8573A_COUNTERS + i]); 227 228 writereg(sc, DP8573A_RT_MODE, i); 229 splx(s); 230 231 return (0); 232 } 233
Indexes created Tue Sep 23 14:10:03 GMT 2025