1 /* $NetBSD: dpt_isa.c,v 1.23 2016/07/14 10:19:06 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Andrew Doran <ad (at) NetBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 /* 31 * ISA front-end for DPT EATA SCSI driver. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: dpt_isa.c,v 1.23 2016/07/14 10:19:06 msaitoh Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/queue.h> 41 42 #include <sys/bus.h> 43 #include <sys/intr.h> 44 45 #include <dev/scsipi/scsipi_all.h> 46 #include <dev/scsipi/scsiconf.h> 47 48 #include <dev/isa/isareg.h> 49 #include <dev/isa/isavar.h> 50 51 #include <dev/isa/isadmareg.h> 52 #include <dev/isa/isadmavar.h> 53 54 #include <dev/ic/dptreg.h> 55 #include <dev/ic/dptvar.h> 56 57 #include <dev/i2o/dptivar.h> 58 59 #define DPT_ISA_IOSIZE 16 60 #define DPT_ISA_MAXCCBS 16 61 62 static void dpt_isa_attach(device_t, device_t, void *); 63 static int dpt_isa_match(device_t, cfdata_t, void *); 64 static int dpt_isa_probe(struct isa_attach_args *, int); 65 static int dpt_isa_wait(bus_space_handle_t, bus_space_tag_t, u_int8_t, 66 u_int8_t); 67 68 CFATTACH_DECL_NEW(dpt_isa, sizeof(struct dpt_softc), 69 dpt_isa_match, dpt_isa_attach, NULL, NULL); 70 71 /* Try 'less intrusive' addresses first */ 72 static const int dpt_isa_iobases[] = { 0x230, 0x330, 0x1f0, 0x170, 0 }; 73 74 /* 75 * Wait for the HBA status register to reach a specific state. 76 */ 77 static int 78 dpt_isa_wait(bus_space_handle_t ioh, bus_space_tag_t iot, u_int8_t mask, 79 u_int8_t state) 80 { 81 int ms; 82 83 for (ms = 2000 * 10; ms; ms--) { 84 if ((bus_space_read_1(iot, ioh, HA_STATUS) & mask) == state) 85 return (0); 86 DELAY(100); 87 } 88 89 return (-1); 90 } 91 92 /* 93 * Match a supported board. 94 */ 95 static int 96 dpt_isa_match(device_t parent, cfdata_t match, void *aux) 97 { 98 struct isa_attach_args *ia = aux; 99 int i; 100 101 if (ia->ia_nio < 1) 102 return (0); 103 if (ia->ia_nirq < 1) 104 return (0); 105 if (ia->ia_ndrq < 1) 106 return (0); 107 108 if (ISA_DIRECT_CONFIG(ia)) 109 return (0); 110 111 if (ia->ia_io[0].ir_addr != ISA_UNKNOWN_PORT) 112 return (dpt_isa_probe(ia, ia->ia_io[0].ir_addr)); 113 114 for (i = 0; dpt_isa_iobases[i] != 0; i++) { 115 if (dpt_isa_probe(ia, dpt_isa_iobases[i])) { 116 ia->ia_io[0].ir_addr = dpt_isa_iobases[i]; 117 return (1); 118 } 119 } 120 121 return (0); 122 } 123 124 /* 125 * Probe for a supported board. 126 */ 127 static int 128 dpt_isa_probe(struct isa_attach_args *ia, int iobase) 129 { 130 struct eata_cfg ec; 131 bus_space_handle_t ioh; 132 bus_space_tag_t iot; 133 int i, j, stat, irq, drq; 134 u_int16_t *p; 135 136 iot = ia->ia_iot; 137 138 if (bus_space_map(iot, iobase, DPT_ISA_IOSIZE, 0, &ioh) != 0) 139 return(0); 140 141 /* 142 * Assumuing the DPT BIOS reset the board, we shouldn't need to 143 * re-do it here. The tests below should weed out non-EATA devices 144 * before we start poking any registers. 145 */ 146 for (i = 1000; i; i--) { 147 if ((bus_space_read_1(iot, ioh, HA_STATUS) & HA_ST_READY) != 0) 148 break; 149 DELAY(2000); 150 } 151 152 if (i == 0) 153 goto bad; 154 155 while((((stat = bus_space_read_1(iot, ioh, HA_STATUS)) 156 != (HA_ST_READY|HA_ST_SEEK_COMPLETE)) 157 && (stat != (HA_ST_READY|HA_ST_SEEK_COMPLETE|HA_ST_ERROR)) 158 && (stat != (HA_ST_READY|HA_ST_SEEK_COMPLETE|HA_ST_ERROR|HA_ST_DRQ))) 159 || (dpt_isa_wait(ioh, iot, HA_ST_BUSY, 0))) 160 /* RAID drives still spinning up? */ 161 if (bus_space_read_1(iot, ioh, HA_ERROR) != 'D' || 162 bus_space_read_1(iot, ioh, HA_ERROR + 1) != 'P' || 163 bus_space_read_1(iot, ioh, HA_ERROR + 2) != 'T') 164 goto bad; 165 166 /* 167 * At this point we can be confident that we are dealing with a DPT 168 * HBA. Issue the read-config command and wait for the data to 169 * appear. XXX We shouldn't be doing this with PIO, but it makes it 170 * a lot easier as no DMA setup is required. 171 */ 172 bus_space_write_1(iot, ioh, HA_COMMAND, CP_PIO_GETCFG); 173 memset(&ec, 0, sizeof(ec)); 174 i = ((uintptr_t)&((struct eata_cfg *)0)->ec_cfglen + 175 sizeof(ec.ec_cfglen)) >> 1; 176 p = (u_int16_t *)&ec; 177 178 if (dpt_isa_wait(ioh, iot, 0xFF, HA_ST_DATA_RDY)) 179 goto bad; 180 181 /* Begin reading */ 182 while (i--) 183 *p++ = bus_space_read_stream_2(iot, ioh, HA_DATA); 184 185 if ((i = ec.ec_cfglen) > (sizeof(struct eata_cfg) 186 - (uintptr_t)(&(((struct eata_cfg *)0L)->ec_cfglen)) 187 - sizeof(ec.ec_cfglen))) 188 i = sizeof(struct eata_cfg) 189 - (uintptr_t)(&(((struct eata_cfg *)0L)->ec_cfglen)) 190 - sizeof(ec.ec_cfglen); 191 192 j = i + (uintptr_t)(&(((struct eata_cfg *)0L)->ec_cfglen)) + 193 sizeof(ec.ec_cfglen); 194 i >>= 1; 195 196 while (i--) 197 *p++ = bus_space_read_stream_2(iot, ioh, HA_DATA); 198 199 /* Flush until we have read 512 bytes. */ 200 i = (512 - j + 1) >> 1; 201 while (i--) 202 bus_space_read_stream_2(iot, ioh, HA_DATA); 203 204 /* Puke if we don't like the returned configuration data. */ 205 if ((bus_space_read_1(iot, ioh, HA_STATUS) & HA_ST_ERROR) != 0 || 206 memcmp(ec.ec_eatasig, "EATA", 4) != 0 || 207 (ec.ec_feat0 & (EC_F0_HBA_VALID | EC_F0_DMA_SUPPORTED)) != 208 (EC_F0_HBA_VALID | EC_F0_DMA_SUPPORTED)) 209 goto bad; 210 211 /* 212 * Which DMA channel to use: if it was hardwired in the kernel 213 * configuration, use that value. If the HBA told us, use that 214 * value. Otherwise, puke. 215 */ 216 if ((drq = ia->ia_drq[0].ir_drq) == ISA_UNKNOWN_DRQ) { 217 int dmanum = ((ec.ec_feat1 & EC_F1_DMA_NUM_MASK) >> 218 EC_F1_DMA_NUM_SHIFT); 219 220 if ((ec.ec_feat0 & EC_F0_DMA_NUM_VALID) == 0 || dmanum > 3) 221 goto bad; 222 drq = "\0\7\6\5"[dmanum]; 223 } 224 225 /* 226 * Which IRQ to use: if it was hardwired in the kernel configuration, 227 * use that value. Otherwise, use what the HBA told us. 228 */ 229 if ((irq = ia->ia_irq[0].ir_irq) == ISA_UNKNOWN_IRQ) 230 irq = ((ec.ec_feat1 & EC_F1_IRQ_NUM_MASK) >> 231 EC_F1_IRQ_NUM_SHIFT); 232 233 ia->ia_nio = 1; 234 ia->ia_io[0].ir_size = DPT_ISA_IOSIZE; 235 236 ia->ia_nirq = 1; 237 ia->ia_irq[0].ir_irq = irq; 238 239 ia->ia_ndrq = 1; 240 ia->ia_drq[0].ir_drq = drq; 241 242 ia->ia_niomem = 0; 243 244 bus_space_unmap(iot, ioh, DPT_ISA_IOSIZE); 245 return (1); 246 bad: 247 bus_space_unmap(iot, ioh, DPT_ISA_IOSIZE); 248 return (0); 249 } 250 251 /* 252 * Attach a matched board. 253 */ 254 static void 255 dpt_isa_attach(device_t parent, device_t self, void *aux) 256 { 257 struct isa_attach_args *ia; 258 isa_chipset_tag_t ic; 259 bus_space_handle_t ioh; 260 bus_space_tag_t iot; 261 struct dpt_softc *sc; 262 struct eata_cfg *ec; 263 int error; 264 265 ia = aux; 266 sc = device_private(self); 267 sc->sc_dev = self; 268 iot = ia->ia_iot; 269 ic = ia->ia_ic; 270 271 aprint_naive("\n"); 272 aprint_normal(": "); 273 274 if ((error = bus_space_map(iot, ia->ia_io[0].ir_addr, DPT_ISA_IOSIZE, 275 0, &ioh)) != 0) { 276 aprint_error("can't map i/o space, error = %d\n", error); 277 return; 278 } 279 280 sc->sc_iot = iot; 281 sc->sc_ioh = ioh; 282 sc->sc_dmat = ia->ia_dmat; 283 284 if ((error = isa_dmacascade(ic, ia->ia_drq[0].ir_drq)) != 0) { 285 aprint_error("unable to cascade DRQ, error = %d\n", error); 286 return; 287 } 288 289 /* Establish the interrupt. */ 290 sc->sc_ih = isa_intr_establish(ic, ia->ia_irq[0].ir_irq, IST_EDGE, 291 IPL_BIO, dpt_intr, sc); 292 if (sc->sc_ih == NULL) { 293 aprint_error("can't establish interrupt\n"); 294 return; 295 } 296 297 if (dpt_readcfg(sc)) { 298 aprint_error("readcfg failed - see dpt(4)\n"); 299 return; 300 } 301 302 /* 303 * Now attach to the bus-independent code. XXX We need to force 304 * parameters that aren't filled in by some ISA boards. In 305 * particular, due to the limited amount of memory we have to play 306 * with for DMA, clamp the number of CCBs to 16. 307 */ 308 ec = &sc->sc_ec; 309 310 if (be16toh(*(int16_t *)ec->ec_queuedepth) > DPT_ISA_MAXCCBS) 311 *(int16_t *)ec->ec_queuedepth = htobe16(DPT_ISA_MAXCCBS); 312 if (ec->ec_maxlun == 0) 313 ec->ec_maxlun = 7; 314 if ((ec->ec_feat3 & EC_F3_MAX_TARGET_MASK) >> EC_F3_MAX_TARGET_SHIFT 315 == 0) 316 ec->ec_feat3 = (ec->ec_feat3 & ~EC_F3_MAX_TARGET_MASK) | 317 (7 << EC_F3_MAX_TARGET_SHIFT); 318 319 sc->sc_bustype = SI_ISA_BUS; 320 sc->sc_isaport = ia->ia_io[0].ir_addr; 321 sc->sc_isairq = ia->ia_irq[0].ir_irq; 322 sc->sc_isadrq = ia->ia_drq[0].ir_drq; 323 324 dpt_init(sc, NULL); 325 } 326
Indexes created Wed Oct 01 15:09:59 GMT 2025