1 /* $NetBSD: scn.c,v 1.11 2023/12/20 15:29:07 thorpej Exp $ */ 2 3 /* 4 * Resurrected from the old pc532 port 1/18/2009. 5 * 6 * XXX- The locking in this is probably totally broken. I haven't attempted 7 * to get it right, but it seems to work okay anyhow. 8 */ 9 10 /* 11 * Copyright (c) 1991, 1992, 1993 12 * The Regents of the University of California. All rights reserved. 13 * 14 * Portions of this software were developed by the Computer Systems 15 * Engineering group at Lawrence Berkeley Laboratory under DARPA 16 * contract BG 91-66 and contributed to Berkeley. 17 * 18 * All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Lawrence Berkeley Laboratory. 22 * 23 * Redistribution and use in source and binary forms, with or without 24 * modification, are permitted provided that the following conditions 25 * are met: 26 * 1. Redistributions of source code must retain the above copyright 27 * notice, this list of conditions and the following disclaimer. 28 * 2. Redistributions in binary form must reproduce the above copyright 29 * notice, this list of conditions and the following disclaimer in the 30 * documentation and/or other materials provided with the distribution. 31 * 3. Neither the name of the University nor the names of its contributors 32 * may be used to endorse or promote products derived from this software 33 * without specific prior written permission. 34 * 35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 45 * SUCH DAMAGE. 46 * 47 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 48 */ 49 50 /* 51 * Copyright (c) 1996, 1997 Philip L. Budne. 52 * Copyright (c) 1993 Philip A. Nelson. 53 * 54 * Portions of this software were developed by the Computer Systems 55 * Engineering group at Lawrence Berkeley Laboratory under DARPA 56 * contract BG 91-66 and contributed to Berkeley. 57 * 58 * All advertising materials mentioning features or use of this software 59 * must display the following acknowledgement: 60 * This product includes software developed by the University of 61 * California, Lawrence Berkeley Laboratory. 62 * 63 * Redistribution and use in source and binary forms, with or without 64 * modification, are permitted provided that the following conditions 65 * are met: 66 * 1. Redistributions of source code must retain the above copyright 67 * notice, this list of conditions and the following disclaimer. 68 * 2. Redistributions in binary form must reproduce the above copyright 69 * notice, this list of conditions and the following disclaimer in the 70 * documentation and/or other materials provided with the distribution. 71 * 3. All advertising materials mentioning features or use of this software 72 * must display the following acknowledgement: 73 * This product includes software developed by the University of 74 * California, Berkeley and its contributors. 75 * 4. Neither the name of the University nor the names of its contributors 76 * may be used to endorse or promote products derived from this software 77 * without specific prior written permission. 78 * 79 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 80 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 82 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 85 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 86 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 87 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 88 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 89 * SUCH DAMAGE. 90 * 91 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 92 */ 93 94 #include <sys/cdefs.h> 95 __KERNEL_RCSID(0, "$NetBSD: scn.c,v 1.11 2023/12/20 15:29:07 thorpej Exp $"); 96 97 #include "opt_ddb.h" 98 #include "opt_kgdb.h" 99 #include "scn.h" 100 101 #include <sys/param.h> 102 #include <sys/systm.h> 103 #include <sys/ioctl.h> 104 #include <sys/select.h> 105 #include <sys/tty.h> 106 #include <sys/proc.h> 107 #include <sys/file.h> 108 #include <sys/uio.h> 109 #include <sys/kernel.h> 110 #include <sys/syslog.h> 111 #include <sys/types.h> 112 #include <sys/device.h> 113 #include <sys/conf.h> 114 #include <sys/intr.h> 115 #ifdef KGDB 116 #include <sys/kgdb.h> 117 #endif 118 #include <sys/kauth.h> 119 120 #include <dev/cons.h> 121 122 #include <machine/autoconf.h> 123 #include <machine/machtype.h> 124 125 #include <sgimips/dev/scnreg.h> 126 #include <sgimips/dev/scnvar.h> 127 128 int scn_match(device_t, struct cfdata *, void *); 129 void scn_attach(device_t, device_t, void *); 130 int scnparam(struct tty *, struct termios *); 131 void scnstart(struct tty *); 132 int scnhwiflow(struct tty *, int); 133 134 void scncnprobe(struct consdev *); 135 void scncninit(struct consdev *); 136 int scncngetc(dev_t); 137 void scncnputc(dev_t, int); 138 void scncnpollc(dev_t, int); 139 int scninit(dev_t, int); 140 void scncnreinit(void *); 141 142 CFATTACH_DECL_NEW(scn, sizeof(struct scn_softc), 143 scn_match, scn_attach, NULL, NULL); 144 145 extern struct cfdriver scn_cd; 146 147 dev_type_open(scnopen); 148 dev_type_close(scnclose); 149 dev_type_read(scnread); 150 dev_type_write(scnwrite); 151 dev_type_ioctl(scnioctl); 152 dev_type_stop(scnstop); 153 dev_type_tty(scntty); 154 dev_type_poll(scnpoll); 155 156 const struct cdevsw scn_cdevsw = { 157 .d_open = scnopen, 158 .d_close = scnclose, 159 .d_read = scnread, 160 .d_write = scnwrite, 161 .d_ioctl = scnioctl, 162 .d_stop = scnstop, 163 .d_tty = scntty, 164 .d_poll = scnpoll, 165 .d_mmap = nommap, 166 .d_kqfilter = ttykqfilter, 167 .d_discard = nodiscard, 168 .d_flag = D_TTY 169 }; 170 171 struct consdev scn_cn = { 172 scncnprobe, 173 scncninit, 174 scncngetc, 175 scncnputc, 176 scncnpollc, 177 NULL, 178 NULL, 179 NULL, 180 NODEV, 181 CN_NORMAL 182 }; 183 184 #ifndef CONSOLE_SPEED 185 #define CONSOLE_SPEED TTYDEF_SPEED 186 #endif 187 188 #ifndef SCNDEF_CFLAG 189 #define SCNDEF_CFLAG TTYDEF_CFLAG 190 #endif 191 192 #ifdef CPU30MHZ 193 #define RECOVER() __asm volatile("bispsrw 0x800" : : : "cc") 194 #else 195 #define RECOVER() 196 #endif 197 198 int scndefaultrate = TTYDEF_SPEED; 199 int scnconsrate = CONSOLE_SPEED; 200 201 static inline struct scn_softc * 202 SOFTC(int unit) 203 { 204 if (unit < 0 || unit >= scn_cd.cd_ndevs) 205 return (NULL); 206 return device_private(scn_cd.cd_devs[unit]); 207 } 208 209 static int scnintr(void *); 210 static void scnrxintr(void *); 211 static int scn_rxintr(struct scn_softc *); 212 static void scnsoft(void *); 213 static void scn_setchip(struct scn_softc *sc); 214 static int scniter(int *, int, int*, int*, struct chan *, int); 215 static int scn_config(int, int, int, int, u_char, u_char); 216 static void scn_rxenable(struct scn_softc *); 217 static void scn_rxdisable(struct scn_softc *); 218 static void dcd_int(struct scn_softc *, struct tty *, u_char); 219 static void scnoverrun(int, long *, const char *); 220 static u_char opbits(struct scn_softc *, int); 221 222 static void *scnsir = NULL; /* s/w intr cookie */ 223 #define setsoftscn() softint_schedule(scnsir) 224 225 #ifdef SCN_TIMING 226 /* 227 * Keep timing info on latency of software interrupt used by 228 * the ringbuf code to empty ring buffer. 229 * "getinfo" program reads data from /dev/kmem. 230 */ 231 static struct timeval tstart; 232 #define NJITTER 100 233 int scn_njitter = NJITTER; 234 int scn_jitter[NJITTER]; 235 #endif 236 237 #define SCN_CLOCK 3686400 /* input clock */ 238 239 /* speed table groups ACR[7] */ 240 #define GRP_A 0 241 #define GRP_B ACR_BRG 242 243 /* combo of MR0[2:0] and ACR[7] */ 244 #define MODE0A MR0_MODE_0 245 #define MODE0B (MR0_MODE_0|ACR_BRG) 246 #define MODE1A MR0_MODE_1 247 #define MODE1B (MR0_MODE_1|ACR_BRG) 248 #define MODE2A MR0_MODE_2 249 #define MODE2B (MR0_MODE_2|ACR_BRG) 250 251 #define ANYMODE -1 252 #define DEFMODE(C92) MODE0A /* use MODE4A if 26c92? */ 253 254 /* speed code for Counter/Timer (all modes, groups) */ 255 #define USE_CT 0xd 256 257 /* 258 * Rate table, ordered by speed, then mode. 259 * NOTE: ordering of modes must be done carefully! 260 */ 261 struct tabent { 262 int32_t speed; 263 int16_t code; 264 int16_t mode; 265 } table[] = { 266 { 50, 0x0, MODE0A }, 267 { 75, 0x0, MODE0B }, 268 { 110, 0x1, MODE0A }, 269 { 110, 0x1, MODE0B }, 270 { 110, 0x1, MODE1A }, 271 { 110, 0x1, MODE1B }, 272 { 134, 0x2, MODE0A }, /* 134.5 */ 273 { 134, 0x2, MODE0B }, /* 134.5 */ 274 { 134, 0x2, MODE1A }, /* 134.5 */ 275 { 134, 0x2, MODE1B }, /* 134.5 */ 276 { 150, 0x3, MODE0A }, 277 { 150, 0x3, MODE0A }, 278 { 200, 0x3, MODE0A }, 279 { 300, 0x4, MODE0A }, 280 { 300, 0x4, MODE0B }, 281 { 300, 0x0, MODE1A }, 282 { 450, 0x0, MODE1B }, 283 { 600, 0x5, MODE0A }, 284 { 600, 0x5, MODE0B }, 285 { 880, 0x1, MODE2A }, 286 { 880, 0x1, MODE2B }, 287 { 900, 0x3, MODE1B }, 288 { 1050, 0x7, MODE0A }, 289 { 1050, 0x7, MODE1A }, 290 { 1076, 0x2, MODE2A }, 291 { 1076, 0x2, MODE2B }, 292 { 1200, 0x6, MODE0A }, 293 { 1200, 0x6, MODE0B }, 294 { 1200, 0x3, MODE1A }, 295 { 1800, 0xa, MODE0B }, 296 { 1800, 0x4, MODE1A }, 297 { 1800, 0x4, MODE1B }, 298 { 2000, 0x7, MODE0B }, 299 { 2000, 0x7, MODE1B }, 300 { 2400, 0x8, MODE0A }, 301 { 2400, 0x8, MODE0B }, 302 { 3600, 0x5, MODE1A }, 303 { 3600, 0x5, MODE1B }, 304 { 4800, 0x9, MODE2A }, 305 { 4800, 0x9, MODE2B }, 306 { 4800, 0x9, MODE0A }, 307 { 4800, 0x9, MODE0B }, 308 { 7200, 0xa, MODE0A }, 309 { 7200, 0x0, MODE2B }, 310 { 7200, 0x6, MODE1A }, 311 { 7200, 0x6, MODE1B }, 312 { 9600, 0xb, MODE2A }, 313 { 9600, 0xb, MODE2B }, 314 { 9600, 0xb, MODE0A }, 315 { 9600, 0xb, MODE0B }, 316 { 9600, 0xd, MODE1A }, /* use C/T as entre' to mode1 */ 317 { 9600, 0xd, MODE1B }, /* use C/T as entre' to mode1 */ 318 { 14400, 0x3, MODE2B }, 319 { 14400, 0x8, MODE1A }, 320 { 14400, 0x8, MODE1B }, 321 { 19200, 0x3, MODE2A }, 322 { 19200, 0xc, MODE2B }, 323 { 19200, 0xc, MODE0B }, 324 { 19200, 0xd, MODE1A }, /* use C/T as entre' to mode1 */ 325 { 19200, 0xd, MODE1B }, /* use C/T as entre' to mode1 */ 326 { 28800, 0x4, MODE2A }, 327 { 28800, 0x4, MODE2B }, 328 { 28800, 0x9, MODE1A }, 329 { 28800, 0x9, MODE1B }, 330 { 38400, 0xc, MODE2A }, 331 { 38400, 0xc, MODE0A }, 332 { 57600, 0x5, MODE2A }, 333 { 57600, 0x5, MODE2B }, 334 { 57600, 0xb, MODE1A }, 335 { 57600, 0xb, MODE1B }, 336 { 115200, 0x6, MODE2A }, 337 { 115200, 0x6, MODE2B }, 338 { 115200, 0xc, MODE1B }, 339 { 230400, 0xc, MODE1A } 340 }; 341 #define TABENTRIES (sizeof(table)/sizeof(table[0])) 342 343 /* 344 * boolean for speed codes which are identical in both A/B BRG groups 345 * in all modes 346 */ 347 static u_char bothgroups[16] = { 348 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1, 1 349 }; 350 351 /* 352 * Manually constructed divisors table 353 * for minimum error (from some of Dave Rand's code) 354 */ 355 const struct { 356 uint16_t speed; 357 uint16_t div; 358 } divs[] = { 359 { 50, 2303 }, /* 2304 is exact?? */ 360 { 110, 1047 }, /* Should be 1047.27 */ 361 { 134, 857 }, /* Should be 856.505576 */ 362 { 1050, 110 }, /* Should be 109.7142857 */ 363 { 2000, 57 } /* Should be 57.6 */ 364 }; 365 #define DIVS (sizeof(divs)/sizeof(divs[0])) 366 367 /* 368 * minor unit bit decode: 369 * CxxxUUU 370 * 371 * C - carrier 372 * 0 - delay open until carrier high 373 * 1 - allow open with carrier low 374 * UUU - unit 0-7 375 */ 376 377 #define DEV_UNIT(x) (minor(x) & 0x7) 378 #define DEV_DIALOUT(x) (minor(x) & 0x80) 379 380 #define SCN_MAXDUART 4 381 static struct duart scn_duart[SCN_MAXDUART]; 382 383 #ifdef KGDB 384 extern int kgdb_dev; 385 extern int kgdb_rate; 386 extern int kgdb_debug_init; 387 #endif 388 389 /* XXXXX - fix this */ 390 #define splrtty() spltty() 391 392 /* RS-232 configuration routines */ 393 394 /* 395 * set chip parameters, or mark for delayed change. 396 * called at spltty() or on TxEMPTY interrupt. 397 * 398 * Reads current values to avoid glitches from redundant sets. 399 * Perhaps should save last value set to avoid read/write? NOTE: 400 * Would still need to do read if write not needed to advance MR 401 * pointer. 402 * 403 * new 2/97 -plb 404 */ 405 406 static void 407 scn_setchip(struct scn_softc *sc) 408 { 409 struct duart *dp; 410 u_char acr, csr, mr1, mr2; 411 int chan; 412 413 if (sc->sc_tty && (sc->sc_tty->t_state & TS_BUSY)) { 414 sc->sc_heldchanges = 1; 415 return; 416 } 417 418 chan = sc->sc_channel; 419 dp = sc->sc_duart; 420 if (dp->type == SC26C92) { 421 u_char nmr0a, mr0a; 422 423 /* input rate high enough so 64 bit time watchdog not 424 * onerous? */ 425 if (dp->chan[chan].ispeed >= 1200) { 426 /* set FIFO threshold at 6 for other 427 * thresholds we could have to set MR1_FFULL 428 */ 429 dp->chan[chan].mr0 |= MR0_RXWD | MR0_RXINT; 430 } else { 431 dp->chan[chan].mr0 &= ~(MR0_RXWD | MR0_RXINT); 432 } 433 434 /* select BRG mode (MR0A only) */ 435 nmr0a = dp->chan[0].mr0 | (dp->mode & MR0_MODE); 436 437 dp->base[CH_CR] = CR_CMD_MR0; 438 RECOVER(); 439 440 mr0a = dp->base[CH_MR]; 441 if (mr0a != nmr0a) { 442 dp->base[CH_CR] = CR_CMD_MR0; 443 RECOVER(); 444 dp->base[CH_MR] = nmr0a; 445 } 446 447 if (chan) { /* channel B? */ 448 u_char mr0b; 449 450 sc->sc_chbase[CH_CR] = CR_CMD_MR0; 451 RECOVER(); 452 mr0b = dp->base[CH_MR]; 453 454 if (dp->chan[chan].mr0 != mr0b) { 455 sc->sc_chbase[CH_CR] = CR_CMD_MR0; 456 RECOVER(); 457 sc->sc_chbase[CH_MR] = dp->chan[chan].mr0; 458 } 459 } 460 } else { 461 sc->sc_chbase[CH_CR] = CR_CMD_MR1; 462 RECOVER(); 463 } 464 465 mr1 = sc->sc_chbase[CH_MR]; 466 mr2 = sc->sc_chbase[CH_MR]; 467 if (mr1 != dp->chan[chan].new_mr1 || 468 mr2 != dp->chan[chan].new_mr2) { 469 sc->sc_chbase[CH_CR] = CR_CMD_MR1; 470 RECOVER(); 471 sc->sc_chbase[CH_MR] = dp->chan[chan].new_mr1; 472 sc->sc_chbase[CH_MR] = dp->chan[chan].new_mr2; 473 } 474 475 acr = dp->acr | (dp->mode & ACR_BRG); 476 dp->base[DU_ACR] = acr; /* write-only reg! */ 477 478 /* set speed codes */ 479 csr = (dp->chan[chan].icode<<4) | dp->chan[chan].ocode; 480 if (sc->sc_chbase[CH_CSR] != csr) { 481 sc->sc_chbase[CH_CSR] = csr; 482 } 483 484 /* see if counter/timer in use */ 485 if (dp->counter && 486 (dp->chan[0].icode == USE_CT || dp->chan[0].ocode == USE_CT || 487 dp->chan[1].icode == USE_CT || dp->chan[1].ocode == USE_CT)) { 488 489 /* program counter/timer only if necessary */ 490 if (dp->counter != dp->ocounter) { 491 uint16_t div; 492 #ifdef DIVS 493 int i; 494 495 /* look for precalculated rate, for minimum error */ 496 for (i = 0; i < DIVS && divs[i].speed <= dp->counter; i++) { 497 if (divs[i].speed == dp->counter) { 498 div = divs[i].div; 499 goto found; 500 } 501 } 502 #endif 503 504 /* not found in table; calculate a value (rounding up) */ 505 div = ((long)SCN_CLOCK/16/2 + dp->counter/2) / dp->counter; 506 507 found: 508 /* halt before loading? may ALWAYS glitch? 509 * reload race may only sometimes glitch?? 510 */ 511 dp->base[DU_CTUR] = div >> 8; 512 dp->base[DU_CTLR] = div & 255; 513 if (dp->ocounter == 0) { 514 /* not previously used? */ 515 u_char temp; 516 /* start C/T running */ 517 temp = dp->base[DU_CSTRT]; 518 __USE(temp); 519 } 520 dp->ocounter = dp->counter; 521 } 522 } else { 523 /* counter not in use; mark as free */ 524 dp->counter = 0; 525 } 526 sc->sc_heldchanges = 0; 527 528 /* 529 * delay a tiny bit to try and avoid tx glitching. 530 * I know we're at spltty(), but this is much better than the 531 * old version used DELAY((96000 / out_speed) * 10000) 532 * -plb 533 */ 534 DELAY(10); 535 } 536 537 /* 538 * iterator function for speeds. 539 * (could be called "findnextcode") 540 * Returns sequence of possible speed codes for a given rate. 541 * should set index to zero before first call. 542 * 543 * Could be implemented as a "checkspeed()" function called 544 * to evaluate table entries, BUT this allows more variety in 545 * use of C/T with fewer table entries. 546 */ 547 548 static int 549 scniter(int *index, int wanted, int *counter, int *mode, struct chan *other, 550 int c92) 551 { 552 553 while (*index < TABENTRIES) { 554 struct tabent *tp; 555 556 tp = table + (*index)++; 557 if (tp->speed != wanted) 558 continue; 559 560 /* if not a 26C92 only look at MODE0 entries */ 561 if (!c92 && (tp->mode & MR0_MODE) != MR0_MODE_0) 562 continue; 563 564 /* 565 * check mode; 566 * OK if this table entry for current mode, or mode not 567 * yet set, or other channel's rates are available in both 568 * A and B groups. 569 */ 570 571 if (tp->mode == *mode || *mode == ANYMODE || 572 (other != NULL && (tp->mode & MR0_MODE) == (*mode & MR0_MODE) && 573 bothgroups[other->icode] && bothgroups[other->ocode])) { 574 /* 575 * for future table entries specifying 576 * use of counter/timer 577 */ 578 if (tp->code == USE_CT) { 579 if (*counter != wanted && *counter != 0) 580 continue; /* counter busy */ 581 *counter = wanted; 582 } 583 *mode = tp->mode; 584 return tp->code; 585 } 586 } 587 588 /* here after returning all applicable table entries */ 589 /* XXX return sequence of USE_CT with all possible modes?? */ 590 if ((*index)++ == TABENTRIES) { 591 /* Max C/T rate (even on 26C92?) is 57600 */ 592 if (wanted <= 57600 && (*counter == wanted || *counter == 0)) { 593 *counter = wanted; 594 return USE_CT; 595 } 596 } 597 598 return -1; /* FAIL */ 599 } 600 601 /* 602 * calculate configuration 603 * rewritten 2/97 -plb 604 */ 605 static int 606 scn_config(int unit, int chan, int ispeed, int ospeed, u_char mr1, u_char mr2) 607 { 608 struct scn_softc *sc; 609 struct duart *dp; 610 int other; /* opposite of chan */ 611 int mode; 612 int counter; 613 int i, o; /* input, output iterator indexes */ 614 int ic, oc; /* input, output codes */ 615 struct chan *ocp; /* other duart channel */ 616 struct tty *otp; /* other channel tty struct */ 617 int c92; /* true if duart is sc26c92 */ 618 int s; 619 620 /* Set up softc pointer. */ 621 if (unit >= scn_cd.cd_ndevs) 622 return ENXIO; 623 sc = SOFTC(unit); 624 chan = sc->sc_channel; 625 other = chan ^ 1; 626 dp = sc->sc_duart; 627 ocp = &dp->chan[other]; 628 otp = ocp->tty; 629 c92 = (dp->type == SC26C92); 630 631 /* 632 * Right now the first combination that works is used. 633 * Perhaps it should search entire solution space for "best" 634 * combination. For example, use heuristic weighting of mode 635 * preferences, and use of counter timer? 636 * 637 * For example right now with 2681/2692 when default rate is 638 * 9600 and other channel is closed setting 19200 will pick 639 * mode 0a and use counter/timer. Better solution might be 640 * mode 0b, leaving counter/timer free! 641 * 642 * When other channel is open might want to prefer 643 * leaving counter timer free, or not flipping A/B group? 644 */ 645 if (otp && (otp->t_state & TS_ISOPEN)) { 646 647 /* 648 * Other channel open; 649 * Find speed codes compatible with current mode/counter. 650 */ 651 652 i = 0; 653 for (;;) { 654 mode = dp->mode; 655 counter = dp->counter; 656 657 /* NOTE: pass other chan pointer to allow group flipping */ 658 ic = scniter(&i, ispeed, &counter, &mode, ocp, c92); 659 if (ic == -1) 660 break; 661 662 o = 0; 663 if ((oc = scniter(&o, ospeed, &counter, 664 &mode, NULL, c92)) != -1) { 665 /* 666 * take first match 667 * 668 * Perhaps calculate heuristic "score", 669 * save score,codes,mode,counter if score 670 * better than previous best? 671 */ 672 goto gotit; 673 } 674 } 675 /* XXX try looping for ospeed? */ 676 } else { 677 /* other channel closed */ 678 int oo, oi; /* other input, output iterators */ 679 int oic, ooc; /* other input, output codes */ 680 681 /* 682 * Here when other channel closed. Finds first 683 * combination that will allow other channel to be opened 684 * (with defaults) and fits our needs. 685 */ 686 oi = 0; 687 for (;;) { 688 mode = ANYMODE; 689 counter = 0; 690 691 oic = scniter(&oi, ocp->ispeed, &counter, &mode, NULL, c92); 692 if (oic == -1) 693 break; 694 695 oo = 0; 696 while ((ooc = scniter(&oo, ocp->ospeed, &counter, 697 &mode, NULL, c92)) != -1) { 698 i = 0; 699 while ((ic = scniter(&i, ispeed, &counter, 700 &mode, NULL, c92)) != -1) { 701 o = 0; 702 if ((oc = scniter(&o, ospeed, &counter, 703 &mode, NULL, c92)) != -1) { 704 /* 705 * take first match 706 * 707 * Perhaps calculate heuristic 708 * "score", save 709 * score,codes,mode,counter 710 * if score better than 711 * previous best? 712 */ 713 s = spltty(); 714 dp->chan[other].icode = oic; 715 dp->chan[other].ocode = ooc; 716 goto gotit2; 717 } 718 } 719 } 720 } 721 } 722 return EINVAL; 723 724 gotit: 725 s = spltty(); 726 gotit2: 727 dp->chan[chan].new_mr1 = mr1; 728 dp->chan[chan].new_mr2 = mr2; 729 dp->chan[chan].ispeed = ispeed; 730 dp->chan[chan].ospeed = ospeed; 731 dp->chan[chan].icode = ic; 732 dp->chan[chan].ocode = oc; 733 if (mode == ANYMODE) /* no mode selected?? */ 734 mode = DEFMODE(c92); 735 dp->mode = mode; 736 dp->counter = counter; 737 738 scn_setchip(sc); /* set chip now, if possible */ 739 splx(s); 740 return (0); 741 } 742 743 int 744 scn_match(device_t parent, struct cfdata *cf, void *aux) 745 { 746 struct mainbus_attach_args *ma = aux; 747 748 if ((mach_type == MACH_SGI_IP6 || mach_type == MACH_SGI_IP10) && 749 ma->ma_addr == 0x1fb80004) 750 return (1); 751 752 return (0); 753 } 754 755 /* 756 * No need to make scn_rx{en,dis}able too efficient, 757 * they're only called on setup, open & close! 758 */ 759 static inline void 760 scn_rxenable(struct scn_softc *sc) 761 { 762 struct duart *dp; 763 int channel; 764 765 dp = sc->sc_duart; 766 channel = sc->sc_channel; 767 768 /* Outputs wire-ored and connected to ICU input for fast rx interrupt. */ 769 if (channel == 0) 770 dp->opcr |= OPCR_OP4_RXRDYA; 771 else 772 dp->opcr |= OPCR_OP5_RXRDYB; 773 dp->base[DU_OPCR] = dp->opcr; 774 dp->imr |= sc->sc_rx_int; 775 dp->base[DU_IMR] = dp->imr; 776 } 777 778 static inline void 779 scn_rxdisable(struct scn_softc *sc) 780 { 781 struct duart *dp; 782 int channel; 783 784 dp = sc->sc_duart; 785 channel = sc->sc_channel; 786 787 /* Outputs wire-ored and connected to ICU input for fast rx interrupt. */ 788 if (channel == 0) 789 dp->opcr &= ~OPCR_OP4_RXRDYA; 790 else 791 dp->opcr &= ~OPCR_OP5_RXRDYB; 792 dp->base[DU_OPCR] = dp->opcr; 793 dp->imr &= ~sc->sc_rx_int; 794 dp->base[DU_IMR] = dp->imr; 795 } 796 797 void 798 scn_attach(device_t parent, device_t self, void *aux) 799 { 800 struct mainbus_attach_args *ma = aux; 801 struct scn_softc *sc; 802 struct duart *duart; 803 volatile u_char *ch_base; 804 volatile u_char *duart_base; 805 int channel; 806 int speed; 807 int s; 808 int maj __diagused; 809 u_char unit; 810 u_char duartno; 811 u_char delim = ':'; 812 u_char mr1, mr2; 813 enum scntype scntype = SCNUNK; 814 const char *duart_type = "Unknown"; 815 bool console, first; 816 devmajor_t major; 817 818 (void)major; 819 820 sc = device_private(self); 821 unit = device_unit(self); 822 823 /* XXX - hard-coded */ 824 if (ma->ma_addr == 0x1fb80004) 825 duartno = 1; 826 else 827 duartno = 0; 828 channel = 0; 829 console = 1; 830 831 duart = sc->sc_duart = &scn_duart[duartno]; 832 duart->chan[channel].sc = sc; 833 first = (duart->base == NULL); 834 835 if (console) { 836 sc->sc_isconsole = 1; 837 sc->sc_swflags |= SCN_SW_SOFTCAR; /* ignore carrier */ 838 } 839 840 duart_base = (volatile u_char *)MIPS_PHYS_TO_KSEG1(ma->ma_addr); 841 ch_base = duart_base; /* XXX */ 842 843 if (first) { 844 /* Probe DUART type */ 845 s = spltty(); 846 if (console) { 847 ch_base[CH_CR] = CR_DIS_TX; 848 delay(5 * 10000); 849 } 850 ch_base[CH_CR] = CR_CMD_MR1; 851 RECOVER(); 852 mr1 = ch_base[CH_MR]; 853 mr2 = ch_base[CH_MR]; 854 ch_base[CH_CR] = CR_CMD_MR1; 855 RECOVER(); 856 ch_base[CH_MR] = 1; 857 ch_base[CH_MR] = 0; 858 ch_base[CH_CR] = CR_CMD_MR1; 859 RECOVER(); 860 if (ch_base[CH_MR] == 1) { 861 /* MR 2 selected */ 862 ch_base[CH_CR] = CR_CMD_MR0; 863 RECOVER(); 864 /* if 2681, MR2 still selected */ 865 ch_base[CH_MR] = 1; 866 ch_base[CH_CR] = CR_CMD_MR1; 867 RECOVER(); 868 ch_base[CH_MR] = 0; /* MR1 */ 869 ch_base[CH_MR] = 0; /* MR2 */ 870 ch_base[CH_CR] = CR_CMD_MR0; 871 RECOVER(); 872 /* if 2681, MR2 still selected */ 873 if((ch_base[CH_MR] & 1) == 1) { 874 duart_type = "sc26c92"; 875 scntype = SC26C92; 876 } else { 877 /* 2681 treats as MR1 Select */ 878 ch_base[CH_CR] = CR_CMD_RTS_OFF; 879 RECOVER(); 880 ch_base[CH_MR] = 1; 881 ch_base[CH_MR] = 0; 882 ch_base[CH_CR] = CR_CMD_RTS_OFF; 883 RECOVER(); 884 if (ch_base[CH_MR] == 1) { 885 duart_type = "scn2681"; 886 scntype = SCN2681; 887 } else { 888 duart_type = "scn2692"; 889 scntype = SCN2692; 890 } 891 } 892 } 893 894 /* If a 2681, the CR_CMD_MR0 is interpreted as a TX_RESET */ 895 if (console) { 896 ch_base[CH_CR] = CR_ENA_TX; 897 RECOVER(); 898 } 899 ch_base[CH_CR] = CR_CMD_MR1; 900 RECOVER(); 901 ch_base[CH_MR] = mr1; 902 ch_base[CH_MR] = mr2; 903 splx(s); 904 905 /* 906 * On IP6 the console chip is duart1. The keyboard/mouse 907 * is duart0. Each chip has two channels and the channels 908 * share an interrupt. Duart0 is interrupt 0, duart1 is 909 * interrupt 1. 910 */ 911 if (duartno != 0 && duartno != 1) 912 panic("scn_attach: bad duartno: %d", duartno); 913 cpu_intr_establish(duartno, IPL_TTY, scnintr, duart); 914 915 printf("%c %s", delim, duart_type); 916 delim = ','; 917 918 duart->base = duart_base; 919 duart->type = scntype; 920 } 921 /* Record channel, uart */ 922 sc->sc_channel = channel; 923 sc->sc_chbase = ch_base; 924 925 /* Initialize modem/interrupt bit masks */ 926 if (channel == 0) { 927 sc->sc_op_rts = OP_RTSA; 928 sc->sc_op_dtr = OP_DTRA; 929 sc->sc_ip_cts = IP_CTSA; 930 sc->sc_ip_dcd = IP_DCDA; 931 932 sc->sc_tx_int = INT_TXA; 933 sc->sc_rx_int = INT_RXA; 934 } else { 935 sc->sc_op_rts = OP_RTSB; 936 sc->sc_op_dtr = OP_DTRB; 937 sc->sc_ip_cts = IP_CTSB; 938 sc->sc_ip_dcd = IP_DCDB; 939 940 sc->sc_tx_int = INT_TXB; 941 sc->sc_rx_int = INT_RXB; 942 } 943 944 /* Initialize counters */ 945 sc->sc_framing_errors = 0; 946 sc->sc_fifo_overruns = 0; 947 sc->sc_parity_errors = 0; 948 sc->sc_breaks = 0; 949 950 if (console) { 951 DELAY(5 * 10000); /* Let the output go out.... */ 952 } 953 954 /* 955 * Set up the hardware to a base state, in particular: 956 * o reset transmitter and receiver 957 * o set speeds and configurations 958 * o receiver interrupts only (RxRDY and BREAK) 959 */ 960 961 s = spltty(); 962 /* RTS off... */ 963 SCN_OP_BIC(sc, sc->sc_op_rts); /* "istop" */ 964 965 ch_base[CH_CR] = CR_DIS_RX | CR_DIS_TX; 966 RECOVER(); 967 ch_base[CH_CR] = CR_CMD_RESET_RX; 968 RECOVER(); 969 ch_base[CH_CR] = CR_CMD_RESET_TX; 970 RECOVER(); 971 ch_base[CH_CR] = CR_CMD_RESET_ERR; 972 RECOVER(); 973 ch_base[CH_CR] = CR_CMD_RESET_BRK; 974 RECOVER(); 975 ch_base[CH_CR] = CR_CMD_MR1; 976 RECOVER(); 977 978 /* No receiver control of RTS. */ 979 ch_base[CH_MR] = 0; 980 ch_base[CH_MR] = 0; 981 982 /* Initialize the uart structure if this is channel A. */ 983 if (first) { 984 /* Disable all interrupts. */ 985 duart_base[DU_IMR] = duart->imr = 0; 986 987 /* Output port config */ 988 duart_base[DU_OPCR] = duart->opcr = 0; 989 990 /* Speeds... */ 991 duart->mode = 0; 992 993 /* 994 * Set initial speed to an illegal code that can be changed to 995 * any other baud. 996 */ 997 duart->chan[0].icode = duart->chan[0].ocode = 0x2f; 998 duart->chan[1].icode = duart->chan[1].ocode = 0x2f; 999 duart->chan[0].ispeed = duart->chan[0].ospeed = 0; 1000 duart->chan[1].ispeed = duart->chan[1].ospeed = 0; 1001 1002 duart->acr = 0; 1003 duart->acr |= ACR_CT_TCLK1; /* timer mode 1x clk */ 1004 } 1005 1006 if (channel == 0) { 1007 duart->acr |= ACR_DELTA_DCDA; /* Set CD int */ 1008 } else { 1009 duart->acr |= ACR_DELTA_DCDB; /* Set CD int */ 1010 } 1011 1012 if (scnsir == NULL) { 1013 /* software intr: calls tty code, hence IPL_TTY */ 1014 scnsir = softint_establish(SOFTINT_SERIAL, scnsoft, NULL); 1015 } 1016 1017 duart_base[DU_ACR] = (duart->mode & ACR_BRG) | duart->acr; 1018 1019 if (console) 1020 speed = scnconsrate; 1021 else 1022 speed = scndefaultrate; 1023 1024 scn_config(unit, channel, speed, speed, MR1_PNONE | MR1_CS8, MR2_STOP1); 1025 if (console) { 1026 maj = cdevsw_lookup_major(&scn_cdevsw); 1027 KASSERT(maj != NODEVMAJOR); 1028 shutdownhook_establish(scncnreinit, NULL); 1029 /* Make sure console can do scncngetc */ 1030 duart_base[DU_OPSET] = channel ? (OP_RTSB | OP_DTRB) : 1031 (OP_RTSA | OP_DTRA); 1032 } 1033 1034 /* Turn on the receiver and transmitters */ 1035 ch_base[CH_CR] = CR_ENA_RX | CR_ENA_TX; 1036 1037 /* Set up the interrupts. */ 1038 duart->imr |= INT_IP; 1039 scn_rxdisable(sc); 1040 splx(s); 1041 1042 if (sc->sc_swflags) { 1043 printf("%c flags %d", delim, sc->sc_swflags); 1044 delim = ','; 1045 } 1046 1047 #ifdef KGDB 1048 major = cdevsw_lookup_major(&scn_cdevsw); 1049 KASSERT(major != NODEVMAJOR); 1050 if (kgdb_dev == makedev(major, unit)) { 1051 if (console) 1052 kgdb_dev = NODEV; /* can't debug over console port */ 1053 else { 1054 scninit(kgdb_dev, kgdb_rate); 1055 scn_rxenable(sc); 1056 scn->sc_iskgdb = 1; 1057 kgdb_attach(scncngetc, scncnputc, kgdb_dev); 1058 if (kgdb_debug_init) { 1059 printf("%c ", delim); 1060 kgdb_connect(1); 1061 } else 1062 printf("%c kgdb enabled", delim); 1063 delim = ','; 1064 } 1065 } 1066 #endif 1067 printf("\n"); 1068 } 1069 1070 /* ARGSUSED */ 1071 int 1072 scnopen(dev_t dev, int flags, int mode, struct lwp *l) 1073 { 1074 struct tty *tp; 1075 int unit = DEV_UNIT(dev); 1076 struct scn_softc *sc; 1077 int error = 0; 1078 1079 if (unit >= scn_cd.cd_ndevs) 1080 return ENXIO; 1081 sc = SOFTC(unit); 1082 if (!sc) 1083 return ENXIO; 1084 1085 tp = sc->sc_tty; 1086 if (!tp) { 1087 tp = tty_alloc(); 1088 sc->sc_tty = sc->sc_duart->chan[sc->sc_channel].tty = tp; 1089 tty_attach(tp); 1090 } 1091 1092 tp->t_oproc = scnstart; 1093 tp->t_param = scnparam; 1094 tp->t_hwiflow = scnhwiflow; 1095 tp->t_dev = dev; 1096 1097 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 1098 return (EBUSY); 1099 1100 ttylock(tp); 1101 1102 if ((tp->t_state & TS_ISOPEN) == 0 && tp->t_wopen == 0) { 1103 ttychars(tp); 1104 tp->t_iflag = TTYDEF_IFLAG; 1105 tp->t_oflag = TTYDEF_OFLAG; 1106 tp->t_cflag = SCNDEF_CFLAG; 1107 1108 sc->sc_rx_blocked = 0; 1109 1110 if (sc->sc_swflags & SCN_SW_CLOCAL) 1111 tp->t_cflag |= CLOCAL; 1112 if (sc->sc_swflags & SCN_SW_CRTSCTS) 1113 tp->t_cflag |= CCTS_OFLOW | CRTS_IFLOW; 1114 tp->t_lflag = TTYDEF_LFLAG; 1115 if (sc->sc_isconsole) 1116 tp->t_ispeed = tp->t_ospeed = scnconsrate; 1117 else 1118 tp->t_ispeed = tp->t_ospeed = scndefaultrate; 1119 scnparam(tp, &tp->t_termios); 1120 ttsetwater(tp); 1121 1122 /* Turn on DTR and RTS. */ 1123 SCN_OP_BIS(sc, sc->sc_op_rts | sc->sc_op_dtr); 1124 1125 /* enable receiver interrupts */ 1126 scn_rxenable(sc); 1127 1128 /* set carrier state; */ 1129 if ((sc->sc_swflags & SCN_SW_SOFTCAR) || /* check ttyflags */ 1130 SCN_DCD(sc) || /* check h/w */ 1131 DEV_DIALOUT(dev)) 1132 tp->t_state |= TS_CARR_ON; 1133 else 1134 tp->t_state &= ~TS_CARR_ON; 1135 } 1136 1137 ttyunlock(tp); 1138 1139 error = ttyopen(tp, SCN_DIALOUT(sc), flags & O_NONBLOCK); 1140 if (error) printf("ttyopen failed line %d, error %d\n", __LINE__, error); 1141 if (error) 1142 goto bad; 1143 1144 error = (*tp->t_linesw->l_open) (dev, tp); 1145 if (error) printf("l_open failed line %d, error %d\n", __LINE__, error); 1146 if (error) 1147 goto bad; 1148 1149 return (0); 1150 1151 bad: 1152 if ((tp->t_state & TS_ISOPEN) == 0 && tp->t_wopen == 0) { 1153 scn_rxdisable(sc); 1154 SCN_OP_BIC(sc, sc->sc_op_rts | sc->sc_op_dtr); 1155 } 1156 1157 return (error); 1158 } 1159 1160 1161 /*ARGSUSED*/ 1162 int 1163 scnclose(dev_t dev, int flags, int mode, struct lwp *l) 1164 { 1165 int unit = DEV_UNIT(dev); 1166 struct scn_softc *sc = SOFTC(unit); 1167 struct tty *tp = sc->sc_tty; 1168 devmajor_t major; 1169 1170 (void)major; 1171 1172 if ((tp->t_state & TS_ISOPEN) == 0) 1173 return 0; 1174 1175 (*tp->t_linesw->l_close) (tp, flags); 1176 1177 #ifdef KGDB 1178 /* do not disable interrupts if debugging */ 1179 major = cdevsw_lookup_major(&scn_devsw); 1180 KASSERT(major != cdevsw_lookup_major); 1181 if (kgdb_dev != makedev(major, unit)) 1182 #endif 1183 if ((tp->t_state & TS_ISOPEN) == 0) { 1184 scn_rxdisable(sc); 1185 } 1186 if ((tp->t_cflag & HUPCL) && (sc->sc_swflags & SCN_SW_SOFTCAR) == 0) { 1187 SCN_OP_BIC(sc, sc->sc_op_dtr); 1188 /* hold low for 1 second */ 1189 tsleep(sc, TTIPRI, ttclos, hz); 1190 } 1191 SCN_CLRDIALOUT(sc); 1192 ttyclose(tp); 1193 1194 #if 0 1195 if ((tp->t_state & TS_ISOPEN) == 0) { 1196 tty_free(tp); 1197 sc->sc_tty = (struct tty *) NULL; 1198 } 1199 #endif 1200 1201 return (0); 1202 } 1203 1204 int 1205 scnread(dev_t dev, struct uio *uio, int flags) 1206 { 1207 struct scn_softc *sc = SOFTC(DEV_UNIT(dev)); 1208 struct tty *tp = sc->sc_tty; 1209 1210 return ((*tp->t_linesw->l_read) (tp, uio, flags)); 1211 } 1212 1213 int 1214 scnwrite(dev_t dev, struct uio *uio, int flags) 1215 { 1216 struct scn_softc *sc = SOFTC(DEV_UNIT(dev)); 1217 struct tty *tp = sc->sc_tty; 1218 1219 return ((*tp->t_linesw->l_write) (tp, uio, flags)); 1220 } 1221 1222 int 1223 scnpoll(dev_t dev, int events, struct lwp *l) 1224 { 1225 struct scn_softc *sc = SOFTC(DEV_UNIT(dev)); 1226 struct tty *tp = sc->sc_tty; 1227 1228 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1229 } 1230 1231 struct tty * 1232 scntty(dev_t dev) 1233 { 1234 struct scn_softc *sc = SOFTC(DEV_UNIT(dev)); 1235 1236 return sc->sc_tty; 1237 } 1238 1239 /* Worker routines for interrupt processing */ 1240 static inline void 1241 dcd_int(struct scn_softc *sc, struct tty *tp, u_char new) 1242 { 1243 1244 if (sc->sc_swflags & SCN_SW_SOFTCAR) 1245 return; 1246 1247 #if 0 1248 printf("scn%d: dcd_int ip %x SCN_DCD %x new %x ipcr %x\n", 1249 sc->unit, 1250 sc->sc_duart->base[DU_IP], 1251 SCN_DCD(sc), 1252 new, 1253 sc->sc_duart->base[DU_IPCR] 1254 ); 1255 #endif 1256 1257 /* XXX set some flag to have some lower (soft) int call line discipline? */ 1258 if (!(*tp->t_linesw->l_modem) (tp, new == 0? 1: 0)) { 1259 SCN_OP_BIC(sc, sc->sc_op_rts | sc->sc_op_dtr); 1260 } 1261 } 1262 1263 /* 1264 * Print out a ring or fifo overrun error message. 1265 */ 1266 static void 1267 scnoverrun(int unit, long *ptime, const char *what) 1268 { 1269 1270 if (*ptime != time_second) { 1271 *ptime = time_second; 1272 log(LOG_WARNING, "scn%d: %s overrun\n", unit, what); 1273 } 1274 } 1275 1276 /* 1277 * Try to block or unblock input using hardware flow-control. 1278 * This is called by kern/tty.c if MDMBUF|CRTSCTS is set, and 1279 * if this function returns non-zero, the TS_TBLOCK flag will 1280 * be set or cleared according to the "stop" arg passed. 1281 */ 1282 int 1283 scnhwiflow(struct tty *tp, int stop) 1284 { 1285 int unit = DEV_UNIT(tp->t_dev); 1286 struct scn_softc *sc = SOFTC(unit); 1287 int s; 1288 1289 s = splrtty(); 1290 if (!stop) { 1291 if (sc->sc_rbput - sc->sc_rbget - 1) { 1292 setsoftscn(); 1293 } 1294 } 1295 splx(s); 1296 return 1; 1297 } 1298 1299 static int 1300 scnintr(void *arg) 1301 { 1302 struct duart *duart = arg; 1303 struct scn_softc *sc0 = duart->chan[0].sc; 1304 struct scn_softc *sc1 = duart->chan[1].sc; 1305 1306 struct tty *tp0 = (sc0 != NULL) ? sc0->sc_tty : NULL; 1307 struct tty *tp1 = (sc1 != NULL) ? sc1->sc_tty : NULL; 1308 1309 char rs_work; 1310 u_char rs_stat; 1311 u_char rs_ipcr; 1312 1313 /* Check for RX interrupts first, since we cannot distinguish by irq. */ 1314 scnrxintr(duart); 1315 1316 do { 1317 /* Loop to pick up ALL pending interrupts for device. */ 1318 rs_work = false; 1319 rs_stat = duart->base[DU_ISR]; 1320 1321 /* channel a */ 1322 if (tp0 != NULL) { 1323 if ((rs_stat & INT_TXA) && (tp0->t_state & TS_BUSY)) { 1324 /* output char done. */ 1325 tp0->t_state &= ~(TS_BUSY | TS_FLUSH); 1326 1327 /* disable tx ints */ 1328 duart->imr &= ~sc0->sc_tx_int; 1329 duart->base[DU_IMR] = duart->imr; 1330 1331 if (sc0->sc_heldchanges) { 1332 scn_setchip(sc0); 1333 } 1334 1335 (*tp0->t_linesw->l_start) (tp0); 1336 rs_work = true; 1337 } 1338 } 1339 /* channel b */ 1340 if (tp1 != NULL) { 1341 if ((rs_stat & INT_TXB) && (tp1->t_state & TS_BUSY)) { 1342 /* output char done. */ 1343 tp1->t_state &= ~(TS_BUSY | TS_FLUSH); 1344 1345 /* disable tx ints */ 1346 duart->imr &= ~sc1->sc_tx_int; 1347 duart->base[DU_IMR] = duart->imr; 1348 1349 if (sc1->sc_heldchanges) { 1350 scn_setchip(sc1); 1351 } 1352 1353 (*tp1->t_linesw->l_start) (tp1); 1354 rs_work = true; 1355 } 1356 } 1357 if (rs_stat & INT_IP) { 1358 rs_work = true; 1359 rs_ipcr = duart->base[DU_IPCR]; 1360 1361 if (rs_ipcr & IPCR_DELTA_DCDA && tp0 != NULL) { 1362 dcd_int(sc0, tp0, rs_ipcr & IPCR_DCDA); 1363 } 1364 if (rs_ipcr & IPCR_DELTA_DCDB && tp1 != NULL) { 1365 dcd_int(sc1, tp1, rs_ipcr & IPCR_DCDB); 1366 } 1367 } 1368 } while (rs_work); 1369 1370 return (1); /* ? */ 1371 } 1372 1373 /* 1374 * Handle rxrdy/ffull interrupt: QUICKLY poll both channels (checking 1375 * status first) and stash data in a ring buffer. Ring buffer scheme 1376 * borowed from sparc/zs.c requires NO interlock on data! 1377 * 1378 * This interrupt should NOT be included in spltty() mask since it 1379 * invokes NO tty code! The whole point is to allow tty input as much 1380 * of the time as possible, while deferring "heavy" character 1381 * processing until later. 1382 * 1383 * see scn.hw.README and scnsoft() for more info. 1384 * 1385 * THIS ROUTINE SHOULD BE KEPT AS CLEAN AS POSSIBLE!! 1386 * IT'S A CANDIDATE FOR RECODING IN ASSEMBLER!! 1387 */ 1388 static inline int 1389 scn_rxintr(struct scn_softc *sc) 1390 { 1391 char sr; 1392 int i, n; 1393 int work; 1394 1395 work = 0; 1396 i = sc->sc_rbput; 1397 while (work <= 10) { 1398 #define SCN_GETCH(SC) \ 1399 sr = (SC)->sc_chbase[CH_SR]; \ 1400 if ((sr & SR_RX_RDY) == 0) \ 1401 break; \ 1402 if (sr & (SR_PARITY | SR_FRAME | SR_BREAK | SR_OVERRUN)) \ 1403 goto exception; \ 1404 work++; \ 1405 (SC)->sc_rbuf[i++ & SCN_RING_MASK] = (SC)->sc_chbase[CH_DAT] 1406 1407 SCN_GETCH(sc); SCN_GETCH(sc); SCN_GETCH(sc); 1408 /* XXX more here if 26C92? -plb */ 1409 continue; 1410 exception: 1411 #if defined(DDB) 1412 if (sc->sc_isconsole && (sr & SR_BREAK)) { 1413 Debugger(); 1414 sr = sc->sc_chbase[CH_SR]; 1415 } 1416 #endif 1417 #if defined(KGDB) 1418 if (sc->sc_iskgdb && (sr & SR_RX_RDY)) { 1419 kgdb_connect(1); 1420 sr = sc->sc_chbase[CH_SR]; 1421 } 1422 #endif 1423 work++; 1424 sc->sc_rbuf[i++ & SCN_RING_MASK] = (sr << 8) | sc->sc_chbase[CH_DAT]; 1425 sc->sc_chbase[CH_CR] = CR_CMD_RESET_ERR; /* resets break? */ 1426 RECOVER(); 1427 } 1428 /* 1429 * If ring is getting too full, try to block input. 1430 */ 1431 n = i - sc->sc_rbget; 1432 if (sc->sc_rbhiwat && (n > sc->sc_rbhiwat)) { 1433 /* If not CRTSCTS sc_rbhiwat is such that this 1434 * never happens. 1435 * Clear RTS 1436 */ 1437 SCN_OP_BIC(sc, sc->sc_op_rts); 1438 sc->sc_rx_blocked = 1; 1439 } 1440 sc->sc_rbput = i; 1441 1442 return work; 1443 } 1444 1445 static void 1446 scnrxintr(void *arg) 1447 { 1448 struct duart *duart = arg; 1449 int work = 0; 1450 1451 if (duart->chan[0].sc != NULL) 1452 work += scn_rxintr(duart->chan[0].sc); 1453 if (duart->chan[1].sc != NULL) 1454 work += scn_rxintr(duart->chan[1].sc); 1455 if (work > 0) { 1456 setsoftscn(); /* trigger s/w intr */ 1457 #ifdef SCN_TIMING 1458 microtime(&tstart); 1459 #endif 1460 } 1461 } 1462 1463 /* 1464 * Here on soft interrupt (at spltty) to empty ring buffers. 1465 * 1466 * Dave's original scheme was to use the DUART receiver timeout 1467 * interrupt. This requires 2692's (which my board doesn't have), and 1468 * I also liked the idea of using the C/T to generate alternate and/or 1469 * arbitrary bauds. -plb 1470 * 1471 * The ringbuffer code comes from Chris Torek's SPARC 44bsd zs driver 1472 * (hence the LBL notice on top of this file), DOES NOT require 1473 * interlocking with interrupt levels! 1474 * 1475 * The 44bsd sparc/zs driver reads the ring buffer from a separate 1476 * zssoftint, while the SunOS 4.x zs driver appears to use 1477 * timeout()'s. timeouts seem to be too slow to deal with high data 1478 * rates. I know, I tried them. 1479 * -plb. 1480 */ 1481 static void 1482 scnsoft(void *arg) 1483 { 1484 int s, unit; 1485 #ifdef SCN_TIMING 1486 struct timeval tend; 1487 u_long t; 1488 1489 microtime(&tend); 1490 t = (tend.tv_sec - tstart.tv_sec) * 1000000 + (tend.tv_usec - tstart.tv_usec); 1491 t = (t + tick / 20) / (tick / 10); 1492 if (t >= NJITTER - 1) { 1493 t = NJITTER - 1; 1494 } 1495 scn_jitter[t]++; 1496 #endif 1497 1498 for (unit = 0; unit < scn_cd.cd_ndevs; unit++) { 1499 struct scn_softc *sc; 1500 struct tty *tp; 1501 int n, get; 1502 1503 sc = SOFTC(unit); 1504 if (sc == NULL) { 1505 continue; 1506 } 1507 tp = sc->sc_tty; 1508 #ifdef KGDB 1509 if (tp == NULL) { 1510 sc->sc_rbget = sc->sc_rbput; 1511 continue; 1512 } 1513 #endif 1514 if (tp == NULL || tp->t_state & TS_TBLOCK) { 1515 continue; 1516 } 1517 1518 1519 get = sc->sc_rbget; 1520 1521 /* NOTE: fetch from rbput is atomic */ 1522 while (get != (n = sc->sc_rbput)) { 1523 /* 1524 * Compute the number of interrupts in the receive ring. 1525 * If the count is overlarge, we lost some events, and 1526 * must advance to the first valid one. It may get 1527 * overwritten if more data are arriving, but this is 1528 * too expensive to check and gains nothing (we already 1529 * lost out; all we can do at this point is trade one 1530 * kind of loss for another). 1531 */ 1532 n -= get; 1533 if (n > SCN_RING_SIZE) { 1534 scnoverrun(unit, &sc->sc_rotime, "ring"); 1535 get += n - SCN_RING_SIZE; 1536 n = SCN_RING_SIZE; 1537 sc->sc_ring_overruns++; 1538 } 1539 while (--n >= 0) { 1540 int c, sr; 1541 1542 if (tp->t_state & TS_TBLOCK) { 1543 sc->sc_rbget = get; 1544 goto done; 1545 } 1546 /* Race to keep ahead of incoming interrupts. */ 1547 c = sc->sc_rbuf[get++ & SCN_RING_MASK]; 1548 1549 sr = c >> 8; /* extract status */ 1550 c &= 0xff; /* leave just character */ 1551 1552 if (sr & SR_OVERRUN) { 1553 scnoverrun(unit, &sc->sc_fotime, "fifo"); 1554 sc->sc_fifo_overruns++; 1555 } 1556 if (sr & SR_PARITY) { 1557 c |= TTY_PE; 1558 sc->sc_parity_errors++; 1559 } 1560 if (sr & SR_FRAME) { 1561 c |= TTY_FE; 1562 sc->sc_framing_errors++; 1563 } 1564 if (sr & SR_BREAK) { 1565 #if 0 1566 /* 1567 * See DDB_CHECK() comments in 1568 * scnrxintr() 1569 */ 1570 if (sc->sc_isconsole) 1571 Debugger(); 1572 #endif 1573 c = TTY_FE | 0; 1574 sc->sc_breaks++; 1575 } 1576 1577 (*tp->t_linesw->l_rint) (c, tp); 1578 1579 if (sc->sc_rx_blocked && n < SCN_RING_THRESH) { 1580 s = splrtty(); 1581 sc->sc_rx_blocked = 0; 1582 SCN_OP_BIS(sc, sc->sc_op_rts); 1583 splx(s); 1584 } 1585 1586 } 1587 sc->sc_rbget = get; 1588 } 1589 done: ; 1590 } 1591 } 1592 1593 /* Convert TIOCM_xxx bits to output port bits. */ 1594 static unsigned char 1595 opbits(struct scn_softc *sc, int tioc_bits) 1596 { 1597 1598 return ((((tioc_bits) & TIOCM_DTR) ? sc->sc_op_dtr : 0) | 1599 (((tioc_bits) & TIOCM_RTS) ? sc->sc_op_rts : 0)); 1600 } 1601 1602 int 1603 scnioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1604 { 1605 int unit = DEV_UNIT(dev); 1606 struct scn_softc *sc = SOFTC(unit); 1607 struct tty *tp = sc->sc_tty; 1608 int error; 1609 1610 error = (*tp->t_linesw->l_ioctl) (tp, cmd, data, flags, l); 1611 if (error != EPASSTHROUGH) 1612 return (error); 1613 1614 error = ttioctl(tp, cmd, data, flags, l); 1615 if (error != EPASSTHROUGH) 1616 return (error); 1617 1618 switch (cmd) { 1619 case TIOCSBRK: 1620 sc->sc_chbase[CH_CR] = CR_CMD_START_BRK; 1621 break; 1622 1623 case TIOCCBRK: 1624 sc->sc_chbase[CH_CR] = CR_CMD_STOP_BRK; 1625 break; 1626 1627 case TIOCSDTR: 1628 SCN_OP_BIS(sc, sc->sc_op_dtr | sc->sc_op_rts); 1629 break; 1630 1631 case TIOCCDTR: 1632 SCN_OP_BIC(sc, sc->sc_op_dtr | sc->sc_op_rts); 1633 break; 1634 1635 case TIOCMSET: { 1636 int s; 1637 unsigned char sbits, cbits; 1638 1639 /* set bits */ 1640 sbits = opbits(sc, *(int *) data); 1641 1642 /* get bits to clear */ 1643 cbits = ~sbits & (sc->sc_op_dtr | sc->sc_op_rts); 1644 1645 s = spltty(); 1646 if (sbits) { 1647 SCN_OP_BIS(sc, sbits); 1648 } 1649 if (cbits) { 1650 SCN_OP_BIC(sc, cbits); 1651 } 1652 splx(s); 1653 break; 1654 } 1655 1656 case TIOCMBIS: 1657 SCN_OP_BIS(sc, opbits(sc, *(int *) data)); 1658 break; 1659 1660 case TIOCMBIC: 1661 SCN_OP_BIC(sc, opbits(sc, *(int *) data)); 1662 break; 1663 1664 case TIOCMGET: { 1665 int bits; 1666 unsigned char ip; 1667 1668 /* s = spltty(); */ 1669 ip = sc->sc_duart->base[DU_IP]; 1670 /* splx(s); */ 1671 1672 bits = 0; 1673 if (ip & sc->sc_ip_dcd) 1674 bits |= TIOCM_CD; 1675 if (ip & sc->sc_ip_cts) 1676 bits |= TIOCM_CTS; 1677 1678 #if 0 1679 /* 1680 * XXX sigh; cannot get op current state!! even if 1681 * maintained in private, RTS is done in h/w!! 1682 */ 1683 unsigned char op = 0; 1684 if (op & sc->sc_op_dtr) 1685 bits |= TIOCM_DTR; 1686 if (op & sc->sc_op_rts) 1687 bits |= TIOCM_RTS; 1688 #endif 1689 1690 *(int *) data = bits; 1691 break; 1692 } 1693 1694 case TIOCGFLAGS:{ 1695 int bits = 0; 1696 1697 if (sc->sc_swflags & SCN_SW_SOFTCAR) 1698 bits |= TIOCFLAG_SOFTCAR; 1699 if (sc->sc_swflags & SCN_SW_CLOCAL) 1700 bits |= TIOCFLAG_CLOCAL; 1701 if (sc->sc_swflags & SCN_SW_CRTSCTS) 1702 bits |= TIOCFLAG_CRTSCTS; 1703 if (sc->sc_swflags & SCN_SW_MDMBUF) 1704 bits |= TIOCFLAG_MDMBUF; 1705 1706 *(int *) data = bits; 1707 break; 1708 } 1709 case TIOCSFLAGS:{ 1710 int userbits, driverbits = 0; 1711 1712 error = kauth_authorize_device_tty(l->l_cred, 1713 KAUTH_DEVICE_TTY_PRIVSET, tp); 1714 if (error != 0) 1715 return (EPERM); 1716 1717 userbits = *(int *) data; 1718 if (userbits & TIOCFLAG_SOFTCAR) 1719 driverbits |= SCN_SW_SOFTCAR; 1720 if (userbits & TIOCFLAG_CLOCAL) 1721 driverbits |= SCN_SW_CLOCAL; 1722 if (userbits & TIOCFLAG_CRTSCTS) 1723 driverbits |= SCN_SW_CRTSCTS; 1724 if (userbits & TIOCFLAG_MDMBUF) 1725 driverbits |= SCN_SW_MDMBUF; 1726 1727 sc->sc_swflags = driverbits; 1728 1729 break; 1730 } 1731 1732 default: 1733 return (EPASSTHROUGH); 1734 } 1735 return (0); 1736 } 1737 1738 int 1739 scnparam(struct tty *tp, struct termios *t) 1740 { 1741 int cflag = t->c_cflag; 1742 int unit = DEV_UNIT(tp->t_dev); 1743 char mr1, mr2; 1744 int error; 1745 struct scn_softc *sc = SOFTC(unit); 1746 1747 /* Is this a hang up? */ 1748 if (t->c_ospeed == B0) { 1749 SCN_OP_BIC(sc, sc->sc_op_dtr); 1750 /* leave DTR down. see comment in scnclose() -plb */ 1751 return (0); 1752 } 1753 mr1 = mr2 = 0; 1754 1755 /* Parity? */ 1756 if (cflag & PARENB) { 1757 if ((cflag & PARODD) == 0) 1758 mr1 |= MR1_PEVEN; 1759 else 1760 mr1 |= MR1_PODD; 1761 } else 1762 mr1 |= MR1_PNONE; 1763 1764 /* Stop bits. */ 1765 if (cflag & CSTOPB) 1766 mr2 |= MR2_STOP2; 1767 else 1768 mr2 |= MR2_STOP1; 1769 1770 /* Data bits. */ 1771 switch (cflag & CSIZE) { 1772 case CS5: 1773 mr1 |= MR1_CS5; 1774 break; 1775 case CS6: 1776 mr1 |= MR1_CS6; 1777 break; 1778 case CS7: 1779 mr1 |= MR1_CS7; 1780 break; 1781 case CS8: 1782 default: 1783 mr1 |= MR1_CS8; 1784 break; 1785 } 1786 1787 if (cflag & CCTS_OFLOW) 1788 mr2 |= MR2_TXCTS; 1789 1790 if (cflag & CRTS_IFLOW) { 1791 mr1 |= MR1_RXRTS; 1792 sc->sc_rbhiwat = SCN_RING_HIWAT; 1793 } else { 1794 sc->sc_rbhiwat = 0; 1795 } 1796 1797 error = scn_config(unit, sc->sc_channel, t->c_ispeed, 1798 t->c_ospeed, mr1, mr2); 1799 1800 /* If successful, copy to tty */ 1801 if (!error) { 1802 tp->t_ispeed = t->c_ispeed; 1803 tp->t_ospeed = t->c_ospeed; 1804 tp->t_cflag = cflag; 1805 } 1806 return (error); 1807 } 1808 1809 /* 1810 * Start or restart a transmission. 1811 */ 1812 void 1813 scnstart(struct tty *tp) 1814 { 1815 int s, c; 1816 int unit = DEV_UNIT(tp->t_dev); 1817 struct scn_softc *sc = SOFTC(unit); 1818 1819 s = spltty(); 1820 if (tp->t_state & (TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1821 goto out; 1822 if (!ttypull(tp)) 1823 goto out; 1824 1825 tp->t_state |= TS_BUSY; 1826 1827 while (sc->sc_chbase[CH_SR] & SR_TX_RDY) { 1828 if ((c = getc(&tp->t_outq)) == -1) 1829 break; 1830 sc->sc_chbase[CH_DAT] = c; 1831 } 1832 sc->sc_duart->imr |= (sc->sc_tx_int | sc->sc_rx_int); 1833 sc->sc_duart->base[DU_IMR] = sc->sc_duart->imr; 1834 1835 out: 1836 splx(s); 1837 } 1838 1839 /* 1840 * Stop output on a line. 1841 */ 1842 /*ARGSUSED*/ 1843 void 1844 scnstop(struct tty *tp, int flags) 1845 { 1846 int s; 1847 1848 s = spltty(); 1849 if (tp->t_state & TS_BUSY) { 1850 if ((tp->t_state & TS_TTSTOP) == 0) 1851 tp->t_state |= TS_FLUSH; 1852 } 1853 splx(s); 1854 } 1855 1856 /* 1857 * Following are all routines needed for SCN to act as console. 1858 */ 1859 1860 void 1861 scncnprobe(struct consdev *cn) 1862 { 1863 } 1864 1865 void 1866 scncnreinit(void *v) 1867 { 1868 volatile u_char *du_base = 1869 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1870 1871 du_base[DU_OPSET] = 1872 SCN_CONSCHAN ? (OP_RTSB | OP_DTRB) : (OP_RTSA | OP_DTRA); 1873 } 1874 1875 void 1876 scncninit(struct consdev *cn) 1877 { 1878 devmajor_t major; 1879 1880 /* initialize required fields */ 1881 major = cdevsw_lookup_major(&scn_cdevsw); 1882 KASSERT(major != NODEV); 1883 cn->cn_dev = makedev(major, SCN_CONSOLE); 1884 cn->cn_pri = CN_REMOTE; 1885 1886 scninit(cn->cn_dev, scnconsrate); 1887 } 1888 1889 /* Used by scncninit and kgdb startup. */ 1890 int 1891 scninit(dev_t dev, int rate) 1892 { 1893 /* XXX - maintain PROM's settings */ 1894 #if 0 1895 volatile u_char *du_base = 1896 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1897 int unit = DEV_UNIT(dev); 1898 1899 du_base[DU_OPSET] = 1900 SCN_CONSCHAN ? (OP_RTSB | OP_DTRB) : (OP_RTSA | OP_DTRA); 1901 scn_config(unit, SCN_CONSCHAN, rate, rate, 1902 MR1_PNONE | MR1_CS8, MR2_STOP1); 1903 #endif 1904 return (0); 1905 } 1906 1907 /* 1908 * Console kernel input character routine. 1909 */ 1910 int 1911 scncngetc(dev_t dev) 1912 { 1913 volatile u_char *ch_base = 1914 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1915 char c; 1916 int s; 1917 1918 s = spltty(); 1919 1920 while ((ch_base[CH_SR] & SR_RX_RDY) == 0) 1921 ; 1922 c = ch_base[CH_DAT]; 1923 1924 splx(s); 1925 return c; 1926 } 1927 1928 void 1929 scncnpollc(dev_t dev, int on) 1930 { 1931 } 1932 1933 /* 1934 * Console kernel output character routine. 1935 */ 1936 void 1937 scncnputc(dev_t dev, int c) 1938 { 1939 volatile u_char *ch_base = 1940 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1941 volatile u_char *du_base = 1942 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1943 int s; 1944 1945 s = spltty(); 1946 1947 if (c == '\n') 1948 scncnputc(dev, '\r'); 1949 1950 while ((ch_base[CH_SR] & SR_TX_RDY) == 0) 1951 ; 1952 ch_base[CH_DAT] = c; 1953 while ((ch_base[CH_SR] & SR_TX_RDY) == 0) 1954 ; 1955 du_base[DU_ISR]; 1956 1957 splx(s); 1958 } 1959
Indexes created Mon Sep 22 10:09:38 GMT 2025