1 /* $NetBSD: ata_wdc.c,v 1.120 2021/10/05 08:01:05 rin Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ata_wdc.c,v 1.120 2021/10/05 08:01:05 rin Exp $"); 58 59 #include "opt_ata.h" 60 #include "opt_wdc.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/file.h> 66 #include <sys/stat.h> 67 #include <sys/buf.h> 68 #include <sys/bufq.h> 69 #include <sys/device.h> 70 #include <sys/disklabel.h> 71 #include <sys/syslog.h> 72 #include <sys/proc.h> 73 74 #include <sys/intr.h> 75 #include <sys/bus.h> 76 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 77 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 78 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 79 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 80 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 81 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 82 83 #include <dev/ata/ataconf.h> 84 #include <dev/ata/atareg.h> 85 #include <dev/ata/atavar.h> 86 #include <dev/ic/wdcreg.h> 87 #include <dev/ic/wdcvar.h> 88 89 #define DEBUG_INTR 0x01 90 #define DEBUG_XFERS 0x02 91 #define DEBUG_STATUS 0x04 92 #define DEBUG_FUNCS 0x08 93 #define DEBUG_PROBE 0x10 94 #ifdef ATADEBUG 95 extern int wdcdebug_wd_mask; /* inited in wd.c */ 96 #define ATADEBUG_PRINT(args, level) \ 97 if (wdcdebug_wd_mask & (level)) \ 98 printf args 99 #else 100 #define ATADEBUG_PRINT(args, level) 101 #endif 102 103 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 104 105 static void wdc_ata_bio(struct ata_drive_datas*, struct ata_xfer *); 106 static int wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 107 static int _wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 108 static int wdc_ata_bio_poll(struct ata_channel *,struct ata_xfer *); 109 static int wdc_ata_bio_intr(struct ata_channel *, struct ata_xfer *, 110 int); 111 static void wdc_ata_bio_kill_xfer(struct ata_channel *, 112 struct ata_xfer *, int); 113 static void wdc_ata_bio_done(struct ata_channel *, struct ata_xfer *); 114 static int wdc_ata_err(struct ata_drive_datas *, struct ata_bio *, int); 115 #define WDC_ATA_NOERR 0x00 /* Drive doesn't report an error */ 116 #define WDC_ATA_RECOV 0x01 /* There was a recovered error */ 117 #define WDC_ATA_ERR 0x02 /* Drive reports an error */ 118 static int wdc_ata_addref(struct ata_drive_datas *); 119 static void wdc_ata_delref(struct ata_drive_datas *); 120 121 const struct ata_bustype wdc_ata_bustype = { 122 .bustype_type = SCSIPI_BUSTYPE_ATA, 123 .ata_bio = wdc_ata_bio, 124 .ata_reset_drive = wdc_reset_drive, 125 .ata_reset_channel = wdc_reset_channel, 126 .ata_exec_command = wdc_exec_command, 127 .ata_get_params = ata_get_params, 128 .ata_addref = wdc_ata_addref, 129 .ata_delref = wdc_ata_delref, 130 .ata_killpending = ata_kill_pending, 131 .ata_recovery = NULL, 132 }; 133 134 static const struct ata_xfer_ops wdc_bio_xfer_ops = { 135 .c_start = wdc_ata_bio_start, 136 .c_poll = wdc_ata_bio_poll, 137 .c_abort = wdc_ata_bio_done, 138 .c_intr = wdc_ata_bio_intr, 139 .c_kill_xfer = wdc_ata_bio_kill_xfer 140 }; 141 142 /* 143 * Handle block I/O operation. 144 */ 145 static void 146 wdc_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 147 { 148 struct ata_channel *chp = drvp->chnl_softc; 149 struct atac_softc *atac = chp->ch_atac; 150 struct ata_bio *ata_bio = &xfer->c_bio; 151 152 if (atac->atac_cap & ATAC_CAP_NOIRQ) 153 ata_bio->flags |= ATA_POLL; 154 if (ata_bio->flags & ATA_POLL) 155 xfer->c_flags |= C_POLL; 156 #if NATA_DMA 157 if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) && 158 (ata_bio->flags & ATA_SINGLE) == 0) 159 xfer->c_flags |= C_DMA; 160 #endif 161 #if NATA_DMA && NATA_PIOBM 162 else 163 #endif 164 #if NATA_PIOBM 165 if (atac->atac_cap & ATAC_CAP_PIOBM) 166 xfer->c_flags |= C_PIOBM; 167 #endif 168 xfer->c_drive = drvp->drive; 169 xfer->c_databuf = ata_bio->databuf; 170 xfer->c_bcount = ata_bio->bcount; 171 xfer->ops = &wdc_bio_xfer_ops; 172 ata_exec_xfer(chp, xfer); 173 } 174 175 static int 176 wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 177 { 178 struct atac_softc *atac = chp->ch_atac; 179 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 180 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 181 struct ata_bio *ata_bio = &xfer->c_bio; 182 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 183 int wait_flags, tfd; 184 const char *errstring; 185 #ifdef WDC_NO_IDS 186 wait_flags = AT_POLL; 187 #else 188 wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 189 #endif 190 191 ATADEBUG_PRINT(("wdc_ata_bio_start %s:%d:%d state %d drive_flags 0x%x " 192 "c_flags 0x%x ch_flags 0x%x\n", 193 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 194 drvp->state, drvp->drive_flags, xfer->c_flags, chp->ch_flags), 195 DEBUG_XFERS); 196 197 ata_channel_lock_owned(chp); 198 199 /* Do control operations specially. */ 200 if (__predict_false(drvp->state < READY)) { 201 /* 202 * Actually, we want to be careful not to mess with the control 203 * state if the device is currently busy, but we can assume 204 * that we never get to this point if that's the case. 205 */ 206 /* If it's not a polled command, we need the kernel thread */ 207 if ((xfer->c_flags & C_POLL) == 0 && !ata_is_thread_run(chp)) 208 return ATASTART_TH; 209 210 /* 211 * disable interrupts, all commands here should be quick 212 * enough to be able to poll, and we don't go here that often 213 */ 214 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 215 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 216 wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); 217 if (wdc->select) 218 wdc->select(chp, xfer->c_drive); 219 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 220 WDSD_IBM | (xfer->c_drive << 4)); 221 DELAY(10); 222 errstring = "wait"; 223 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 224 &tfd)) 225 goto ctrltimeout; 226 wdccommandshort(chp, xfer->c_drive, WDCC_RECAL); 227 /* Wait for at last 400ns for status bit to be valid */ 228 DELAY(1); 229 errstring = "recal"; 230 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 231 &tfd)) 232 goto ctrltimeout; 233 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 234 goto ctrlerror; 235 /* Don't try to set modes if controller can't be adjusted */ 236 if (atac->atac_set_modes == NULL) 237 goto geometry; 238 /* Also don't try if the drive didn't report its mode */ 239 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 240 goto geometry; 241 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 242 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 243 errstring = "piomode"; 244 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 245 &tfd)) 246 goto ctrltimeout; 247 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 248 goto ctrlerror; 249 #if NATA_DMA 250 #if NATA_UDMA 251 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 252 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 253 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 254 } else 255 #endif 256 if (drvp->drive_flags & ATA_DRIVE_DMA) { 257 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 258 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 259 } else { 260 goto geometry; 261 } 262 errstring = "dmamode"; 263 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 264 &tfd)) 265 goto ctrltimeout; 266 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 267 goto ctrlerror; 268 #endif /* NATA_DMA */ 269 geometry: 270 if (ata_bio->flags & ATA_LBA) 271 goto multimode; 272 wdccommand(chp, xfer->c_drive, WDCC_IDP, 273 drvp->lp->d_ncylinders, 274 drvp->lp->d_ntracks - 1, 0, drvp->lp->d_nsectors, 275 (drvp->lp->d_type == DKTYPE_ST506) ? 276 drvp->lp->d_precompcyl / 4 : 0); 277 errstring = "geometry"; 278 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 279 &tfd)) 280 goto ctrltimeout; 281 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 282 goto ctrlerror; 283 multimode: 284 if (drvp->multi == 1) 285 goto ready; 286 wdccommand(chp, xfer->c_drive, WDCC_SETMULTI, 0, 0, 0, 287 drvp->multi, 0); 288 errstring = "setmulti"; 289 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 290 &tfd)) 291 goto ctrltimeout; 292 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 293 goto ctrlerror; 294 ready: 295 drvp->state = READY; 296 /* 297 * The drive is usable now 298 */ 299 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 300 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 301 wd_aux_ctlr, WDCTL_4BIT); 302 delay(10); /* some drives need a little delay here */ 303 } 304 305 return _wdc_ata_bio_start(chp, xfer); 306 ctrltimeout: 307 printf("%s:%d:%d: %s timed out\n", 308 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 309 errstring); 310 ata_bio->error = TIMEOUT; 311 goto ctrldone; 312 ctrlerror: 313 printf("%s:%d:%d: %s ", 314 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 315 errstring); 316 if (ATACH_ST(tfd) & WDCS_DWF) { 317 printf("drive fault\n"); 318 ata_bio->error = ERR_DF; 319 } else { 320 ata_bio->r_error = ATACH_ERR(tfd); 321 ata_bio->error = ERROR; 322 printf("error (%x)\n", ata_bio->r_error); 323 } 324 ctrldone: 325 drvp->state = 0; 326 327 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 328 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 329 WDCTL_4BIT); 330 return ATASTART_ABORT; 331 } 332 333 static int 334 _wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 335 { 336 struct atac_softc *atac = chp->ch_atac; 337 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 338 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 339 struct ata_bio *ata_bio = &xfer->c_bio; 340 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 341 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 342 uint16_t cyl; 343 uint8_t head, sect, cmd = 0; 344 int nblks, tfd; 345 #if NATA_DMA || NATA_PIOBM 346 int error, dma_flags = 0; 347 #endif 348 349 ATADEBUG_PRINT(("_wdc_ata_bio_start %s:%d:%d\n", 350 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 351 DEBUG_INTR | DEBUG_XFERS); 352 353 #if NATA_DMA || NATA_PIOBM 354 if (xfer->c_flags & (C_DMA | C_PIOBM)) { 355 #if NATA_DMA 356 if (drvp->n_xfers <= NXFER) 357 drvp->n_xfers++; 358 #endif 359 dma_flags = (ata_bio->flags & ATA_READ) ? WDC_DMA_READ : 0; 360 if (ata_bio->flags & ATA_LBA48) 361 dma_flags |= WDC_DMA_LBA48; 362 } 363 #endif 364 /* 365 * 366 * When starting a multi-sector transfer, or doing single-sector 367 * transfers... 368 */ 369 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 370 if (ata_bio->flags & ATA_SINGLE) 371 nblks = 1; 372 else 373 nblks = xfer->c_bcount / drvp->lp->d_secsize; 374 /* Check for bad sectors and adjust transfer, if necessary. */ 375 if ((drvp->lp->d_flags & D_BADSECT) != 0) { 376 long blkdiff; 377 int i; 378 for (i = 0; (blkdiff = drvp->badsect[i]) != -1; 379 i++) { 380 blkdiff -= ata_bio->blkno; 381 if (blkdiff < 0) 382 continue; 383 if (blkdiff == 0) { 384 /* Replace current block of transfer. */ 385 ata_bio->blkno = 386 drvp->lp->d_secperunit - 387 drvp->lp->d_nsectors - i - 1; 388 } 389 if (blkdiff < nblks) { 390 /* Bad block inside transfer. */ 391 ata_bio->flags |= ATA_SINGLE; 392 nblks = 1; 393 } 394 break; 395 } 396 /* Transfer is okay now. */ 397 } 398 if (ata_bio->flags & ATA_LBA48) { 399 sect = 0; 400 cyl = 0; 401 head = 0; 402 } else if (ata_bio->flags & ATA_LBA) { 403 sect = (ata_bio->blkno >> 0) & 0xff; 404 cyl = (ata_bio->blkno >> 8) & 0xffff; 405 head = (ata_bio->blkno >> 24) & 0x0f; 406 head |= WDSD_LBA; 407 } else { 408 int blkno = ata_bio->blkno; 409 sect = blkno % drvp->lp->d_nsectors; 410 sect++; /* Sectors begin with 1, not 0. */ 411 blkno /= drvp->lp->d_nsectors; 412 head = blkno % drvp->lp->d_ntracks; 413 blkno /= drvp->lp->d_ntracks; 414 cyl = blkno; 415 head |= WDSD_CHS; 416 } 417 #if NATA_DMA 418 if (xfer->c_flags & C_DMA) { 419 uint16_t count = nblks, features = 0; 420 421 ata_bio->nblks = nblks; 422 ata_bio->nbytes = xfer->c_bcount; 423 cmd = (ata_bio->flags & ATA_READ) ? 424 WDCC_READDMA : WDCC_WRITEDMA; 425 /* Init the DMA channel. */ 426 error = (*wdc->dma_init)(wdc->dma_arg, 427 chp->ch_channel, xfer->c_drive, 428 (char *)xfer->c_databuf + xfer->c_skip, 429 ata_bio->nbytes, dma_flags); 430 if (error) { 431 if (error == EINVAL) { 432 /* 433 * We can't do DMA on this transfer 434 * for some reason. Fall back to 435 * PIO. 436 */ 437 xfer->c_flags &= ~C_DMA; 438 error = 0; 439 goto do_pio; 440 } 441 ata_bio->error = ERR_DMA; 442 ata_bio->r_error = 0; 443 return ATASTART_ABORT; 444 } 445 /* Initiate command */ 446 if (wdc->select) 447 wdc->select(chp, xfer->c_drive); 448 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 449 0, WDSD_IBM | (xfer->c_drive << 4)); 450 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, 451 &tfd)) { 452 case WDCWAIT_OK: 453 break; 454 case WDCWAIT_TOUT: 455 goto timeout; 456 case WDCWAIT_THR: 457 return ATASTART_TH; 458 } 459 /* start the DMA channel before */ 460 if ((chp->ch_flags & ATACH_DMA_BEFORE_CMD) != 0) 461 (*wdc->dma_start)(wdc->dma_arg, 462 chp->ch_channel, xfer->c_drive); 463 if (ata_bio->flags & ATA_LBA48) { 464 uint8_t device = WDSD_LBA; 465 cmd = atacmd_to48(cmd); 466 467 atacmd_toncq(xfer, &cmd, &count, &features, 468 &device); 469 470 wdccommandext(chp, xfer->c_drive, cmd, 471 ata_bio->blkno, count, features, device); 472 } else { 473 wdccommand(chp, xfer->c_drive, cmd, cyl, 474 head, sect, count, features); 475 } 476 /* start the DMA channel after */ 477 if ((chp->ch_flags & ATACH_DMA_BEFORE_CMD) == 0) 478 (*wdc->dma_start)(wdc->dma_arg, 479 chp->ch_channel, xfer->c_drive); 480 chp->ch_flags |= ATACH_DMA_WAIT; 481 /* wait for irq */ 482 goto intr; 483 } /* else not DMA */ 484 do_pio: 485 #endif /* NATA_DMA */ 486 #if NATA_PIOBM 487 if ((xfer->c_flags & C_PIOBM) && xfer->c_skip == 0) { 488 if (ata_bio->flags & ATA_POLL) { 489 /* XXX not supported yet --- fall back to PIO */ 490 xfer->c_flags &= ~C_PIOBM; 491 } else { 492 /* Init the DMA channel. */ 493 error = (*wdc->dma_init)(wdc->dma_arg, 494 chp->ch_channel, xfer->c_drive, 495 (char *)xfer->c_databuf + xfer->c_skip, 496 xfer->c_bcount, 497 dma_flags | WDC_DMA_PIOBM_ATA); 498 if (error) { 499 if (error == EINVAL) { 500 /* 501 * We can't do DMA on this 502 * transfer for some reason. 503 * Fall back to PIO. 504 */ 505 xfer->c_flags &= ~C_PIOBM; 506 error = 0; 507 } else { 508 ata_bio->error = ERR_DMA; 509 ata_bio->r_error = 0; 510 return ATASTART_ABORT; 511 } 512 } 513 } 514 } 515 #endif 516 ata_bio->nblks = uimin(nblks, drvp->multi); 517 ata_bio->nbytes = ata_bio->nblks * drvp->lp->d_secsize; 518 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 519 if (ata_bio->nblks > 1) { 520 cmd = (ata_bio->flags & ATA_READ) ? 521 WDCC_READMULTI : WDCC_WRITEMULTI; 522 } else { 523 cmd = (ata_bio->flags & ATA_READ) ? 524 WDCC_READ : WDCC_WRITE; 525 } 526 /* Initiate command! */ 527 if (wdc->select) 528 wdc->select(chp, xfer->c_drive); 529 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 530 WDSD_IBM | (xfer->c_drive << 4)); 531 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, &tfd)) { 532 case WDCWAIT_OK: 533 break; 534 case WDCWAIT_TOUT: 535 goto timeout; 536 case WDCWAIT_THR: 537 return ATASTART_TH; 538 } 539 if (ata_bio->flags & ATA_LBA48) { 540 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 541 ata_bio->blkno, nblks, 0, WDSD_LBA); 542 } else { 543 wdccommand(chp, xfer->c_drive, cmd, cyl, 544 head, sect, nblks, 545 (drvp->lp->d_type == DKTYPE_ST506) ? 546 drvp->lp->d_precompcyl / 4 : 0); 547 } 548 } else if (ata_bio->nblks > 1) { 549 /* The number of blocks in the last stretch may be smaller. */ 550 nblks = xfer->c_bcount / drvp->lp->d_secsize; 551 if (ata_bio->nblks > nblks) { 552 ata_bio->nblks = nblks; 553 ata_bio->nbytes = xfer->c_bcount; 554 } 555 } 556 /* If this was a write and not using DMA, push the data. */ 557 if ((ata_bio->flags & ATA_READ) == 0) { 558 /* 559 * we have to busy-wait here, we can't rely on running in 560 * thread context. 561 */ 562 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL, &tfd) != 0) { 563 printf("%s:%d:%d: timeout waiting for DRQ, " 564 "st=0x%02x, err=0x%02x\n", 565 device_xname(atac->atac_dev), chp->ch_channel, 566 xfer->c_drive, 567 ATACH_ST(tfd), ATACH_ERR(tfd)); 568 if (wdc_ata_err(drvp, ata_bio, tfd) != WDC_ATA_ERR) 569 ata_bio->error = TIMEOUT; 570 return ATASTART_ABORT; 571 } 572 if (wdc_ata_err(drvp, ata_bio, tfd) == WDC_ATA_ERR) { 573 return ATASTART_ABORT; 574 } 575 #if NATA_PIOBM 576 if (xfer->c_flags & C_PIOBM) { 577 /* start the busmastering PIO */ 578 (*wdc->piobm_start)(wdc->dma_arg, 579 chp->ch_channel, xfer->c_drive, 580 xfer->c_skip, ata_bio->nbytes, 0); 581 chp->ch_flags |= ATACH_DMA_WAIT; 582 } else 583 #endif 584 585 wdc->dataout_pio(chp, drvp->drive_flags, 586 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 587 } 588 589 #if NATA_DMA 590 intr: 591 #endif 592 /* Wait for IRQ (either real or polled) */ 593 if ((xfer->c_flags & C_POLL) == 0) { 594 /* start timeout machinery */ 595 callout_reset(&chp->c_timo_callout, 596 ATA_DELAY / 1000 * hz, wdctimeout, chp); 597 chp->ch_flags |= ATACH_IRQ_WAIT; 598 return ATASTART_STARTED; 599 } else { 600 return ATASTART_POLL; 601 } 602 603 timeout: 604 printf("%s:%d:%d: not ready, st=0x%02x, err=0x%02x\n", 605 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 606 ATACH_ST(tfd), ATACH_ERR(tfd)); 607 if (wdc_ata_err(drvp, ata_bio, tfd) != WDC_ATA_ERR) 608 ata_bio->error = TIMEOUT; 609 return ATASTART_ABORT; 610 } 611 612 static int 613 wdc_ata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 614 { 615 /* Wait for at last 400ns for status bit to be valid */ 616 delay(1); 617 #if NATA_DMA 618 if (chp->ch_flags & ATACH_DMA_WAIT) { 619 wdc_dmawait(chp, xfer, ATA_DELAY); 620 chp->ch_flags &= ~ATACH_DMA_WAIT; 621 } 622 #endif 623 wdc_ata_bio_intr(chp, xfer, 0); 624 return (xfer->c_bio.flags & ATA_ITSDONE) ? ATAPOLL_DONE : ATAPOLL_AGAIN; 625 } 626 627 static int 628 wdc_ata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 629 { 630 struct atac_softc *atac = chp->ch_atac; 631 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 632 struct ata_bio *ata_bio = &xfer->c_bio; 633 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 634 int drv_err, tfd; 635 636 ATADEBUG_PRINT(("wdc_ata_bio_intr %s:%d:%d\n", 637 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 638 DEBUG_INTR | DEBUG_XFERS); 639 640 ata_channel_lock(chp); 641 642 /* Is it not a transfer, but a control operation? */ 643 if (drvp->state < READY) { 644 printf("%s:%d:%d: bad state %d in wdc_ata_bio_intr\n", 645 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 646 drvp->state); 647 panic("wdc_ata_bio_intr: bad state"); 648 } 649 650 /* 651 * if we missed an interrupt in a PIO transfer, reset and restart. 652 * Don't try to continue transfer, we may have missed cycles. 653 */ 654 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 655 ata_bio->error = TIMEOUT; 656 goto err; 657 } 658 659 #if NATA_PIOBM 660 /* Transfer-done interrupt for busmastering PIO read */ 661 if ((xfer->c_flags & C_PIOBM) && (chp->ch_flags & ATACH_PIOBM_WAIT)) { 662 chp->ch_flags &= ~ATACH_PIOBM_WAIT; 663 goto end; 664 } 665 #endif 666 667 /* Ack interrupt done by wdc_wait_for_unbusy */ 668 if (wdc_wait_for_unbusy(chp, 669 (irq == 0) ? ATA_DELAY : 0, AT_POLL, &tfd) < 0) { 670 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 671 ata_channel_unlock(chp); 672 return 0; /* IRQ was not for us */ 673 } 674 printf("%s:%d:%d: device timeout, c_bcount=%d, c_skip%d\n", 675 device_xname(atac->atac_dev), chp->ch_channel, 676 xfer->c_drive, xfer->c_bcount, xfer->c_skip); 677 ata_bio->error = TIMEOUT; 678 goto err; 679 } 680 if (wdc->irqack) 681 wdc->irqack(chp); 682 683 drv_err = wdc_ata_err(drvp, ata_bio, tfd); 684 685 #if NATA_DMA 686 /* If we were using DMA, Turn off the DMA channel and check for error */ 687 if (xfer->c_flags & C_DMA) { 688 if (ata_bio->flags & ATA_POLL) { 689 /* 690 * IDE drives deassert WDCS_BSY before transfer is 691 * complete when using DMA. Polling for DRQ to deassert 692 * is not enough DRQ is not required to be 693 * asserted for DMA transfers, so poll for DRDY. 694 */ 695 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 696 ATA_DELAY, ATA_POLL, &tfd) == WDCWAIT_TOUT) { 697 printf("%s:%d:%d: polled transfer timed out " 698 "(st=0x%x)\n", 699 device_xname(atac->atac_dev), 700 chp->ch_channel, xfer->c_drive, 701 ATACH_ST(tfd)); 702 ata_bio->error = TIMEOUT; 703 drv_err = WDC_ATA_ERR; 704 } 705 } 706 if (wdc->dma_status != 0) { 707 if (drv_err != WDC_ATA_ERR) { 708 ata_bio->error = ERR_DMA; 709 drv_err = WDC_ATA_ERR; 710 } 711 } 712 if (ATACH_ST(tfd) & WDCS_DRQ) { 713 if (drv_err != WDC_ATA_ERR) { 714 printf("%s:%d:%d: intr with DRQ (st=0x%x)\n", 715 device_xname(atac->atac_dev), 716 chp->ch_channel, 717 xfer->c_drive, ATACH_ST(tfd)); 718 ata_bio->error = TIMEOUT; 719 drv_err = WDC_ATA_ERR; 720 } 721 } 722 if (drv_err != WDC_ATA_ERR) 723 goto end; 724 if (ata_bio->r_error & WDCE_CRC || ata_bio->error == ERR_DMA) { 725 ata_dmaerr(drvp, 726 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 727 goto err; 728 } 729 } 730 #endif /* NATA_DMA */ 731 732 /* if we had an error, end */ 733 if (drv_err == WDC_ATA_ERR) 734 goto err; 735 736 /* If this was a read and not using DMA, fetch the data. */ 737 if ((ata_bio->flags & ATA_READ) != 0) { 738 if ((ATACH_ST(tfd) & WDCS_DRQ) != WDCS_DRQ) { 739 printf("%s:%d:%d: read intr before drq\n", 740 device_xname(atac->atac_dev), chp->ch_channel, 741 xfer->c_drive); 742 ata_bio->error = TIMEOUT; 743 goto err; 744 } 745 #if NATA_PIOBM 746 if (xfer->c_flags & C_PIOBM) { 747 /* start the busmastering PIO */ 748 (*wdc->piobm_start)(wdc->dma_arg, 749 chp->ch_channel, xfer->c_drive, 750 xfer->c_skip, ata_bio->nbytes, 751 WDC_PIOBM_XFER_IRQ); 752 chp->ch_flags |= ATACH_DMA_WAIT | ATACH_PIOBM_WAIT; 753 ata_channel_unlock(chp); 754 return 1; 755 } 756 #endif 757 wdc->datain_pio(chp, drvp->drive_flags, 758 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 759 } 760 761 #if NATA_DMA || NATA_PIOBM 762 end: 763 #endif 764 ata_bio->blkno += ata_bio->nblks; 765 ata_bio->blkdone += ata_bio->nblks; 766 xfer->c_skip += ata_bio->nbytes; 767 xfer->c_bcount -= ata_bio->nbytes; 768 769 /* See if this transfer is complete. */ 770 if (xfer->c_bcount > 0) { 771 if ((ata_bio->flags & ATA_POLL) == 0) { 772 /* Start the next operation */ 773 KASSERT((chp->ch_flags & ATACH_IRQ_WAIT) == 0); 774 callout_stop(&chp->c_timo_callout); 775 ata_xfer_start(xfer); 776 } else { 777 /* 778 * Let ata_xfer_start() do the loop; 779 * see wdc_ata_bio_poll(). 780 */ 781 } 782 ata_channel_unlock(chp); 783 return 1; 784 } 785 786 /* Done with this transfer */ 787 ata_bio->error = NOERROR; 788 err: ata_channel_unlock(chp); 789 wdc_ata_bio_done(chp, xfer); 790 return 1; 791 } 792 793 static void 794 wdc_ata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 795 int reason) 796 { 797 struct ata_bio *ata_bio = &xfer->c_bio; 798 int drive = xfer->c_drive; 799 bool deactivate = true; 800 801 ata_bio->flags |= ATA_ITSDONE; 802 switch (reason) { 803 case KILL_GONE_INACTIVE: 804 deactivate = false; 805 /* FALLTHROUGH */ 806 case KILL_GONE: 807 ata_bio->error = ERR_NODEV; 808 break; 809 case KILL_RESET: 810 ata_bio->error = ERR_RESET; 811 break; 812 default: 813 printf("wdc_ata_bio_kill_xfer: unknown reason %d\n", 814 reason); 815 panic("wdc_ata_bio_kill_xfer"); 816 } 817 ata_bio->r_error = WDCE_ABRT; 818 819 if (deactivate) 820 ata_deactivate_xfer(chp, xfer); 821 822 ATADEBUG_PRINT(("wdc_ata_bio_kill_xfer: drv_done\n"), DEBUG_XFERS); 823 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 824 } 825 826 static void 827 wdc_ata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 828 { 829 struct ata_bio *ata_bio = &xfer->c_bio; 830 int drive = xfer->c_drive; 831 832 ATADEBUG_PRINT(("wdc_ata_bio_done %s:%d:%d: flags 0x%x\n", 833 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 834 xfer->c_drive, (u_int)xfer->c_flags), 835 DEBUG_XFERS); 836 837 if (ata_waitdrain_xfer_check(chp, xfer)) 838 return; 839 840 /* feed back residual bcount to our caller */ 841 ata_bio->bcount = xfer->c_bcount; 842 843 /* mark controller inactive and free xfer */ 844 ata_deactivate_xfer(chp, xfer); 845 846 ata_bio->flags |= ATA_ITSDONE; 847 ATADEBUG_PRINT(("wdc_ata_done: drv_done\n"), DEBUG_XFERS); 848 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 849 ATADEBUG_PRINT(("atastart from wdc_ata_done, flags 0x%x\n", 850 chp->ch_flags), DEBUG_XFERS); 851 atastart(chp); 852 } 853 854 static int 855 wdc_ata_err(struct ata_drive_datas *drvp, struct ata_bio *ata_bio, int tfd) 856 { 857 ata_bio->error = 0; 858 if (ATACH_ST(tfd) & WDCS_BSY) { 859 ata_bio->error = TIMEOUT; 860 return WDC_ATA_ERR; 861 } 862 863 if (ATACH_ST(tfd) & WDCS_DWF) { 864 ata_bio->error = ERR_DF; 865 return WDC_ATA_ERR; 866 } 867 868 if (ATACH_ST(tfd) & WDCS_ERR) { 869 ata_bio->error = ERROR; 870 ata_bio->r_error = ATACH_ERR(tfd); 871 if (ata_bio->r_error & (WDCE_BBK | WDCE_UNC | WDCE_IDNF | 872 WDCE_ABRT | WDCE_TK0NF | WDCE_AMNF)) 873 return WDC_ATA_ERR; 874 return WDC_ATA_NOERR; 875 } 876 877 if (ATACH_ST(tfd) & WDCS_CORR) 878 ata_bio->flags |= ATA_CORR; 879 return WDC_ATA_NOERR; 880 } 881 882 static int 883 wdc_ata_addref(struct ata_drive_datas *drvp) 884 { 885 struct ata_channel *chp = drvp->chnl_softc; 886 887 return (ata_addref(chp)); 888 } 889 890 static void 891 wdc_ata_delref(struct ata_drive_datas *drvp) 892 { 893 struct ata_channel *chp = drvp->chnl_softc; 894 895 ata_delref(chp); 896 } 897
Indexes created Sun Sep 21 16:09:51 GMT 2025