| /src/external/ibm-public/postfix/dist/src/global/ |
| dsb_scan.c | 58 DSN_BUF *dsb = (DSN_BUF *) ptr; local
66 RECV_ATTR_STR(MAIL_ATTR_DSN_STATUS, dsb->status),
67 RECV_ATTR_STR(MAIL_ATTR_DSN_DTYPE, dsb->dtype),
68 RECV_ATTR_STR(MAIL_ATTR_DSN_DTEXT, dsb->dtext),
69 RECV_ATTR_STR(MAIL_ATTR_DSN_MTYPE, dsb->mtype),
70 RECV_ATTR_STR(MAIL_ATTR_DSN_MNAME, dsb->mname),
71 RECV_ATTR_STR(MAIL_ATTR_DSN_ACTION, dsb->action),
72 RECV_ATTR_STR(MAIL_ATTR_WHY, dsb->reason),
|
| deliver_pass.c | 152 static int deliver_pass_final_reply(VSTREAM *stream, DSN_BUF *dsb)
157 RECV_ATTR_FUNC(dsb_scan, (void *) dsb),
174 DSN_BUF *dsb; local
198 dsb = dsb_create();
216 } else if ((status = deliver_pass_final_reply(stream, dsb))
228 dsb_free(dsb);
|
| dsn_buf.c | 29 /* DSN_BUF *dsb_update(dsb, status, action, mtype, mname, dtype,
31 /* DSN_BUF *dsb;
40 /* DSN_BUF *dsb_simple(dsb, status, reason_fmt, ...)
41 /* DSN_BUF *dsb;
45 /* DSN_BUF *dsb_unix(dsb, status, dtext, reason_fmt, ...)
46 /* DSN_BUF *dsb;
50 /* DSN_BUF *dsb_formal(dsb, status, action, mtype, mname, dtype,
52 /* DSN_BUF *dsb;
60 /* DSN_BUF *dsb_status(dsb, status)
61 /* DSN_BUF *dsb;
173 DSN_BUF *dsb; local
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dsb.c | 20 * DOC: DSB
22 * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
23 * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
24 * engine that can be programmed to download the DSB from memory.
27 * faster. DSB Support added from Gen12 Intel graphics based platform.
29 * DSB's can access only the pipe, plane, and transcoder Data Island Packet
32 * DSB HW can support only register writes (both indexed and direct MMIO
33 * writes). There are no registers reads possible with DSB HW engine.
36 /* DSB opcodes. *
109 struct intel_dsb *dsb = &crtc->dsb; local
[all...] |
| intel_color.c | 635 struct intel_dsb *dsb = intel_dsb_get(crtc); local
639 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
640 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
641 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
649 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0),
651 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1),
653 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2),
657 intel_dsb_put(dsb);
817 struct intel_dsb *dsb = intel_dsb_get(crtc); local
821 intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red)
833 struct intel_dsb *dsb = intel_dsb_get(crtc); local
866 struct intel_dsb *dsb = intel_dsb_get(crtc); local
920 struct intel_dsb *dsb = intel_dsb_get(crtc); local
[all...] |
| intel_display_types.h | 1106 /* per pipe DSB related info */
1107 struct intel_dsb dsb; member in struct:intel_crtc
|
| /src/external/ibm-public/postfix/dist/src/oqmgr/ |
| qmgr_deliver.c | 126 static int qmgr_deliver_final_reply(VSTREAM *stream, DSN_BUF *dsb)
134 RECV_ATTR_FUNC(dsb_scan, (void *) dsb),
252 static DSN_BUF *dsb; local
265 if (dsb == 0)
266 dsb = dsb_create();
280 status = qmgr_deliver_final_reply(entry->stream, dsb);
298 DSN_SIMPLE(&dsb->dsn, "4.3.0", whatsup));
302 DSN_SIMPLE(&dsb->dsn, "4.3.0",
323 qmgr_defer_transport(transport, &dsb->dsn);
342 (void) DSN_SIMPLE(&dsb->dsn, "4.3.0", "unknown mail transport error")
[all...] |
| /src/external/ibm-public/postfix/dist/src/qmgr/ |
| qmgr_deliver.c | 131 static int qmgr_deliver_final_reply(VSTREAM *stream, DSN_BUF *dsb)
139 RECV_ATTR_FUNC(dsb_scan, (void *) dsb),
257 static DSN_BUF *dsb; local
270 if (dsb == 0)
271 dsb = dsb_create();
285 status = qmgr_deliver_final_reply(entry->stream, dsb);
303 DSN_SIMPLE(&dsb->dsn, "4.3.0", whatsup));
307 DSN_SIMPLE(&dsb->dsn, "4.3.0",
328 qmgr_defer_transport(transport, &dsb->dsn);
347 (void) DSN_SIMPLE(&dsb->dsn, "4.3.0", "unknown mail transport error")
[all...] |
| /src/sys/arch/arm/include/ |
| cpufunc.h | 47 * Options for DMB and DSB:
61 #define dsb(opt) __asm __volatile("dsb " __STRING(opt) : : : "memory") macro
68 #define dsb(opt) \ macro
79 #define dma_r_r() dsb(oshld) // actually r_rw
80 #define dma_w_w() dsb(oshst)
81 #define dma_rw_w() dsb(osh) // actually rw_rw
83 #define dma_r_r() dsb(osh) // actually rw_rw
84 #define dma_w_w() dsb(oshst)
85 #define dma_rw_w() dsb(osh) // actually rw_r
[all...] |
| /src/external/gpl3/gdb/dist/sim/aarch64/ |
| simulator.c | 13494 dsb (sim_cpu *cpu) function
14138 /* We are interested in HINT, DSB, DMB and ISB
14144 DSB, DMB, ISB are data store barrier, data memory barrier and
14148 op2 : DSB ==> 100, DMB ==> 101, ISB ==> 110
14185 case 4: dsb (cpu); return;
|
| /src/external/gpl3/gdb.old/dist/sim/aarch64/ |
| simulator.c | 13494 dsb (sim_cpu *cpu) function
14138 /* We are interested in HINT, DSB, DMB and ISB
14144 DSB, DMB, ISB are data store barrier, data memory barrier and
14148 op2 : DSB ==> 100, DMB ==> 101, ISB ==> 110
14185 case 4: dsb (cpu); return;
|
