1 /* $NetBSD: edc_mca.c,v 1.55 2022/09/25 17:21:18 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jaromir Dolecek. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for MCA ESDI controllers and disks conforming to IBM DASD 34 * spec. 35 * 36 * The driver was written with DASD Storage Interface Specification 37 * for MCA rev. 2.2 in hands, thanks to Scott Telford <st (at) epcc.ed.ac.uk>. 38 * 39 * TODO: 40 * - improve error recovery 41 * Issue soft reset on error or timeout? 42 * - test with > 1 disk (this is supported by some controllers) 43 * - test with > 1 ESDI controller in machine; shared interrupts 44 * necessary for this to work should be supported - edc_intr() specifically 45 * checks if the interrupt is for this controller 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: edc_mca.c,v 1.55 2022/09/25 17:21:18 thorpej Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/buf.h> 54 #include <sys/bufq.h> 55 #include <sys/errno.h> 56 #include <sys/device.h> 57 #include <sys/endian.h> 58 #include <sys/disklabel.h> 59 #include <sys/disk.h> 60 #include <sys/syslog.h> 61 #include <sys/proc.h> 62 #include <sys/vnode.h> 63 #include <sys/kernel.h> 64 #include <sys/kthread.h> 65 #include <sys/rndsource.h> 66 67 #include <sys/bus.h> 68 #include <sys/intr.h> 69 70 #include <dev/mca/mcareg.h> 71 #include <dev/mca/mcavar.h> 72 #include <dev/mca/mcadevs.h> 73 74 #include <dev/mca/edcreg.h> 75 #include <dev/mca/edvar.h> 76 #include <dev/mca/edcvar.h> 77 78 #include "locators.h" 79 80 #define EDC_ATTN_MAXTRIES 10000 /* How many times check for unbusy */ 81 #define EDC_MAX_CMD_RES_LEN 8 82 83 struct edc_mca_softc { 84 device_t sc_dev; 85 86 bus_space_tag_t sc_iot; 87 bus_space_handle_t sc_ioh; 88 89 /* DMA related stuff */ 90 bus_dma_tag_t sc_dmat; /* DMA tag as passed by parent */ 91 bus_dmamap_t sc_dmamap_xfer; /* transfer dma map */ 92 93 void *sc_ih; /* interrupt handle */ 94 95 int sc_flags; 96 #define DASD_QUIET 0x01 /* don't dump cmd error info */ 97 98 #define DASD_MAXDEVS 8 99 struct ed_softc *sc_ed[DASD_MAXDEVS]; 100 int sc_maxdevs; /* max number of disks attached to this 101 * controller */ 102 103 /* I/O results variables */ 104 volatile int sc_stat; 105 #define STAT_START 0 106 #define STAT_ERROR 1 107 #define STAT_DONE 2 108 volatile int sc_resblk; /* residual block count */ 109 110 /* CMD status block - only set & used in edc_intr() */ 111 u_int16_t status_block[EDC_MAX_CMD_RES_LEN]; 112 }; 113 114 int edc_mca_probe(device_t, cfdata_t, void *); 115 void edc_mca_attach(device_t, device_t, void *); 116 117 CFATTACH_DECL_NEW(edc_mca, sizeof(struct edc_mca_softc), 118 edc_mca_probe, edc_mca_attach, NULL, NULL); 119 120 static int edc_intr(void *); 121 static void edc_dump_status_block(struct edc_mca_softc *, 122 u_int16_t *, int); 123 static int edc_do_attn(struct edc_mca_softc *, int, int, int); 124 static void edc_cmd_wait(struct edc_mca_softc *, int, int); 125 static void edcworker(void *); 126 127 int 128 edc_mca_probe(device_t parent, cfdata_t match, void *aux) 129 { 130 struct mca_attach_args *ma = aux; 131 132 switch (ma->ma_id) { 133 case MCA_PRODUCT_IBM_ESDIC: 134 case MCA_PRODUCT_IBM_ESDIC_IG: 135 return (1); 136 default: 137 return (0); 138 } 139 } 140 141 void 142 edc_mca_attach(device_t parent, device_t self, void *aux) 143 { 144 struct edc_mca_softc *sc = device_private(self); 145 struct mca_attach_args *ma = aux; 146 struct ed_attach_args eda; 147 int pos2, pos3, pos4; 148 int irq, drq, iobase; 149 const char *typestr; 150 int devno, error; 151 int locs[EDCCF_NLOCS]; 152 153 sc->sc_dev = self; 154 155 pos2 = mca_conf_read(ma->ma_mc, ma->ma_slot, 2); 156 pos3 = mca_conf_read(ma->ma_mc, ma->ma_slot, 3); 157 pos4 = mca_conf_read(ma->ma_mc, ma->ma_slot, 4); 158 159 /* 160 * POS register 2: (adf pos0) 161 * 162 * 7 6 5 4 3 2 1 0 163 * \ \____/ \ \__ enable: 0=adapter disabled, 1=adapter enabled 164 * \ \ \___ Primary/Alternate Port Addresses: 165 * \ \ 0=0x3510-3517 1=0x3518-0x351f 166 * \ \_____ DMA Arbitration Level: 0101=5 0110=6 0111=7 167 * \ 0000=0 0001=1 0011=3 0100=4 168 * \_________ Fairness On/Off: 1=On 0=Off 169 * 170 * POS register 3: (adf pos1) 171 * 172 * 7 6 5 4 3 2 1 0 173 * 0 0 \_/ 174 * \__________ DMA Burst Pacing Interval: 10=24ms 11=31ms 175 * 01=16ms 00=Burst Disabled 176 * 177 * POS register 4: (adf pos2) 178 * 179 * 7 6 5 4 3 2 1 0 180 * \_/ \__ DMA Pacing Control: 1=Disabled 0=Enabled 181 * \____ Time to Release: 1X=6ms 01=3ms 00=Immediate 182 * 183 * IRQ is fixed to 14 (0x0e). 184 */ 185 186 switch (ma->ma_id) { 187 case MCA_PRODUCT_IBM_ESDIC: 188 typestr = "IBM ESDI Fixed Disk Controller"; 189 break; 190 case MCA_PRODUCT_IBM_ESDIC_IG: 191 typestr = "IBM Integ. ESDI Fixed Disk & Controller"; 192 break; 193 default: 194 typestr = NULL; 195 break; 196 } 197 198 irq = ESDIC_IRQ; 199 iobase = (pos2 & IO_IS_ALT) ? ESDIC_IOALT : ESDIC_IOPRM; 200 drq = (pos2 & DRQ_MASK) >> 2; 201 202 aprint_naive("\n"); 203 aprint_normal(": slot %d irq %d drq %d: %s\n", ma->ma_slot+1, 204 irq, drq, typestr); 205 206 #ifdef DIAGNOSTIC 207 /* 208 * It's not strictly necessary to check this, machine configuration 209 * utility uses only valid addresses. 210 */ 211 if (drq == 2 || drq >= 8) { 212 aprint_error_dev(sc->sc_dev, 213 "invalid DMA Arbitration Level %d\n", drq); 214 return; 215 } 216 #endif 217 218 aprint_normal_dev(self, "Fairness %s, Release %s, ", 219 (pos2 & FAIRNESS_ENABLE) ? "On" : "Off", 220 (pos4 & RELEASE_1) ? "6ms" 221 : ((pos4 & RELEASE_2) ? "3ms" : "Immediate") 222 ); 223 if ((pos4 & PACING_CTRL_DISABLE) == 0) { 224 static const char * const pacint[] = 225 { "disabled", "16ms", "24ms", "31ms"}; 226 aprint_normal("DMA burst pacing interval %s\n", 227 pacint[(pos3 & PACING_INT_MASK) >> 4]); 228 } else 229 aprint_normal("DMA pacing control disabled\n"); 230 231 sc->sc_iot = ma->ma_iot; 232 233 if (bus_space_map(sc->sc_iot, iobase, 234 ESDIC_REG_NPORTS, 0, &sc->sc_ioh)) { 235 aprint_error_dev(sc->sc_dev, "couldn't map registers\n"); 236 return; 237 } 238 239 sc->sc_ih = mca_intr_establish(ma->ma_mc, irq, IPL_BIO, edc_intr, sc); 240 if (sc->sc_ih == NULL) { 241 aprint_error_dev(sc->sc_dev, 242 "couldn't establish interrupt handler\n"); 243 return; 244 } 245 246 /* Create a MCA DMA map, used for data transfer */ 247 sc->sc_dmat = ma->ma_dmat; 248 if ((error = mca_dmamap_create(sc->sc_dmat, MAXPHYS, 249 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | MCABUS_DMA_16BIT, 250 &sc->sc_dmamap_xfer, drq)) != 0){ 251 aprint_error_dev(sc->sc_dev, 252 "couldn't create DMA map - error %d\n", error); 253 return; 254 } 255 256 /* 257 * Integrated ESDI controller supports only one disk, other 258 * controllers support two disks. 259 */ 260 if (ma->ma_id == MCA_PRODUCT_IBM_ESDIC_IG) 261 sc->sc_maxdevs = 1; 262 else 263 sc->sc_maxdevs = 2; 264 265 /* 266 * Reset controller and attach individual disks. ed attach routine 267 * uses polling so that this works with interrupts disabled. 268 */ 269 270 /* Do a reset to ensure sane state after warm boot. */ 271 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 272 /* hard reset */ 273 aprint_normal_dev(self, "controller busy, " 274 "performing hardware reset ...\n"); 275 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 276 BCR_INT_ENABLE|BCR_RESET); 277 } else { 278 /* "SOFT" reset */ 279 edc_do_attn(sc, ATN_RESET_ATTACHMENT, DASD_DEVNO_CONTROLLER,0); 280 } 281 282 /* 283 * Since interrupts are disabled, it's necessary 284 * to detect the interrupt request and call edc_intr() 285 * explicitly. See also edc_run_cmd(). 286 */ 287 while (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 288 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) 289 edc_intr(sc); 290 291 delay(100); 292 } 293 294 /* be quiet during probes */ 295 sc->sc_flags |= DASD_QUIET; 296 297 /* check for attached disks */ 298 for (devno = 0; devno < sc->sc_maxdevs; devno++) { 299 eda.edc_drive = devno; 300 locs[EDCCF_DRIVE] = devno; 301 302 sc->sc_ed[devno] = device_private( 303 config_found(self, &eda, NULL, 304 CFARGS(.submatch = config_stdsubmatch, 305 .locators = locs))); 306 307 /* If initialization did not succeed, NULL the pointer. */ 308 if (sc->sc_ed[devno] 309 && (sc->sc_ed[devno]->sc_flags & EDF_INIT) == 0) 310 sc->sc_ed[devno] = NULL; 311 } 312 313 /* enable full error dumps again */ 314 sc->sc_flags &= ~DASD_QUIET; 315 316 /* 317 * Check if there are any disks attached. If not, disestablish 318 * the interrupt. 319 */ 320 for (devno = 0; devno < sc->sc_maxdevs; devno++) { 321 if (sc->sc_ed[devno]) 322 break; 323 } 324 325 if (devno == sc->sc_maxdevs) { 326 aprint_error("%s: disabling controller (no drives attached)\n", 327 device_xname(sc->sc_dev)); 328 mca_intr_disestablish(ma->ma_mc, sc->sc_ih); 329 return; 330 } 331 332 /* 333 * Run the worker thread. 334 */ 335 config_pending_incr(self); 336 if ((error = kthread_create(PRI_NONE, 0, NULL, edcworker, sc, NULL, 337 "%s", device_xname(sc->sc_dev)))) { 338 aprint_error_dev(sc->sc_dev, 339 "cannot spawn worker thread: errno=%d\n", error); 340 panic("edc_mca_attach"); 341 } 342 } 343 344 void 345 edc_add_disk(struct edc_mca_softc *sc, struct ed_softc *ed) 346 { 347 sc->sc_ed[ed->sc_devno] = ed; 348 } 349 350 static int 351 edc_intr(void *arg) 352 { 353 struct edc_mca_softc *sc = arg; 354 u_int8_t isr, intr_id; 355 u_int16_t sifr; 356 int cmd = -1, devno; 357 358 /* 359 * Check if the interrupt was for us. 360 */ 361 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) == 0) 362 return (0); 363 364 /* 365 * Read ISR to find out interrupt type. This also clears the interrupt 366 * condition and BSR_INTR flag. Accordings to docs interrupt ID of 0, 2 367 * and 4 are reserved and not used. 368 */ 369 isr = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ISR); 370 intr_id = isr & ISR_INTR_ID_MASK; 371 372 #ifdef EDC_DEBUG 373 if (intr_id == 0 || intr_id == 2 || intr_id == 4) { 374 aprint_error_dev(sc->sc_dev, "bogus interrupt id %d\n", 375 (int) intr_id); 376 return (0); 377 } 378 #endif 379 380 /* Get number of device whose intr this was */ 381 devno = (isr & 0xe0) >> 5; 382 383 /* 384 * Get Status block. Higher byte always says how long the status 385 * block is, rest is device number and command code. 386 * Check the status block length against our supported maximum length 387 * and fetch the data. 388 */ 389 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh,BSR) & BSR_SIFR_FULL) { 390 size_t len; 391 int i; 392 393 sifr = le16toh(bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 394 len = (sifr & 0xff00) >> 8; 395 #ifdef DEBUG 396 if (len > EDC_MAX_CMD_RES_LEN) 397 panic("%s: maximum Status Length exceeded: %d > %d", 398 device_xname(sc->sc_dev), 399 len, EDC_MAX_CMD_RES_LEN); 400 #endif 401 402 /* Get command code */ 403 cmd = sifr & SIFR_CMD_MASK; 404 405 /* Read whole status block */ 406 sc->status_block[0] = sifr; 407 for(i=1; i < len; i++) { 408 while((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 409 & BSR_SIFR_FULL) == 0) 410 ; 411 412 sc->status_block[i] = le16toh( 413 bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 414 } 415 /* zero out rest */ 416 if (i < EDC_MAX_CMD_RES_LEN) { 417 memset(&sc->status_block[i], 0, 418 (EDC_MAX_CMD_RES_LEN-i)*sizeof(u_int16_t)); 419 } 420 } 421 422 switch (intr_id) { 423 case ISR_DATA_TRANSFER_RDY: 424 /* 425 * Ready to do DMA. The DMA controller has already been 426 * setup, now just kick disk controller to do the transfer. 427 */ 428 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 429 BCR_INT_ENABLE|BCR_DMA_ENABLE); 430 break; 431 432 case ISR_COMPLETED: 433 case ISR_COMPLETED_WITH_ECC: 434 case ISR_COMPLETED_RETRIES: 435 case ISR_COMPLETED_WARNING: 436 /* 437 * Copy device config data if appropriate. sc->sc_ed[] 438 * entry might be NULL during probe. 439 */ 440 if (cmd == CMD_GET_DEV_CONF && sc->sc_ed[devno]) { 441 memcpy(sc->sc_ed[devno]->sense_data, sc->status_block, 442 sizeof(sc->sc_ed[devno]->sense_data)); 443 } 444 445 sc->sc_stat = STAT_DONE; 446 break; 447 448 case ISR_RESET_COMPLETED: 449 case ISR_ABORT_COMPLETED: 450 /* nothing to do */ 451 break; 452 453 case ISR_ATTN_ERROR: 454 /* 455 * Basically, this means driver bug or something seriously 456 * hosed. panic rather than extending the lossage. 457 * No status block available, so no further info. 458 */ 459 panic("%s: dev %d: attention error", 460 device_xname(sc->sc_dev), 461 devno); 462 /* NOTREACHED */ 463 break; 464 465 default: 466 if ((sc->sc_flags & DASD_QUIET) == 0) 467 edc_dump_status_block(sc, sc->status_block, intr_id); 468 469 sc->sc_stat = STAT_ERROR; 470 break; 471 } 472 473 /* 474 * Unless the interrupt is for Data Transfer Ready or 475 * Attention Error, finish by assertion EOI. This makes 476 * attachment aware the interrupt is processed and system 477 * is ready to accept another one. 478 */ 479 if (intr_id != ISR_DATA_TRANSFER_RDY && intr_id != ISR_ATTN_ERROR) 480 edc_do_attn(sc, ATN_END_INT, devno, intr_id); 481 482 /* If Read or Write Data, wakeup worker thread to finish it */ 483 if (intr_id != ISR_DATA_TRANSFER_RDY) { 484 if (cmd == CMD_READ_DATA || cmd == CMD_WRITE_DATA) 485 sc->sc_resblk = sc->status_block[SB_RESBLKCNT_IDX]; 486 wakeup(sc); 487 } 488 489 return (1); 490 } 491 492 /* 493 * This follows the exact order for Attention Request as 494 * written in DASD Storage Interface Specification MC (Rev 2.2). 495 */ 496 static int 497 edc_do_attn(struct edc_mca_softc *sc, int attn_type, int devno, int intr_id) 498 { 499 int tries; 500 501 /* 1. Disable interrupts in BCR. */ 502 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 0); 503 504 /* 505 * 2. Assure NOT BUSY and NO INTERRUPT PENDING, unless acknowledging 506 * a RESET COMPLETED interrupt. 507 */ 508 if (intr_id != ISR_RESET_COMPLETED) { 509 #ifdef EDC_DEBUG 510 if (attn_type == ATN_CMD_REQ 511 && (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 512 & BSR_INT_PENDING)) 513 panic("%s: edc int pending", device_xname(sc->sc_dev)); 514 #endif 515 516 for(tries=1; tries < EDC_ATTN_MAXTRIES; tries++) { 517 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 518 & BSR_BUSY) == 0) 519 break; 520 } 521 522 if (tries == EDC_ATTN_MAXTRIES) { 523 printf("%s: edc_do_attn: timeout waiting for " 524 "attachment to become available\n", 525 device_xname(sc->sc_ed[devno]->sc_dev)); 526 return (EIO); 527 } 528 } 529 530 /* 531 * 3. Write proper DEVICE NUMBER and Attention number to ATN. 532 */ 533 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ATN, attn_type | (devno<<5)); 534 535 /* 536 * 4. Enable interrupts via BCR. 537 */ 538 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, BCR_INT_ENABLE); 539 540 return (0); 541 } 542 543 /* 544 * Wait until command is processed, timeout after 'secs' seconds. 545 * We use mono_time, since we don't need actual RTC, just time 546 * interval. 547 */ 548 static void 549 edc_cmd_wait(struct edc_mca_softc *sc, int secs, int poll) 550 { 551 int val; 552 553 if (!poll) { 554 int s; 555 556 /* Not polling, can sleep. Sleep until we are awakened, 557 * but maximum secs seconds. 558 */ 559 s = splbio(); 560 if (sc->sc_stat != STAT_DONE) 561 (void) tsleep(sc, PRIBIO, "edcwcmd", secs * hz); 562 splx(s); 563 } 564 565 /* Wait until the command is completely finished */ 566 while((val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR)) 567 & BSR_CMD_INPROGRESS) { 568 if (poll && (val & BSR_INTR)) 569 edc_intr(sc); 570 } 571 } 572 573 /* 574 * Command controller to execute specified command on a device. 575 */ 576 int 577 edc_run_cmd(struct edc_mca_softc *sc, int cmd, int devno, 578 u_int16_t cmd_args[], int cmd_len, int poll) 579 { 580 int i, error, tries; 581 u_int16_t cmd0; 582 583 sc->sc_stat = STAT_START; 584 585 /* Do Attention Request for Command Request. */ 586 if ((error = edc_do_attn(sc, ATN_CMD_REQ, devno, 0))) 587 return (error); 588 589 /* 590 * Construct the command. The bits are like this: 591 * 592 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 593 * \_/ 0 0 1 0 \__/ \_____/ 594 * \ \__________/ \ \_ Command Code (see CMD_*) 595 * \ \ \__ Device: 0 common, 7 controller 596 * \ \__ Options: reserved, bit 10=cache bypass bit 597 * \_ Type: 00=2B, 01=4B, 10 and 11 reserved 598 * 599 * We always use device 0 or 1, so difference is made only by Command 600 * Code, Command Options and command length. 601 */ 602 cmd0 = ((cmd_len == 4) ? (CIFR_LONG_CMD) : 0) 603 | (devno << 5) 604 | (cmd_args[0] << 8) | cmd; 605 cmd_args[0] = cmd0; 606 607 /* 608 * Write word of CMD to the CIFR. This sets "Command 609 * Interface Register Full (CMD IN)" in BSR. Once the attachment 610 * detects it, it reads the word and clears CMD IN. This all should 611 * be quite fast, so don't sleep in !poll case neither. 612 */ 613 for(i=0; i < cmd_len; i++) { 614 bus_space_write_2(sc->sc_iot, sc->sc_ioh, CIFR, 615 htole16(cmd_args[i])); 616 617 /* Wait until CMD IN is cleared. */ 618 tries = 0; 619 for(; (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 620 & BSR_CIFR_FULL) && tries < 10000 ; tries++) 621 delay(poll ? 1000 : 1); 622 ; 623 624 if (tries == 10000 625 && bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 626 & BSR_CIFR_FULL) { 627 aprint_error_dev(sc->sc_dev, 628 "device too slow to accept command %d\n", cmd); 629 return (EIO); 630 } 631 } 632 633 /* Wait for command to complete, but maximum 15 seconds. */ 634 edc_cmd_wait(sc, 15, poll); 635 636 return ((sc->sc_stat != STAT_DONE) ? EIO : 0); 637 } 638 639 #ifdef EDC_DEBUG 640 static const char * const edc_commands[] = { 641 "Invalid Command", 642 "Read Data", 643 "Write Data", 644 "Read Verify", 645 "Write with Verify", 646 "Seek", 647 "Park Head", 648 "Get Command Complete Status", 649 "Get Device Status", 650 "Get Device Configuration", 651 "Get POS Information", 652 "Translate RBA", 653 "Write Attachment Buffer", 654 "Read Attachment Buffer", 655 "Run Diagnostic Test", 656 "Get Diagnostic Status Block", 657 "Get MFG Header", 658 "Format Unit", 659 "Format Prepare", 660 "Set MAX RBA", 661 "Set Power Saving Mode", 662 "Power Conservation Command", 663 }; 664 665 static const char * const edc_cmd_status[256] = { 666 "Reserved", 667 "Command completed successfully", 668 "Reserved", 669 "Command completed successfully with ECC applied", 670 "Reserved", 671 "Command completed successfully with retries", 672 "Format Command partially completed", /* Status available */ 673 "Command completed successfully with ECC and retries", 674 "Command completed with Warning", /* Command Error is available */ 675 "Aborted", 676 "Reset completed", 677 "Data Transfer Ready", /* No Status Block available */ 678 "Command terminated with failure", /* Device Error is available */ 679 "DMA Error", /* Retry entire command as recovery */ 680 "Command Block Error", 681 "Attention Error (Illegal Attention Code)", 682 /* 0x14 - 0xff reserved */ 683 }; 684 685 static const char * const edc_cmd_error[256] = { 686 "No Error", 687 "Invalid parameter in the command block", 688 "Reserved", 689 "Command not supported", 690 "Command Aborted per request", 691 "Reserved", 692 "Command rejected", /* Attachment diagnostic failure */ 693 "Format Rejected", /* Prepare Format command is required */ 694 "Format Error (Primary Map is not readable)", 695 "Format Error (Secondary map is not readable)", 696 "Format Error (Diagnostic Failure)", 697 "Format Warning (Secondary Map Overflow)", 698 "Reserved" 699 "Format Error (Host Checksum Error)", 700 "Reserved", 701 "Format Warning (Push table overflow)", 702 "Format Warning (More pushes than allowed)", 703 "Reserved", 704 "Format Warning (Error during verifying)", 705 "Invalid device number for the command", 706 /* 0x14-0xff reserved */ 707 }; 708 709 static const char * const edc_dev_errors[] = { 710 "No Error", 711 "Seek Fault", /* Device report */ 712 "Interface Fault (Parity, Attn, or Cmd Complete Error)", 713 "Block not found (ID not found)", 714 "Block not found (AM not found)", 715 "Data ECC Error (hard error)", 716 "ID CRC Error", 717 "RBA Out of Range", 718 "Reserved", 719 "Defective Block", 720 "Reserved", 721 "Selection Error", 722 "Reserved", 723 "Write Fault", 724 "No index or sector pulse", 725 "Device Not Ready", 726 "Seek Error", /* Attachment report */ 727 "Bad Format", 728 "Volume Overflow", 729 "No Data AM Found", 730 "Block not found (No ID AM or ID CRC error occurred)", 731 "Reserved", 732 "Reserved", 733 "No ID found on track (ID search)", 734 /* 0x19 - 0xff reserved */ 735 }; 736 #endif /* EDC_DEBUG */ 737 738 static void 739 edc_dump_status_block(struct edc_mca_softc *sc, u_int16_t *status_block, 740 int intr_id) 741 { 742 #ifdef EDC_DEBUG 743 printf("%s: Command: %s, Status: %s (intr %d)\n", 744 device_xname(sc->sc_dev), 745 edc_commands[status_block[0] & 0x1f], 746 edc_cmd_status[SB_GET_CMD_STATUS(status_block)], 747 intr_id 748 ); 749 #else 750 printf("%s: Command: %d, Status: %d (intr %d)\n", 751 device_xname(sc->sc_dev), 752 status_block[0] & 0x1f, 753 SB_GET_CMD_STATUS(status_block), 754 intr_id 755 ); 756 #endif 757 printf("%s: # left blocks: %u, last processed RBA: %u\n", 758 device_xname(sc->sc_dev), 759 status_block[SB_RESBLKCNT_IDX], 760 (status_block[5] << 16) | status_block[4]); 761 762 if (intr_id == ISR_COMPLETED_WARNING) { 763 #ifdef EDC_DEBUG 764 aprint_error_dev(sc->sc_dev, "Command Error Code: %s\n", 765 edc_cmd_error[status_block[1] & 0xff]); 766 #else 767 aprint_error_dev(sc->sc_dev, "Command Error Code: %d\n", 768 status_block[1] & 0xff); 769 #endif 770 } 771 772 if (intr_id == ISR_CMD_FAILED) { 773 #ifdef EDC_DEBUG 774 char buf[100]; 775 776 printf("%s: Device Error Code: %s\n", 777 device_xname(sc->sc_dev), 778 edc_dev_errors[status_block[2] & 0xff]); 779 snprintb(buf, sizeof(buf), 780 "\20" 781 "\01SeekOrCmdComplete" 782 "\02Track0Flag" 783 "\03WriteFault" 784 "\04Selected" 785 "\05Ready" 786 "\06Reserved0" 787 "\07STANDBY" 788 "\010Reserved0", (status_block[2] & 0xff00) >> 8); 789 790 printf("%s: Device Status: %s\n", 791 device_xname(sc->sc_dev), buf); 792 #else 793 printf("%s: Device Error Code: %d, Device Status: %d\n", 794 device_xname(sc->sc_dev), 795 status_block[2] & 0xff, 796 (status_block[2] & 0xff00) >> 8); 797 #endif 798 } 799 } 800 /* 801 * Main worker thread function. 802 */ 803 void 804 edcworker(void *arg) 805 { 806 struct edc_mca_softc *sc = (struct edc_mca_softc *) arg; 807 struct ed_softc *ed; 808 struct buf *bp; 809 int i, error; 810 811 config_pending_decr(sc->sc_dev); 812 813 for(;;) { 814 /* Wait until awakened */ 815 (void) tsleep(sc, PRIBIO, "edcidle", 0); 816 817 for(i=0; i<sc->sc_maxdevs; ) { 818 if ((ed = sc->sc_ed[i]) == NULL) { 819 i++; 820 continue; 821 } 822 823 /* Is there a buf for us ? */ 824 mutex_enter(&ed->sc_q_lock); 825 if ((bp = bufq_get(ed->sc_q)) == NULL) { 826 mutex_exit(&ed->sc_q_lock); 827 i++; 828 continue; 829 } 830 mutex_exit(&ed->sc_q_lock); 831 832 /* Instrumentation. */ 833 disk_busy(&ed->sc_dk); 834 835 error = edc_bio(sc, ed, bp->b_data, bp->b_bcount, 836 bp->b_rawblkno, (bp->b_flags & B_READ), 0); 837 838 if (error) { 839 bp->b_error = error; 840 } else { 841 /* Set resid, most commonly to zero. */ 842 bp->b_resid = sc->sc_resblk * DEV_BSIZE; 843 } 844 845 disk_unbusy(&ed->sc_dk, (bp->b_bcount - bp->b_resid), 846 (bp->b_flags & B_READ)); 847 rnd_add_uint32(&ed->rnd_source, bp->b_blkno); 848 biodone(bp); 849 } 850 } 851 } 852 853 int 854 edc_bio(struct edc_mca_softc *sc, struct ed_softc *ed, void *data, 855 size_t bcount, daddr_t rawblkno, int isread, int poll) 856 { 857 u_int16_t cmd_args[4]; 858 int error=0, fl; 859 u_int16_t track; 860 u_int16_t cyl; 861 u_int8_t head; 862 u_int8_t sector; 863 864 mca_disk_busy(); 865 866 /* set WAIT and R/W flag appropriately for the DMA transfer */ 867 fl = ((poll) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK) 868 | ((isread) ? BUS_DMA_READ : BUS_DMA_WRITE); 869 870 /* Load the buffer for DMA transfer. */ 871 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_xfer, data, 872 bcount, NULL, BUS_DMA_STREAMING|fl))) { 873 printf("%s: ed_bio: unable to load DMA buffer - error %d\n", 874 device_xname(ed->sc_dev), error); 875 goto out; 876 } 877 878 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, 879 bcount, (isread) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 880 881 track = rawblkno / ed->sectors; 882 head = track % ed->heads; 883 cyl = track / ed->heads; 884 sector = rawblkno % ed->sectors; 885 886 /* Read or Write Data command */ 887 cmd_args[0] = 2; /* Options 0000010 */ 888 cmd_args[1] = bcount / DEV_BSIZE; 889 cmd_args[2] = ((cyl & 0x1f) << 11) | (head << 5) | sector; 890 cmd_args[3] = ((cyl & 0x3E0) >> 5); 891 error = edc_run_cmd(sc, 892 (isread) ? CMD_READ_DATA : CMD_WRITE_DATA, 893 ed->sc_devno, cmd_args, 4, poll); 894 895 /* Sync the DMA memory */ 896 if (!error) { 897 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, bcount, 898 (isread)? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 899 } 900 901 /* We are done, unload buffer from DMA map */ 902 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_xfer); 903 904 out: 905 mca_disk_unbusy(); 906 907 return (error); 908 } 909
Indexes created Sun Sep 21 20:09:37 GMT 2025