1 /* $NetBSD: if_enet.c,v 1.37 2024/02/07 04:20:26 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2014 Ryo Shimizu 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * i.MX6,7 10/100/1000-Mbps ethernet MAC (ENET) 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_enet.c,v 1.37 2024/02/07 04:20:26 msaitoh Exp $"); 35 36 #include "vlan.h" 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/mbuf.h> 41 #include <sys/device.h> 42 #include <sys/sockio.h> 43 #include <sys/kernel.h> 44 #include <sys/rndsource.h> 45 46 #include <lib/libkern/libkern.h> 47 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 #include <net/if_ether.h> 52 #include <net/bpf.h> 53 #include <net/if_vlanvar.h> 54 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/ip.h> 58 59 #include <dev/mii/mii.h> 60 #include <dev/mii/miivar.h> 61 62 #include <arm/imx/if_enetreg.h> 63 #include <arm/imx/if_enetvar.h> 64 65 #undef DEBUG_ENET 66 #undef ENET_EVENT_COUNTER 67 68 #define ENET_TICK hz 69 70 #ifdef DEBUG_ENET 71 int enet_debug = 0; 72 # define DEVICE_DPRINTF(args...) \ 73 do { if (enet_debug) device_printf(sc->sc_dev, args); } while (0) 74 #else 75 # define DEVICE_DPRINTF(args...) 76 #endif 77 78 79 #define RXDESC_MAXBUFSIZE 0x07f0 80 /* ENET does not work greather than 0x0800... */ 81 82 #undef ENET_SUPPORT_JUMBO /* JUMBO FRAME SUPPORT is unstable */ 83 #ifdef ENET_SUPPORT_JUMBO 84 # define ENET_MAX_PKT_LEN 4034 /* MAX FIFO LEN */ 85 #else 86 # define ENET_MAX_PKT_LEN 1522 87 #endif 88 #define ENET_DEFAULT_PKT_LEN 1522 /* including VLAN tag */ 89 #define MTU2FRAMESIZE(n) \ 90 ((n) + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN) 91 92 93 #define ENET_MAX_PKT_NSEGS 64 94 95 #define ENET_TX_NEXTIDX(idx) \ 96 (((idx) >= (ENET_TX_RING_CNT - 1)) ? 0 : ((idx) + 1)) 97 #define ENET_RX_NEXTIDX(idx) \ 98 (((idx) >= (ENET_RX_RING_CNT - 1)) ? 0 : ((idx) + 1)) 99 100 #define TXDESC_WRITEOUT(idx) \ 101 bus_dmamap_sync(sc->sc_dmat, sc->sc_txdesc_dmamap, \ 102 sizeof(struct enet_txdesc) * (idx), \ 103 sizeof(struct enet_txdesc), \ 104 BUS_DMASYNC_PREWRITE) 105 106 #define TXDESC_READIN(idx) \ 107 bus_dmamap_sync(sc->sc_dmat, sc->sc_txdesc_dmamap, \ 108 sizeof(struct enet_txdesc) * (idx), \ 109 sizeof(struct enet_txdesc), \ 110 BUS_DMASYNC_PREREAD) 111 112 #define RXDESC_WRITEOUT(idx) \ 113 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxdesc_dmamap, \ 114 sizeof(struct enet_rxdesc) * (idx), \ 115 sizeof(struct enet_rxdesc), \ 116 BUS_DMASYNC_PREWRITE) 117 118 #define RXDESC_READIN(idx) \ 119 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxdesc_dmamap, \ 120 sizeof(struct enet_rxdesc) * (idx), \ 121 sizeof(struct enet_rxdesc), \ 122 BUS_DMASYNC_PREREAD) 123 124 #define ENET_REG_READ(sc, reg) \ 125 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, reg) 126 127 #define ENET_REG_WRITE(sc, reg, value) \ 128 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, reg, value) 129 130 #ifdef ENET_EVENT_COUNTER 131 static void enet_attach_evcnt(struct enet_softc *); 132 static void enet_update_evcnt(struct enet_softc *); 133 #endif 134 135 static void enet_tick(void *); 136 static int enet_tx_intr(void *); 137 static int enet_rx_intr(void *); 138 static void enet_rx_csum(struct enet_softc *, struct ifnet *, struct mbuf *, 139 int); 140 141 static void enet_start(struct ifnet *); 142 static int enet_ifflags_cb(struct ethercom *); 143 static int enet_ioctl(struct ifnet *, u_long, void *); 144 static int enet_init(struct ifnet *); 145 static void enet_stop(struct ifnet *, int); 146 static void enet_watchdog(struct ifnet *); 147 static void enet_mediastatus(struct ifnet *, struct ifmediareq *); 148 149 static int enet_miibus_readreg(device_t, int, int, uint16_t *); 150 static int enet_miibus_writereg(device_t, int, int, uint16_t); 151 static void enet_miibus_statchg(struct ifnet *); 152 153 static void enet_gethwaddr(struct enet_softc *, uint8_t *); 154 static void enet_sethwaddr(struct enet_softc *, uint8_t *); 155 static void enet_setmulti(struct enet_softc *); 156 static int enet_encap_mbufalign(struct mbuf **); 157 static int enet_encap_txring(struct enet_softc *, struct mbuf **); 158 static int enet_init_regs(struct enet_softc *, int); 159 static int enet_alloc_ring(struct enet_softc *); 160 static void enet_init_txring(struct enet_softc *); 161 static int enet_init_rxring(struct enet_softc *); 162 static void enet_reset_rxdesc(struct enet_softc *, int); 163 static int enet_alloc_rxbuf(struct enet_softc *, int); 164 static void enet_drain_txbuf(struct enet_softc *); 165 static void enet_drain_rxbuf(struct enet_softc *); 166 static int enet_alloc_dma(struct enet_softc *, size_t, void **, 167 bus_dmamap_t *); 168 169 int 170 enet_attach_common(device_t self) 171 { 172 struct enet_softc *sc = device_private(self); 173 struct ifnet *ifp; 174 struct mii_data * const mii = &sc->sc_mii; 175 176 /* allocate dma buffer */ 177 if (enet_alloc_ring(sc)) 178 return -1; 179 180 #define IS_ENADDR_ZERO(enaddr) \ 181 ((enaddr[0] | enaddr[1] | enaddr[2] | \ 182 enaddr[3] | enaddr[4] | enaddr[5]) == 0) 183 184 if (IS_ENADDR_ZERO(sc->sc_enaddr)) { 185 /* by any chance, mac-address is already set by bootloader? */ 186 enet_gethwaddr(sc, sc->sc_enaddr); 187 if (IS_ENADDR_ZERO(sc->sc_enaddr)) { 188 /* give up. set randomly */ 189 uint32_t eaddr = random(); 190 /* not multicast */ 191 sc->sc_enaddr[0] = (eaddr >> 24) & 0xfc; 192 sc->sc_enaddr[1] = eaddr >> 16; 193 sc->sc_enaddr[2] = eaddr >> 8; 194 sc->sc_enaddr[3] = eaddr; 195 eaddr = random(); 196 sc->sc_enaddr[4] = eaddr >> 8; 197 sc->sc_enaddr[5] = eaddr; 198 199 aprint_error_dev(self, 200 "cannot get mac address. set randomly\n"); 201 } 202 } 203 enet_sethwaddr(sc, sc->sc_enaddr); 204 205 aprint_normal_dev(self, "Ethernet address %s\n", 206 ether_sprintf(sc->sc_enaddr)); 207 208 enet_init_regs(sc, 1); 209 210 /* callout will be scheduled from enet_init() */ 211 callout_init(&sc->sc_tick_ch, 0); 212 callout_setfunc(&sc->sc_tick_ch, enet_tick, sc); 213 214 /* setup ifp */ 215 ifp = &sc->sc_ethercom.ec_if; 216 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 217 ifp->if_softc = sc; 218 ifp->if_mtu = ETHERMTU; 219 ifp->if_baudrate = IF_Gbps(1); 220 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 221 ifp->if_ioctl = enet_ioctl; 222 ifp->if_start = enet_start; 223 ifp->if_init = enet_init; 224 ifp->if_stop = enet_stop; 225 ifp->if_watchdog = enet_watchdog; 226 227 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 228 #ifdef ENET_SUPPORT_JUMBO 229 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 230 #endif 231 232 ifp->if_capabilities = IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 233 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | 234 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 235 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx | 236 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 237 238 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(ENET_TX_RING_CNT, IFQ_MAXLEN)); 239 IFQ_SET_READY(&ifp->if_snd); 240 241 /* setup MII */ 242 sc->sc_ethercom.ec_mii = mii; 243 mii->mii_ifp = ifp; 244 mii->mii_readreg = enet_miibus_readreg; 245 mii->mii_writereg = enet_miibus_writereg; 246 mii->mii_statchg = enet_miibus_statchg; 247 ifmedia_init(&mii->mii_media, 0, ether_mediachange, enet_mediastatus); 248 249 /* try to attach PHY */ 250 mii_attach(self, mii, 0xffffffff, sc->sc_phyid, MII_OFFSET_ANY, 0); 251 if (LIST_FIRST(&mii->mii_phys) == NULL) { 252 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 253 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 254 } else { 255 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 256 } 257 258 if_attach(ifp); 259 ether_ifattach(ifp, sc->sc_enaddr); 260 ether_set_ifflags_cb(&sc->sc_ethercom, enet_ifflags_cb); 261 262 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 263 RND_TYPE_NET, RND_FLAG_DEFAULT); 264 265 #ifdef ENET_EVENT_COUNTER 266 enet_attach_evcnt(sc); 267 #endif 268 269 sc->sc_stopping = false; 270 271 return 0; 272 } 273 274 #ifdef ENET_EVENT_COUNTER 275 static void 276 enet_attach_evcnt(struct enet_softc *sc) 277 { 278 const char *xname; 279 280 xname = device_xname(sc->sc_dev); 281 282 #define ENET_EVCNT_ATTACH(name) \ 283 evcnt_attach_dynamic(&sc->sc_ev_ ## name, EVCNT_TYPE_MISC, \ 284 NULL, xname, #name); 285 286 ENET_EVCNT_ATTACH(t_drop); 287 ENET_EVCNT_ATTACH(t_packets); 288 ENET_EVCNT_ATTACH(t_bc_pkt); 289 ENET_EVCNT_ATTACH(t_mc_pkt); 290 ENET_EVCNT_ATTACH(t_crc_align); 291 ENET_EVCNT_ATTACH(t_undersize); 292 ENET_EVCNT_ATTACH(t_oversize); 293 ENET_EVCNT_ATTACH(t_frag); 294 ENET_EVCNT_ATTACH(t_jab); 295 ENET_EVCNT_ATTACH(t_col); 296 ENET_EVCNT_ATTACH(t_p64); 297 ENET_EVCNT_ATTACH(t_p65to127n); 298 ENET_EVCNT_ATTACH(t_p128to255n); 299 ENET_EVCNT_ATTACH(t_p256to511); 300 ENET_EVCNT_ATTACH(t_p512to1023); 301 ENET_EVCNT_ATTACH(t_p1024to2047); 302 ENET_EVCNT_ATTACH(t_p_gte2048); 303 ENET_EVCNT_ATTACH(t_octets); 304 ENET_EVCNT_ATTACH(r_packets); 305 ENET_EVCNT_ATTACH(r_bc_pkt); 306 ENET_EVCNT_ATTACH(r_mc_pkt); 307 ENET_EVCNT_ATTACH(r_crc_align); 308 ENET_EVCNT_ATTACH(r_undersize); 309 ENET_EVCNT_ATTACH(r_oversize); 310 ENET_EVCNT_ATTACH(r_frag); 311 ENET_EVCNT_ATTACH(r_jab); 312 ENET_EVCNT_ATTACH(r_p64); 313 ENET_EVCNT_ATTACH(r_p65to127); 314 ENET_EVCNT_ATTACH(r_p128to255); 315 ENET_EVCNT_ATTACH(r_p256to511); 316 ENET_EVCNT_ATTACH(r_p512to1023); 317 ENET_EVCNT_ATTACH(r_p1024to2047); 318 ENET_EVCNT_ATTACH(r_p_gte2048); 319 ENET_EVCNT_ATTACH(r_octets); 320 } 321 322 static void 323 enet_update_evcnt(struct enet_softc *sc) 324 { 325 sc->sc_ev_t_drop.ev_count += ENET_REG_READ(sc, ENET_RMON_T_DROP); 326 sc->sc_ev_t_packets.ev_count += ENET_REG_READ(sc, ENET_RMON_T_PACKETS); 327 sc->sc_ev_t_bc_pkt.ev_count += ENET_REG_READ(sc, ENET_RMON_T_BC_PKT); 328 sc->sc_ev_t_mc_pkt.ev_count += ENET_REG_READ(sc, ENET_RMON_T_MC_PKT); 329 sc->sc_ev_t_crc_align.ev_count += ENET_REG_READ(sc, ENET_RMON_T_CRC_ALIGN); 330 sc->sc_ev_t_undersize.ev_count += ENET_REG_READ(sc, ENET_RMON_T_UNDERSIZE); 331 sc->sc_ev_t_oversize.ev_count += ENET_REG_READ(sc, ENET_RMON_T_OVERSIZE); 332 sc->sc_ev_t_frag.ev_count += ENET_REG_READ(sc, ENET_RMON_T_FRAG); 333 sc->sc_ev_t_jab.ev_count += ENET_REG_READ(sc, ENET_RMON_T_JAB); 334 sc->sc_ev_t_col.ev_count += ENET_REG_READ(sc, ENET_RMON_T_COL); 335 sc->sc_ev_t_p64.ev_count += ENET_REG_READ(sc, ENET_RMON_T_P64); 336 sc->sc_ev_t_p65to127n.ev_count += ENET_REG_READ(sc, ENET_RMON_T_P65TO127N); 337 sc->sc_ev_t_p128to255n.ev_count += ENET_REG_READ(sc, ENET_RMON_T_P128TO255N); 338 sc->sc_ev_t_p256to511.ev_count += ENET_REG_READ(sc, ENET_RMON_T_P256TO511); 339 sc->sc_ev_t_p512to1023.ev_count += ENET_REG_READ(sc, ENET_RMON_T_P512TO1023); 340 sc->sc_ev_t_p1024to2047.ev_count += ENET_REG_READ(sc, ENET_RMON_T_P1024TO2047); 341 sc->sc_ev_t_p_gte2048.ev_count += ENET_REG_READ(sc, ENET_RMON_T_P_GTE2048); 342 sc->sc_ev_t_octets.ev_count += ENET_REG_READ(sc, ENET_RMON_T_OCTETS); 343 sc->sc_ev_r_packets.ev_count += ENET_REG_READ(sc, ENET_RMON_R_PACKETS); 344 sc->sc_ev_r_bc_pkt.ev_count += ENET_REG_READ(sc, ENET_RMON_R_BC_PKT); 345 sc->sc_ev_r_mc_pkt.ev_count += ENET_REG_READ(sc, ENET_RMON_R_MC_PKT); 346 sc->sc_ev_r_crc_align.ev_count += ENET_REG_READ(sc, ENET_RMON_R_CRC_ALIGN); 347 sc->sc_ev_r_undersize.ev_count += ENET_REG_READ(sc, ENET_RMON_R_UNDERSIZE); 348 sc->sc_ev_r_oversize.ev_count += ENET_REG_READ(sc, ENET_RMON_R_OVERSIZE); 349 sc->sc_ev_r_frag.ev_count += ENET_REG_READ(sc, ENET_RMON_R_FRAG); 350 sc->sc_ev_r_jab.ev_count += ENET_REG_READ(sc, ENET_RMON_R_JAB); 351 sc->sc_ev_r_p64.ev_count += ENET_REG_READ(sc, ENET_RMON_R_P64); 352 sc->sc_ev_r_p65to127.ev_count += ENET_REG_READ(sc, ENET_RMON_R_P65TO127); 353 sc->sc_ev_r_p128to255.ev_count += ENET_REG_READ(sc, ENET_RMON_R_P128TO255); 354 sc->sc_ev_r_p256to511.ev_count += ENET_REG_READ(sc, ENET_RMON_R_P256TO511); 355 sc->sc_ev_r_p512to1023.ev_count += ENET_REG_READ(sc, ENET_RMON_R_P512TO1023); 356 sc->sc_ev_r_p1024to2047.ev_count += ENET_REG_READ(sc, ENET_RMON_R_P1024TO2047); 357 sc->sc_ev_r_p_gte2048.ev_count += ENET_REG_READ(sc, ENET_RMON_R_P_GTE2048); 358 sc->sc_ev_r_octets.ev_count += ENET_REG_READ(sc, ENET_RMON_R_OCTETS); 359 } 360 #endif /* ENET_EVENT_COUNTER */ 361 362 static void 363 enet_tick(void *arg) 364 { 365 struct enet_softc *sc; 366 struct mii_data *mii; 367 struct ifnet *ifp; 368 int s; 369 370 sc = arg; 371 mii = &sc->sc_mii; 372 ifp = &sc->sc_ethercom.ec_if; 373 374 s = splnet(); 375 376 if (sc->sc_stopping) 377 goto out; 378 379 #ifdef ENET_EVENT_COUNTER 380 enet_update_evcnt(sc); 381 #endif 382 383 /* update counters */ 384 if_statadd(ifp, if_ierrors, 385 (uint64_t)ENET_REG_READ(sc, ENET_RMON_R_UNDERSIZE) + 386 (uint64_t)ENET_REG_READ(sc, ENET_RMON_R_FRAG) + 387 (uint64_t)ENET_REG_READ(sc, ENET_RMON_R_JAB)); 388 389 /* clear counters */ 390 ENET_REG_WRITE(sc, ENET_MIBC, ENET_MIBC_MIB_CLEAR); 391 ENET_REG_WRITE(sc, ENET_MIBC, 0); 392 393 mii_tick(mii); 394 out: 395 396 if (!sc->sc_stopping) 397 callout_schedule(&sc->sc_tick_ch, ENET_TICK); 398 399 splx(s); 400 } 401 402 int 403 enet_intr(void *arg) 404 { 405 struct enet_softc *sc; 406 struct ifnet *ifp; 407 uint32_t status; 408 409 sc = arg; 410 status = ENET_REG_READ(sc, ENET_EIR); 411 412 if (sc->sc_imxtype == 7) { 413 if (status & (ENET_EIR_TXF | ENET_EIR_TXF1 | ENET_EIR_TXF2)) 414 enet_tx_intr(arg); 415 if (status & (ENET_EIR_RXF | ENET_EIR_RXF1 | ENET_EIR_RXF2)) 416 enet_rx_intr(arg); 417 } else { 418 if (status & ENET_EIR_TXF) 419 enet_tx_intr(arg); 420 if (status & ENET_EIR_RXF) 421 enet_rx_intr(arg); 422 } 423 424 if (status & ENET_EIR_EBERR) { 425 device_printf(sc->sc_dev, "Ethernet Bus Error\n"); 426 ifp = &sc->sc_ethercom.ec_if; 427 enet_stop(ifp, 1); 428 enet_init(ifp); 429 } else { 430 ENET_REG_WRITE(sc, ENET_EIR, status); 431 } 432 433 rnd_add_uint32(&sc->sc_rnd_source, status); 434 435 return 1; 436 } 437 438 static int 439 enet_tx_intr(void *arg) 440 { 441 struct enet_softc *sc; 442 struct ifnet *ifp; 443 struct enet_txsoft *txs; 444 int idx; 445 446 sc = (struct enet_softc *)arg; 447 ifp = &sc->sc_ethercom.ec_if; 448 449 for (idx = sc->sc_tx_considx; idx != sc->sc_tx_prodidx; 450 idx = ENET_TX_NEXTIDX(idx)) { 451 452 txs = &sc->sc_txsoft[idx]; 453 454 TXDESC_READIN(idx); 455 if (sc->sc_txdesc_ring[idx].tx_flags1_len & TXFLAGS1_R) { 456 /* This TX Descriptor has not been transmitted yet */ 457 break; 458 } 459 460 /* txsoft is available on first segment (TXFLAGS1_T1) */ 461 if (sc->sc_txdesc_ring[idx].tx_flags1_len & TXFLAGS1_T1) { 462 bus_dmamap_unload(sc->sc_dmat, 463 txs->txs_dmamap); 464 m_freem(txs->txs_mbuf); 465 if_statinc(ifp, if_opackets); 466 } 467 468 /* checking error */ 469 if (sc->sc_txdesc_ring[idx].tx_flags1_len & TXFLAGS1_L) { 470 uint32_t flags2; 471 472 flags2 = sc->sc_txdesc_ring[idx].tx_flags2; 473 474 if (flags2 & (TXFLAGS2_TXE | 475 TXFLAGS2_UE | TXFLAGS2_EE | TXFLAGS2_FE | 476 TXFLAGS2_LCE | TXFLAGS2_OE | TXFLAGS2_TSE)) { 477 #ifdef DEBUG_ENET 478 if (enet_debug) { 479 char flagsbuf[128]; 480 481 snprintb(flagsbuf, sizeof(flagsbuf), 482 "\20" "\20TRANSMIT" "\16UNDERFLOW" 483 "\15COLLISION" "\14FRAME" 484 "\13LATECOLLISION" "\12OVERFLOW", 485 flags2); 486 487 device_printf(sc->sc_dev, 488 "txdesc[%d]: transmit error: " 489 "flags2=%s\n", idx, flagsbuf); 490 } 491 #endif /* DEBUG_ENET */ 492 if_statinc(ifp, if_oerrors); 493 } 494 } 495 496 sc->sc_tx_free++; 497 } 498 sc->sc_tx_considx = idx; 499 500 if (sc->sc_tx_free > 0) 501 sc->sc_txbusy = false; 502 503 /* 504 * No more pending TX descriptor, 505 * cancel the watchdog timer. 506 */ 507 if (sc->sc_tx_free == ENET_TX_RING_CNT) 508 ifp->if_timer = 0; 509 510 return 1; 511 } 512 513 static int 514 enet_rx_intr(void *arg) 515 { 516 struct enet_softc *sc; 517 struct ifnet *ifp; 518 struct enet_rxsoft *rxs; 519 int idx, len, amount; 520 uint32_t flags1, flags2; 521 struct mbuf *m, *m0, *mprev; 522 523 sc = arg; 524 ifp = &sc->sc_ethercom.ec_if; 525 526 m0 = mprev = NULL; 527 amount = 0; 528 for (idx = sc->sc_rx_readidx; ; idx = ENET_RX_NEXTIDX(idx)) { 529 530 rxs = &sc->sc_rxsoft[idx]; 531 532 RXDESC_READIN(idx); 533 if (sc->sc_rxdesc_ring[idx].rx_flags1_len & RXFLAGS1_E) { 534 /* This RX Descriptor has not been received yet */ 535 break; 536 } 537 538 /* 539 * build mbuf from RX Descriptor if needed 540 */ 541 m = rxs->rxs_mbuf; 542 rxs->rxs_mbuf = NULL; 543 544 flags1 = sc->sc_rxdesc_ring[idx].rx_flags1_len; 545 len = RXFLAGS1_LEN(flags1); 546 547 #define RACC_SHIFT16 2 548 if (m0 == NULL) { 549 m0 = m; 550 m_adj(m0, RACC_SHIFT16); 551 len -= RACC_SHIFT16; 552 m->m_len = len; 553 amount = len; 554 } else { 555 if (flags1 & RXFLAGS1_L) 556 len = len - amount - RACC_SHIFT16; 557 558 m->m_len = len; 559 amount += len; 560 if (m->m_flags & M_PKTHDR) 561 m_remove_pkthdr(m); 562 mprev->m_next = m; 563 } 564 mprev = m; 565 566 flags2 = sc->sc_rxdesc_ring[idx].rx_flags2; 567 568 if (flags1 & RXFLAGS1_L) { 569 /* last buffer */ 570 if ((amount < ETHER_HDR_LEN) || 571 ((flags1 & (RXFLAGS1_LG | RXFLAGS1_NO | 572 RXFLAGS1_CR | RXFLAGS1_OV | RXFLAGS1_TR)) || 573 (flags2 & (RXFLAGS2_ME | RXFLAGS2_PE | 574 RXFLAGS2_CE)))) { 575 576 #ifdef DEBUG_ENET 577 if (enet_debug) { 578 char flags1buf[128], flags2buf[128]; 579 snprintb(flags1buf, sizeof(flags1buf), 580 "\20" "\31MISS" "\26LENGTHVIOLATION" 581 "\25NONOCTET" "\23CRC" "\22OVERRUN" 582 "\21TRUNCATED", flags1); 583 snprintb(flags2buf, sizeof(flags2buf), 584 "\20" "\40MAC" "\33PHY" 585 "\32COLLISION", flags2); 586 587 DEVICE_DPRINTF( 588 "rxdesc[%d]: receive error: " 589 "flags1=%s,flags2=%s,len=%d\n", 590 idx, flags1buf, flags2buf, amount); 591 } 592 #endif /* DEBUG_ENET */ 593 if_statinc(ifp, if_ierrors); 594 m_freem(m0); 595 596 } else { 597 /* packet receive ok */ 598 m_set_rcvif(m0, ifp); 599 m0->m_pkthdr.len = amount; 600 601 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 602 rxs->rxs_dmamap->dm_mapsize, 603 BUS_DMASYNC_PREREAD); 604 605 if (ifp->if_csum_flags_rx & (M_CSUM_IPv4 | 606 M_CSUM_TCPv4 | M_CSUM_UDPv4 | 607 M_CSUM_TCPv6 | M_CSUM_UDPv6)) 608 enet_rx_csum(sc, ifp, m0, idx); 609 610 if_percpuq_enqueue(ifp->if_percpuq, m0); 611 } 612 613 m0 = NULL; 614 mprev = NULL; 615 amount = 0; 616 617 } else { 618 /* continued from previous buffer */ 619 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 620 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 621 } 622 623 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 624 if (enet_alloc_rxbuf(sc, idx) != 0) { 625 panic("enet_alloc_rxbuf NULL\n"); 626 } 627 } 628 sc->sc_rx_readidx = idx; 629 630 /* re-enable RX DMA to make sure */ 631 ENET_REG_WRITE(sc, ENET_RDAR, ENET_RDAR_ACTIVE); 632 633 return 1; 634 } 635 636 static void 637 enet_rx_csum(struct enet_softc *sc, struct ifnet *ifp, struct mbuf *m, int idx) 638 { 639 uint32_t flags2; 640 uint8_t proto; 641 642 flags2 = sc->sc_rxdesc_ring[idx].rx_flags2; 643 644 if (flags2 & RXFLAGS2_IPV6) { 645 proto = sc->sc_rxdesc_ring[idx].rx_proto; 646 647 /* RXFLAGS2_PCR is valid when IPv6 and TCP/UDP */ 648 if ((proto == IPPROTO_TCP) && 649 (ifp->if_csum_flags_rx & M_CSUM_TCPv6)) 650 m->m_pkthdr.csum_flags |= M_CSUM_TCPv6; 651 else if ((proto == IPPROTO_UDP) && 652 (ifp->if_csum_flags_rx & M_CSUM_UDPv6)) 653 m->m_pkthdr.csum_flags |= M_CSUM_UDPv6; 654 else 655 return; 656 657 /* IPv6 protocol checksum error */ 658 if (flags2 & RXFLAGS2_PCR) 659 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 660 661 } else { 662 struct ether_header *eh; 663 uint8_t *ip; 664 665 eh = mtod(m, struct ether_header *); 666 667 /* XXX: is an IPv4? */ 668 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 669 return; 670 ip = (uint8_t *)(eh + 1); 671 if ((ip[0] & 0xf0) == 0x40) 672 return; 673 674 proto = sc->sc_rxdesc_ring[idx].rx_proto; 675 if (flags2 & RXFLAGS2_ICE) { 676 if (ifp->if_csum_flags_rx & M_CSUM_IPv4) { 677 m->m_pkthdr.csum_flags |= 678 M_CSUM_IPv4 | M_CSUM_IPv4_BAD; 679 } 680 } else { 681 if (ifp->if_csum_flags_rx & M_CSUM_IPv4) { 682 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 683 } 684 685 /* 686 * PCR is valid when 687 * ICE == 0 and FRAG == 0 688 */ 689 if (flags2 & RXFLAGS2_FRAG) 690 return; 691 692 /* 693 * PCR is valid when proto is TCP or UDP 694 */ 695 if ((proto == IPPROTO_TCP) && 696 (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 697 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 698 else if ((proto == IPPROTO_UDP) && 699 (ifp->if_csum_flags_rx & M_CSUM_UDPv4)) 700 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 701 else 702 return; 703 704 /* IPv4 protocol cksum error */ 705 if (flags2 & RXFLAGS2_PCR) 706 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 707 } 708 } 709 } 710 711 static void 712 enet_setmulti(struct enet_softc *sc) 713 { 714 struct ethercom *ec = &sc->sc_ethercom; 715 struct ifnet *ifp = &ec->ec_if; 716 struct ether_multi *enm; 717 struct ether_multistep step; 718 uint32_t crc, hashidx; 719 uint32_t gaddr[2]; 720 721 if (ifp->if_flags & IFF_PROMISC) { 722 /* receive all unicast packet */ 723 ENET_REG_WRITE(sc, ENET_IAUR, 0xffffffff); 724 ENET_REG_WRITE(sc, ENET_IALR, 0xffffffff); 725 /* receive all multicast packet */ 726 gaddr[0] = gaddr[1] = 0xffffffff; 727 } else { 728 gaddr[0] = gaddr[1] = 0; 729 730 ETHER_LOCK(ec); 731 ETHER_FIRST_MULTI(step, ec, enm); 732 while (enm != NULL) { 733 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 734 ETHER_ADDR_LEN)) { 735 /* 736 * if specified by range, give up setting hash, 737 * and fallback to allmulti. 738 */ 739 gaddr[0] = gaddr[1] = 0xffffffff; 740 break; 741 } 742 743 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 744 hashidx = __SHIFTOUT(crc, __BITS(30,26)); 745 gaddr[__SHIFTOUT(crc, __BIT(31))] |= __BIT(hashidx); 746 747 ETHER_NEXT_MULTI(step, enm); 748 } 749 ETHER_UNLOCK(ec); 750 751 /* dont't receive any unicast packet (except own address) */ 752 ENET_REG_WRITE(sc, ENET_IAUR, 0); 753 ENET_REG_WRITE(sc, ENET_IALR, 0); 754 } 755 756 if (gaddr[0] == 0xffffffff && gaddr[1] == 0xffffffff) 757 ifp->if_flags |= IFF_ALLMULTI; 758 else 759 ifp->if_flags &= ~IFF_ALLMULTI; 760 761 /* receive multicast packets according to multicast filter */ 762 ENET_REG_WRITE(sc, ENET_GAUR, gaddr[1]); 763 ENET_REG_WRITE(sc, ENET_GALR, gaddr[0]); 764 765 } 766 767 static void 768 enet_gethwaddr(struct enet_softc *sc, uint8_t *hwaddr) 769 { 770 uint32_t paddr; 771 772 paddr = ENET_REG_READ(sc, ENET_PALR); 773 hwaddr[0] = paddr >> 24; 774 hwaddr[1] = paddr >> 16; 775 hwaddr[2] = paddr >> 8; 776 hwaddr[3] = paddr; 777 778 paddr = ENET_REG_READ(sc, ENET_PAUR); 779 hwaddr[4] = paddr >> 24; 780 hwaddr[5] = paddr >> 16; 781 } 782 783 static void 784 enet_sethwaddr(struct enet_softc *sc, uint8_t *hwaddr) 785 { 786 uint32_t paddr; 787 788 paddr = (hwaddr[0] << 24) | (hwaddr[1] << 16) | (hwaddr[2] << 8) | 789 hwaddr[3]; 790 ENET_REG_WRITE(sc, ENET_PALR, paddr); 791 paddr = (hwaddr[4] << 24) | (hwaddr[5] << 16); 792 ENET_REG_WRITE(sc, ENET_PAUR, paddr); 793 } 794 795 /* 796 * ifnet interfaces 797 */ 798 static int 799 enet_init(struct ifnet *ifp) 800 { 801 struct enet_softc *sc; 802 int s, error; 803 804 sc = ifp->if_softc; 805 806 s = splnet(); 807 808 enet_init_regs(sc, 0); 809 enet_init_txring(sc); 810 error = enet_init_rxring(sc); 811 if (error != 0) { 812 enet_drain_rxbuf(sc); 813 device_printf(sc->sc_dev, "Cannot allocate mbuf cluster\n"); 814 goto init_failure; 815 } 816 817 /* reload mac address */ 818 memcpy(sc->sc_enaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 819 enet_sethwaddr(sc, sc->sc_enaddr); 820 821 /* program multicast address */ 822 enet_setmulti(sc); 823 824 /* update if_flags */ 825 ifp->if_flags |= IFF_RUNNING; 826 sc->sc_txbusy = false; 827 828 /* update local copy of if_flags */ 829 sc->sc_if_flags = ifp->if_flags; 830 831 /* mii */ 832 mii_mediachg(&sc->sc_mii); 833 834 /* enable RX DMA */ 835 ENET_REG_WRITE(sc, ENET_RDAR, ENET_RDAR_ACTIVE); 836 837 sc->sc_stopping = false; 838 callout_schedule(&sc->sc_tick_ch, ENET_TICK); 839 840 init_failure: 841 splx(s); 842 843 return error; 844 } 845 846 static void 847 enet_start(struct ifnet *ifp) 848 { 849 struct enet_softc *sc; 850 struct mbuf *m; 851 int npkt; 852 853 if ((ifp->if_flags & IFF_RUNNING) == 0) 854 return; 855 856 sc = ifp->if_softc; 857 for (npkt = 0; !sc->sc_txbusy; npkt++) { 858 IFQ_POLL(&ifp->if_snd, m); 859 if (m == NULL) 860 break; 861 862 if (sc->sc_tx_free <= 0) { 863 /* no tx descriptor now... */ 864 sc->sc_txbusy = true; 865 DEVICE_DPRINTF("TX descriptor is full\n"); 866 break; 867 } 868 869 IFQ_DEQUEUE(&ifp->if_snd, m); 870 871 if (enet_encap_txring(sc, &m) != 0) { 872 /* too many mbuf chains? */ 873 sc->sc_txbusy = true; 874 DEVICE_DPRINTF( 875 "TX descriptor is full. dropping packet\n"); 876 m_freem(m); 877 if_statinc(ifp, if_oerrors); 878 break; 879 } 880 881 /* Pass the packet to any BPF listeners */ 882 bpf_mtap(ifp, m, BPF_D_OUT); 883 } 884 885 if (npkt) { 886 /* enable TX DMA */ 887 ENET_REG_WRITE(sc, ENET_TDAR, ENET_TDAR_ACTIVE); 888 889 ifp->if_timer = 5; 890 } 891 } 892 893 static void 894 enet_stop(struct ifnet *ifp, int disable) 895 { 896 struct enet_softc *sc; 897 int s; 898 uint32_t v; 899 900 sc = ifp->if_softc; 901 902 s = splnet(); 903 904 sc->sc_stopping = true; 905 callout_stop(&sc->sc_tick_ch); 906 907 /* clear ENET_ECR[ETHEREN] to abort receive and transmit */ 908 v = ENET_REG_READ(sc, ENET_ECR); 909 ENET_REG_WRITE(sc, ENET_ECR, v & ~ENET_ECR_ETHEREN); 910 911 /* Mark the interface as down and cancel the watchdog timer. */ 912 ifp->if_flags &= ~IFF_RUNNING; 913 ifp->if_timer = 0; 914 sc->sc_txbusy = false; 915 916 if (disable) { 917 enet_drain_txbuf(sc); 918 enet_drain_rxbuf(sc); 919 } 920 921 splx(s); 922 } 923 924 static void 925 enet_watchdog(struct ifnet *ifp) 926 { 927 struct enet_softc *sc; 928 int s; 929 930 sc = ifp->if_softc; 931 s = splnet(); 932 933 device_printf(sc->sc_dev, "watchdog timeout\n"); 934 if_statinc(ifp, if_oerrors); 935 936 /* salvage packets left in descriptors */ 937 enet_tx_intr(sc); 938 enet_rx_intr(sc); 939 940 /* reset */ 941 enet_stop(ifp, 1); 942 enet_init(ifp); 943 944 splx(s); 945 } 946 947 static void 948 enet_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 949 { 950 struct enet_softc *sc = ifp->if_softc; 951 952 ether_mediastatus(ifp, ifmr); 953 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) 954 | sc->sc_flowflags; 955 } 956 957 static int 958 enet_ifflags_cb(struct ethercom *ec) 959 { 960 struct ifnet *ifp = &ec->ec_if; 961 struct enet_softc *sc = ifp->if_softc; 962 u_short change = ifp->if_flags ^ sc->sc_if_flags; 963 964 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 965 return ENETRESET; 966 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 967 return 0; 968 969 enet_setmulti(sc); 970 971 sc->sc_if_flags = ifp->if_flags; 972 return 0; 973 } 974 975 static int 976 enet_ioctl(struct ifnet *ifp, u_long command, void *data) 977 { 978 struct enet_softc *sc; 979 struct ifreq *ifr; 980 int s, error; 981 uint32_t v; 982 983 sc = ifp->if_softc; 984 ifr = data; 985 986 error = 0; 987 988 s = splnet(); 989 990 switch (command) { 991 case SIOCSIFMTU: 992 if (MTU2FRAMESIZE(ifr->ifr_mtu) > ENET_MAX_PKT_LEN) { 993 error = EINVAL; 994 } else { 995 ifp->if_mtu = ifr->ifr_mtu; 996 997 /* set maximum frame length */ 998 v = MTU2FRAMESIZE(ifr->ifr_mtu); 999 ENET_REG_WRITE(sc, ENET_FTRL, v); 1000 v = ENET_REG_READ(sc, ENET_RCR); 1001 v &= ~ENET_RCR_MAX_FL(0x3fff); 1002 v |= ENET_RCR_MAX_FL(ifp->if_mtu + ETHER_HDR_LEN + 1003 ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 1004 ENET_REG_WRITE(sc, ENET_RCR, v); 1005 } 1006 break; 1007 case SIOCSIFMEDIA: 1008 /* Flow control requires full-duplex mode. */ 1009 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1010 (ifr->ifr_media & IFM_FDX) == 0) 1011 ifr->ifr_media &= ~IFM_ETH_FMASK; 1012 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1013 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1014 /* We can do both TXPAUSE and RXPAUSE. */ 1015 ifr->ifr_media |= 1016 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1017 } 1018 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1019 } 1020 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1021 break; 1022 default: 1023 error = ether_ioctl(ifp, command, data); 1024 if (error != ENETRESET) 1025 break; 1026 1027 /* post-process */ 1028 error = 0; 1029 switch (command) { 1030 case SIOCSIFCAP: 1031 error = if_init(ifp); 1032 break; 1033 case SIOCADDMULTI: 1034 case SIOCDELMULTI: 1035 if (ifp->if_flags & IFF_RUNNING) 1036 enet_setmulti(sc); 1037 break; 1038 } 1039 break; 1040 } 1041 1042 splx(s); 1043 1044 return error; 1045 } 1046 1047 /* 1048 * for MII 1049 */ 1050 static int 1051 enet_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 1052 { 1053 struct enet_softc *sc; 1054 int timeout; 1055 uint32_t status; 1056 1057 sc = device_private(dev); 1058 1059 /* clear MII update */ 1060 ENET_REG_WRITE(sc, ENET_EIR, ENET_EIR_MII); 1061 1062 /* read command */ 1063 ENET_REG_WRITE(sc, ENET_MMFR, 1064 ENET_MMFR_ST | ENET_MMFR_OP_READ | ENET_MMFR_TA | 1065 ENET_MMFR_PHY_REG(reg) | ENET_MMFR_PHY_ADDR(phy)); 1066 1067 /* check MII update */ 1068 for (timeout = 5000; timeout > 0; --timeout) { 1069 status = ENET_REG_READ(sc, ENET_EIR); 1070 if (status & ENET_EIR_MII) 1071 break; 1072 } 1073 if (timeout <= 0) { 1074 DEVICE_DPRINTF("MII read timeout: reg=0x%02x\n", 1075 reg); 1076 return ETIMEDOUT; 1077 } else 1078 *val = ENET_REG_READ(sc, ENET_MMFR) & ENET_MMFR_DATAMASK; 1079 1080 return 0; 1081 } 1082 1083 static int 1084 enet_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 1085 { 1086 struct enet_softc *sc; 1087 int timeout; 1088 1089 sc = device_private(dev); 1090 1091 /* clear MII update */ 1092 ENET_REG_WRITE(sc, ENET_EIR, ENET_EIR_MII); 1093 1094 /* write command */ 1095 ENET_REG_WRITE(sc, ENET_MMFR, 1096 ENET_MMFR_ST | ENET_MMFR_OP_WRITE | ENET_MMFR_TA | 1097 ENET_MMFR_PHY_REG(reg) | ENET_MMFR_PHY_ADDR(phy) | 1098 (ENET_MMFR_DATAMASK & val)); 1099 1100 /* check MII update */ 1101 for (timeout = 5000; timeout > 0; --timeout) { 1102 if (ENET_REG_READ(sc, ENET_EIR) & ENET_EIR_MII) 1103 break; 1104 } 1105 if (timeout <= 0) { 1106 DEVICE_DPRINTF("MII write timeout: reg=0x%02x\n", reg); 1107 return ETIMEDOUT; 1108 } 1109 1110 return 0; 1111 } 1112 1113 static void 1114 enet_miibus_statchg(struct ifnet *ifp) 1115 { 1116 struct enet_softc *sc; 1117 struct mii_data *mii; 1118 struct ifmedia_entry *ife; 1119 uint32_t ecr, ecr0; 1120 uint32_t rcr, rcr0; 1121 uint32_t tcr, tcr0; 1122 1123 sc = ifp->if_softc; 1124 mii = &sc->sc_mii; 1125 ife = mii->mii_media.ifm_cur; 1126 1127 /* get current status */ 1128 ecr0 = ecr = ENET_REG_READ(sc, ENET_ECR) & ~ENET_ECR_RESET; 1129 rcr0 = rcr = ENET_REG_READ(sc, ENET_RCR); 1130 tcr0 = tcr = ENET_REG_READ(sc, ENET_TCR); 1131 1132 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1133 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 1134 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1135 mii->mii_media_active &= ~IFM_ETH_FMASK; 1136 } 1137 1138 if ((ife->ifm_media & IFM_FDX) != 0) { 1139 tcr |= ENET_TCR_FDEN; /* full duplex */ 1140 rcr &= ~ENET_RCR_DRT; /* enable receive on transmit */ 1141 } else { 1142 tcr &= ~ENET_TCR_FDEN; /* half duplex */ 1143 rcr |= ENET_RCR_DRT; /* disable receive on transmit */ 1144 } 1145 1146 if ((tcr ^ tcr0) & ENET_TCR_FDEN) { 1147 /* 1148 * need to reset because 1149 * FDEN can change when ECR[ETHEREN] is 0 1150 */ 1151 enet_init_regs(sc, 0); 1152 return; 1153 } 1154 1155 switch (IFM_SUBTYPE(ife->ifm_media)) { 1156 case IFM_AUTO: 1157 case IFM_1000_T: 1158 ecr |= ENET_ECR_SPEED; /* 1000Mbps mode */ 1159 rcr &= ~ENET_RCR_RMII_10T; 1160 break; 1161 case IFM_100_TX: 1162 ecr &= ~ENET_ECR_SPEED; /* 100Mbps mode */ 1163 rcr &= ~ENET_RCR_RMII_10T; /* 100Mbps mode */ 1164 break; 1165 case IFM_10_T: 1166 ecr &= ~ENET_ECR_SPEED; /* 10Mbps mode */ 1167 rcr |= ENET_RCR_RMII_10T; /* 10Mbps mode */ 1168 break; 1169 default: 1170 ecr = ecr0; 1171 rcr = rcr0; 1172 tcr = tcr0; 1173 break; 1174 } 1175 1176 if (sc->sc_rgmii == 0) 1177 ecr &= ~ENET_ECR_SPEED; 1178 1179 if (sc->sc_flowflags & IFM_FLOW) 1180 rcr |= ENET_RCR_FCE; 1181 else 1182 rcr &= ~ENET_RCR_FCE; 1183 1184 /* update registers if need change */ 1185 if (ecr != ecr0) 1186 ENET_REG_WRITE(sc, ENET_ECR, ecr); 1187 if (rcr != rcr0) 1188 ENET_REG_WRITE(sc, ENET_RCR, rcr); 1189 if (tcr != tcr0) 1190 ENET_REG_WRITE(sc, ENET_TCR, tcr); 1191 } 1192 1193 /* 1194 * handling descriptors 1195 */ 1196 static void 1197 enet_init_txring(struct enet_softc *sc) 1198 { 1199 int i; 1200 1201 /* build TX ring */ 1202 for (i = 0; i < ENET_TX_RING_CNT; i++) { 1203 sc->sc_txdesc_ring[i].tx_flags1_len = 1204 ((i == (ENET_TX_RING_CNT - 1)) ? TXFLAGS1_W : 0); 1205 sc->sc_txdesc_ring[i].tx_databuf = 0; 1206 sc->sc_txdesc_ring[i].tx_flags2 = TXFLAGS2_INT; 1207 sc->sc_txdesc_ring[i].tx__reserved1 = 0; 1208 sc->sc_txdesc_ring[i].tx_flags3 = 0; 1209 sc->sc_txdesc_ring[i].tx_1588timestamp = 0; 1210 sc->sc_txdesc_ring[i].tx__reserved2 = 0; 1211 sc->sc_txdesc_ring[i].tx__reserved3 = 0; 1212 1213 TXDESC_WRITEOUT(i); 1214 } 1215 1216 sc->sc_tx_free = ENET_TX_RING_CNT; 1217 sc->sc_tx_considx = 0; 1218 sc->sc_tx_prodidx = 0; 1219 } 1220 1221 static int 1222 enet_init_rxring(struct enet_softc *sc) 1223 { 1224 int i, error; 1225 1226 /* build RX ring */ 1227 for (i = 0; i < ENET_RX_RING_CNT; i++) { 1228 error = enet_alloc_rxbuf(sc, i); 1229 if (error != 0) 1230 return error; 1231 } 1232 1233 sc->sc_rx_readidx = 0; 1234 1235 return 0; 1236 } 1237 1238 static int 1239 enet_alloc_rxbuf(struct enet_softc *sc, int idx) 1240 { 1241 struct mbuf *m; 1242 int error; 1243 1244 KASSERT((idx >= 0) && (idx < ENET_RX_RING_CNT)); 1245 1246 /* free mbuf if already allocated */ 1247 if (sc->sc_rxsoft[idx].rxs_mbuf != NULL) { 1248 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxsoft[idx].rxs_dmamap); 1249 m_freem(sc->sc_rxsoft[idx].rxs_mbuf); 1250 sc->sc_rxsoft[idx].rxs_mbuf = NULL; 1251 } 1252 1253 /* allocate new mbuf cluster */ 1254 MGETHDR(m, M_DONTWAIT, MT_DATA); 1255 if (m == NULL) 1256 return ENOBUFS; 1257 MCLGET(m, M_DONTWAIT); 1258 if (!(m->m_flags & M_EXT)) { 1259 m_freem(m); 1260 return ENOBUFS; 1261 } 1262 m->m_len = MCLBYTES; 1263 m->m_next = NULL; 1264 1265 error = bus_dmamap_load(sc->sc_dmat, sc->sc_rxsoft[idx].rxs_dmamap, 1266 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1267 BUS_DMA_READ | BUS_DMA_NOWAIT); 1268 if (error) { 1269 m_freem(m); 1270 return error; 1271 } 1272 1273 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxsoft[idx].rxs_dmamap, 0, 1274 sc->sc_rxsoft[idx].rxs_dmamap->dm_mapsize, 1275 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1276 1277 sc->sc_rxsoft[idx].rxs_mbuf = m; 1278 enet_reset_rxdesc(sc, idx); 1279 return 0; 1280 } 1281 1282 static void 1283 enet_reset_rxdesc(struct enet_softc *sc, int idx) 1284 { 1285 uint32_t paddr; 1286 1287 paddr = sc->sc_rxsoft[idx].rxs_dmamap->dm_segs[0].ds_addr; 1288 1289 sc->sc_rxdesc_ring[idx].rx_flags1_len = 1290 RXFLAGS1_E | 1291 ((idx == (ENET_RX_RING_CNT - 1)) ? RXFLAGS1_W : 0); 1292 sc->sc_rxdesc_ring[idx].rx_databuf = paddr; 1293 sc->sc_rxdesc_ring[idx].rx_flags2 = 1294 RXFLAGS2_INT; 1295 sc->sc_rxdesc_ring[idx].rx_hl = 0; 1296 sc->sc_rxdesc_ring[idx].rx_proto = 0; 1297 sc->sc_rxdesc_ring[idx].rx_cksum = 0; 1298 sc->sc_rxdesc_ring[idx].rx_flags3 = 0; 1299 sc->sc_rxdesc_ring[idx].rx_1588timestamp = 0; 1300 sc->sc_rxdesc_ring[idx].rx__reserved2 = 0; 1301 sc->sc_rxdesc_ring[idx].rx__reserved3 = 0; 1302 1303 RXDESC_WRITEOUT(idx); 1304 } 1305 1306 static void 1307 enet_drain_txbuf(struct enet_softc *sc) 1308 { 1309 int idx; 1310 struct enet_txsoft *txs; 1311 struct ifnet *ifp; 1312 1313 ifp = &sc->sc_ethercom.ec_if; 1314 1315 for (idx = sc->sc_tx_considx; idx != sc->sc_tx_prodidx; 1316 idx = ENET_TX_NEXTIDX(idx)) { 1317 1318 /* txsoft[] is used only first segment */ 1319 txs = &sc->sc_txsoft[idx]; 1320 TXDESC_READIN(idx); 1321 if (sc->sc_txdesc_ring[idx].tx_flags1_len & TXFLAGS1_T1) { 1322 sc->sc_txdesc_ring[idx].tx_flags1_len = 0; 1323 bus_dmamap_unload(sc->sc_dmat, 1324 txs->txs_dmamap); 1325 m_freem(txs->txs_mbuf); 1326 1327 if_statinc(ifp, if_oerrors); 1328 } 1329 sc->sc_tx_free++; 1330 } 1331 } 1332 1333 static void 1334 enet_drain_rxbuf(struct enet_softc *sc) 1335 { 1336 int i; 1337 1338 for (i = 0; i < ENET_RX_RING_CNT; i++) { 1339 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) { 1340 sc->sc_rxdesc_ring[i].rx_flags1_len = 0; 1341 bus_dmamap_unload(sc->sc_dmat, 1342 sc->sc_rxsoft[i].rxs_dmamap); 1343 m_freem(sc->sc_rxsoft[i].rxs_mbuf); 1344 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1345 } 1346 } 1347 } 1348 1349 static int 1350 enet_alloc_ring(struct enet_softc *sc) 1351 { 1352 int i, error; 1353 1354 /* 1355 * build DMA maps for TX. 1356 * TX descriptor must be able to contain mbuf chains, 1357 * so, make up ENET_MAX_PKT_NSEGS dmamap. 1358 */ 1359 for (i = 0; i < ENET_TX_RING_CNT; i++) { 1360 error = bus_dmamap_create(sc->sc_dmat, ENET_MAX_PKT_LEN, 1361 ENET_MAX_PKT_NSEGS, ENET_MAX_PKT_LEN, 0, BUS_DMA_NOWAIT, 1362 &sc->sc_txsoft[i].txs_dmamap); 1363 1364 if (error) { 1365 aprint_error_dev(sc->sc_dev, 1366 "can't create DMA map for TX descs\n"); 1367 goto fail_1; 1368 } 1369 } 1370 1371 /* 1372 * build DMA maps for RX. 1373 * RX descripter contains An mbuf cluster, 1374 * and make up a dmamap. 1375 */ 1376 for (i = 0; i < ENET_RX_RING_CNT; i++) { 1377 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1378 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1379 &sc->sc_rxsoft[i].rxs_dmamap); 1380 if (error) { 1381 aprint_error_dev(sc->sc_dev, 1382 "can't create DMA map for RX descs\n"); 1383 goto fail_2; 1384 } 1385 } 1386 1387 if (enet_alloc_dma(sc, sizeof(struct enet_txdesc) * ENET_TX_RING_CNT, 1388 (void **)&(sc->sc_txdesc_ring), &(sc->sc_txdesc_dmamap)) != 0) 1389 return -1; 1390 memset(sc->sc_txdesc_ring, 0, 1391 sizeof(struct enet_txdesc) * ENET_TX_RING_CNT); 1392 1393 if (enet_alloc_dma(sc, sizeof(struct enet_rxdesc) * ENET_RX_RING_CNT, 1394 (void **)&(sc->sc_rxdesc_ring), &(sc->sc_rxdesc_dmamap)) != 0) 1395 return -1; 1396 memset(sc->sc_rxdesc_ring, 0, 1397 sizeof(struct enet_rxdesc) * ENET_RX_RING_CNT); 1398 1399 return 0; 1400 1401 fail_2: 1402 for (i = 0; i < ENET_RX_RING_CNT; i++) { 1403 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1404 bus_dmamap_destroy(sc->sc_dmat, 1405 sc->sc_rxsoft[i].rxs_dmamap); 1406 } 1407 fail_1: 1408 for (i = 0; i < ENET_TX_RING_CNT; i++) { 1409 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1410 bus_dmamap_destroy(sc->sc_dmat, 1411 sc->sc_txsoft[i].txs_dmamap); 1412 } 1413 return error; 1414 } 1415 1416 static int 1417 enet_encap_mbufalign(struct mbuf **mp) 1418 { 1419 struct mbuf *m, *m0, *mt, *p, *x; 1420 void *ap; 1421 uint32_t alignoff, chiplen; 1422 1423 /* 1424 * iMX6 SoC ethernet controller requires 1425 * address of buffer must aligned 8, and 1426 * length of buffer must be greater than 10 (first fragment only?) 1427 */ 1428 #define ALIGNBYTE 8 1429 #define MINBUFSIZE 10 1430 #define ALIGN_PTR(p, align) \ 1431 (void *)(((uintptr_t)(p) + ((align) - 1)) & -(align)) 1432 1433 m0 = *mp; 1434 mt = p = NULL; 1435 for (m = m0; m != NULL; m = m->m_next) { 1436 alignoff = (uintptr_t)m->m_data & (ALIGNBYTE - 1); 1437 if (m->m_len < (ALIGNBYTE * 2)) { 1438 /* 1439 * rearrange mbuf data aligned 1440 * 1441 * align 8 * * * * * 1442 * +0123456789abcdef0123456789abcdef0 1443 * FROM m->m_data[___________abcdefghijklmn_______] 1444 * 1445 * +0123456789abcdef0123456789abcdef0 1446 * TO m->m_data[________abcdefghijklm___________] or 1447 * m->m_data[________________abcdefghijklmn__] 1448 */ 1449 if ((alignoff != 0) && (m->m_len != 0)) { 1450 chiplen = ALIGNBYTE - alignoff; 1451 if (M_LEADINGSPACE(m) >= alignoff) { 1452 ap = m->m_data - alignoff; 1453 memmove(ap, m->m_data, m->m_len); 1454 m->m_data = ap; 1455 } else if (M_TRAILINGSPACE(m) >= chiplen) { 1456 ap = m->m_data + chiplen; 1457 memmove(ap, m->m_data, m->m_len); 1458 m->m_data = ap; 1459 } else { 1460 /* 1461 * no space to align data. (M_READONLY?) 1462 * allocate new mbuf aligned, 1463 * and copy to it. 1464 */ 1465 MGET(x, M_DONTWAIT, m->m_type); 1466 if (x == NULL) { 1467 m_freem(m); 1468 return ENOBUFS; 1469 } 1470 MCLAIM(x, m->m_owner); 1471 if (m->m_flags & M_PKTHDR) 1472 m_move_pkthdr(x, m); 1473 x->m_len = m->m_len; 1474 x->m_data = ALIGN_PTR(x->m_data, 1475 ALIGNBYTE); 1476 memcpy(mtod(x, void *), mtod(m, void *), 1477 m->m_len); 1478 p->m_next = x; 1479 x->m_next = m_free(m); 1480 m = x; 1481 } 1482 } 1483 1484 /* 1485 * fill 1st mbuf at least 10byte 1486 * 1487 * align 8 * * * * * 1488 * +0123456789abcdef0123456789abcdef0 1489 * FROM m->m_data[________abcde___________________] 1490 * m->m_data[__fg____________________________] 1491 * m->m_data[_________________hi_____________] 1492 * m->m_data[__________jk____________________] 1493 * m->m_data[____l___________________________] 1494 * 1495 * +0123456789abcdef0123456789abcdef0 1496 * TO m->m_data[________abcdefghij______________] 1497 * m->m_data[________________________________] 1498 * m->m_data[________________________________] 1499 * m->m_data[___________k____________________] 1500 * m->m_data[____l___________________________] 1501 */ 1502 if (mt == NULL) { 1503 mt = m; 1504 while (mt->m_len == 0) { 1505 mt = mt->m_next; 1506 if (mt == NULL) { 1507 m_freem(m); 1508 return ENOBUFS; 1509 } 1510 } 1511 1512 /* mt = 1st mbuf, x = 2nd mbuf */ 1513 x = mt->m_next; 1514 while (mt->m_len < MINBUFSIZE) { 1515 if (x == NULL) { 1516 m_freem(m); 1517 return ENOBUFS; 1518 } 1519 1520 alignoff = (uintptr_t)x->m_data & 1521 (ALIGNBYTE - 1); 1522 chiplen = ALIGNBYTE - alignoff; 1523 if (chiplen > x->m_len) { 1524 chiplen = x->m_len; 1525 } else if ((mt->m_len + chiplen) < 1526 MINBUFSIZE) { 1527 /* 1528 * next mbuf should be greater 1529 * than ALIGNBYTE? 1530 */ 1531 if (x->m_len >= (chiplen + 1532 ALIGNBYTE * 2)) 1533 chiplen += ALIGNBYTE; 1534 else 1535 chiplen = x->m_len; 1536 } 1537 1538 if (chiplen && 1539 (M_TRAILINGSPACE(mt) < chiplen)) { 1540 /* 1541 * move data to the beginning of 1542 * m_dat[] (aligned) to en- 1543 * large trailingspace 1544 */ 1545 ap = M_BUFADDR(mt); 1546 ap = ALIGN_PTR(ap, ALIGNBYTE); 1547 memcpy(ap, mt->m_data, 1548 mt->m_len); 1549 mt->m_data = ap; 1550 } 1551 1552 if (chiplen && 1553 (M_TRAILINGSPACE(mt) >= chiplen)) { 1554 memcpy(mt->m_data + mt->m_len, 1555 x->m_data, chiplen); 1556 mt->m_len += chiplen; 1557 m_adj(x, chiplen); 1558 } 1559 1560 x = x->m_next; 1561 } 1562 } 1563 1564 } else { 1565 mt = m; 1566 1567 /* 1568 * allocate new mbuf x, and rearrange as below; 1569 * 1570 * align 8 * * * * * 1571 * +0123456789abcdef0123456789abcdef0 1572 * FROM m->m_data[____________abcdefghijklmnopq___] 1573 * 1574 * +0123456789abcdef0123456789abcdef0 1575 * TO x->m_data[________abcdefghijkl____________] 1576 * m->m_data[________________________mnopq___] 1577 * 1578 */ 1579 if (alignoff != 0) { 1580 /* at least ALIGNBYTE */ 1581 chiplen = ALIGNBYTE - alignoff + ALIGNBYTE; 1582 1583 MGET(x, M_DONTWAIT, m->m_type); 1584 if (x == NULL) { 1585 m_freem(m); 1586 return ENOBUFS; 1587 } 1588 MCLAIM(x, m->m_owner); 1589 if (m->m_flags & M_PKTHDR) 1590 m_move_pkthdr(x, m); 1591 x->m_data = ALIGN_PTR(x->m_data, ALIGNBYTE); 1592 memcpy(mtod(x, void *), mtod(m, void *), 1593 chiplen); 1594 x->m_len = chiplen; 1595 x->m_next = m; 1596 m_adj(m, chiplen); 1597 1598 if (p == NULL) 1599 m0 = x; 1600 else 1601 p->m_next = x; 1602 } 1603 } 1604 p = m; 1605 } 1606 *mp = m0; 1607 1608 return 0; 1609 } 1610 1611 static int 1612 enet_encap_txring(struct enet_softc *sc, struct mbuf **mp) 1613 { 1614 bus_dmamap_t map; 1615 struct mbuf *m; 1616 int csumflags, idx, i, error; 1617 uint32_t flags1, flags2; 1618 1619 idx = sc->sc_tx_prodidx; 1620 map = sc->sc_txsoft[idx].txs_dmamap; 1621 1622 /* align mbuf data for claim of ENET */ 1623 error = enet_encap_mbufalign(mp); 1624 if (error != 0) 1625 return error; 1626 1627 m = *mp; 1628 csumflags = m->m_pkthdr.csum_flags; 1629 1630 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1631 BUS_DMA_NOWAIT); 1632 if (error != 0) { 1633 device_printf(sc->sc_dev, 1634 "Error mapping mbuf into TX chain: error=%d\n", error); 1635 m_freem(m); 1636 return error; 1637 } 1638 1639 if (map->dm_nsegs > sc->sc_tx_free) { 1640 bus_dmamap_unload(sc->sc_dmat, map); 1641 device_printf(sc->sc_dev, 1642 "too many mbuf chain %d\n", map->dm_nsegs); 1643 m_freem(m); 1644 return ENOBUFS; 1645 } 1646 1647 /* fill protocol cksum zero beforehand */ 1648 if (csumflags & (M_CSUM_UDPv4 | M_CSUM_TCPv4 | 1649 M_CSUM_UDPv6 | M_CSUM_TCPv6)) { 1650 int ehlen; 1651 uint16_t etype; 1652 1653 m_copydata(m, ETHER_ADDR_LEN * 2, sizeof(etype), &etype); 1654 switch (ntohs(etype)) { 1655 case ETHERTYPE_IP: 1656 case ETHERTYPE_IPV6: 1657 ehlen = ETHER_HDR_LEN; 1658 break; 1659 case ETHERTYPE_VLAN: 1660 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1661 break; 1662 default: 1663 ehlen = 0; 1664 break; 1665 } 1666 1667 if (ehlen) { 1668 const int off = 1669 M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data) + 1670 M_CSUM_DATA_IPv4_OFFSET(m->m_pkthdr.csum_data); 1671 if (m->m_pkthdr.len >= ehlen + off + sizeof(uint16_t)) { 1672 uint16_t zero = 0; 1673 m_copyback(m, ehlen + off, sizeof(zero), &zero); 1674 } 1675 } 1676 } 1677 1678 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1679 BUS_DMASYNC_PREWRITE); 1680 1681 for (i = 0; i < map->dm_nsegs; i++) { 1682 flags1 = TXFLAGS1_R; 1683 flags2 = 0; 1684 1685 if (i == 0) { 1686 flags1 |= TXFLAGS1_T1; /* mark as first segment */ 1687 sc->sc_txsoft[idx].txs_mbuf = m; 1688 } 1689 1690 /* checksum offloading */ 1691 if (csumflags & (M_CSUM_UDPv4 | M_CSUM_TCPv4 | 1692 M_CSUM_UDPv6 | M_CSUM_TCPv6)) 1693 flags2 |= TXFLAGS2_PINS; 1694 if (csumflags & (M_CSUM_IPv4)) 1695 flags2 |= TXFLAGS2_IINS; 1696 1697 if (i == map->dm_nsegs - 1) { 1698 /* mark last segment */ 1699 flags1 |= TXFLAGS1_L | TXFLAGS1_TC; 1700 flags2 |= TXFLAGS2_INT; 1701 } 1702 if (idx == ENET_TX_RING_CNT - 1) { 1703 /* mark end of ring */ 1704 flags1 |= TXFLAGS1_W; 1705 } 1706 1707 sc->sc_txdesc_ring[idx].tx_databuf = map->dm_segs[i].ds_addr; 1708 sc->sc_txdesc_ring[idx].tx_flags2 = flags2; 1709 sc->sc_txdesc_ring[idx].tx_flags3 = 0; 1710 TXDESC_WRITEOUT(idx); 1711 1712 sc->sc_txdesc_ring[idx].tx_flags1_len = 1713 flags1 | TXFLAGS1_LEN(map->dm_segs[i].ds_len); 1714 TXDESC_WRITEOUT(idx); 1715 1716 idx = ENET_TX_NEXTIDX(idx); 1717 sc->sc_tx_free--; 1718 } 1719 1720 sc->sc_tx_prodidx = idx; 1721 1722 return 0; 1723 } 1724 1725 /* 1726 * device initialize 1727 */ 1728 static int 1729 enet_init_regs(struct enet_softc *sc, int init) 1730 { 1731 struct mii_data *mii; 1732 struct ifmedia_entry *ife; 1733 paddr_t paddr; 1734 uint32_t val; 1735 int miimode, fulldup, ecr_speed, rcr_speed, flowctrl; 1736 1737 if (init) { 1738 fulldup = 1; 1739 ecr_speed = ENET_ECR_SPEED; 1740 rcr_speed = 0; 1741 flowctrl = 0; 1742 } else { 1743 mii = &sc->sc_mii; 1744 ife = mii->mii_media.ifm_cur; 1745 1746 if ((ife->ifm_media & IFM_FDX) != 0) 1747 fulldup = 1; 1748 else 1749 fulldup = 0; 1750 1751 switch (IFM_SUBTYPE(ife->ifm_media)) { 1752 case IFM_10_T: 1753 ecr_speed = 0; 1754 rcr_speed = ENET_RCR_RMII_10T; 1755 break; 1756 case IFM_100_TX: 1757 ecr_speed = 0; 1758 rcr_speed = 0; 1759 break; 1760 default: 1761 ecr_speed = ENET_ECR_SPEED; 1762 rcr_speed = 0; 1763 break; 1764 } 1765 1766 flowctrl = sc->sc_flowflags & IFM_FLOW; 1767 } 1768 1769 if (sc->sc_rgmii == 0) 1770 ecr_speed = 0; 1771 1772 /* reset */ 1773 ENET_REG_WRITE(sc, ENET_ECR, ecr_speed | ENET_ECR_RESET); 1774 1775 /* mask and clear all interrupt */ 1776 ENET_REG_WRITE(sc, ENET_EIMR, 0); 1777 ENET_REG_WRITE(sc, ENET_EIR, 0xffffffff); 1778 1779 /* full duplex */ 1780 ENET_REG_WRITE(sc, ENET_TCR, fulldup ? ENET_TCR_FDEN : 0); 1781 1782 /* clear and enable MIB register */ 1783 ENET_REG_WRITE(sc, ENET_MIBC, ENET_MIBC_MIB_CLEAR); 1784 ENET_REG_WRITE(sc, ENET_MIBC, 0); 1785 1786 /* MII speed setup. MDCclk(=2.5MHz) = (internal module clock)/((val+1)*2) */ 1787 val = (sc->sc_clock + (5000000 - 1)) / 5000000 - 1; 1788 ENET_REG_WRITE(sc, ENET_MSCR, __SHIFTIN(val, ENET_MSCR_MII_SPEED)); 1789 1790 /* Opcode/Pause Duration */ 1791 ENET_REG_WRITE(sc, ENET_OPD, 0x00010020); 1792 1793 /* Receive FIFO */ 1794 ENET_REG_WRITE(sc, ENET_RSFL, 16); /* RxFIFO Section Full */ 1795 ENET_REG_WRITE(sc, ENET_RSEM, 0x84); /* RxFIFO Section Empty */ 1796 ENET_REG_WRITE(sc, ENET_RAEM, 8); /* RxFIFO Almost Empty */ 1797 ENET_REG_WRITE(sc, ENET_RAFL, 8); /* RxFIFO Almost Full */ 1798 1799 /* Transmit FIFO */ 1800 ENET_REG_WRITE(sc, ENET_TFWR, ENET_TFWR_STRFWD | 1801 ENET_TFWR_FIFO(128)); /* TxFIFO Watermark */ 1802 ENET_REG_WRITE(sc, ENET_TSEM, 0); /* TxFIFO Section Empty */ 1803 ENET_REG_WRITE(sc, ENET_TAEM, 256); /* TxFIFO Almost Empty */ 1804 ENET_REG_WRITE(sc, ENET_TAFL, 8); /* TxFIFO Almost Full */ 1805 ENET_REG_WRITE(sc, ENET_TIPG, 12); /* Tx Inter-Packet Gap */ 1806 1807 /* hardware checksum is default off (override in TX descripter) */ 1808 ENET_REG_WRITE(sc, ENET_TACC, 0); 1809 1810 /* 1811 * align ethernet payload on 32bit, discard frames with MAC layer error, 1812 * and don't discard checksum error 1813 */ 1814 ENET_REG_WRITE(sc, ENET_RACC, ENET_RACC_SHIFT16 | ENET_RACC_LINEDIS); 1815 1816 /* maximum frame size */ 1817 val = ENET_DEFAULT_PKT_LEN; 1818 ENET_REG_WRITE(sc, ENET_FTRL, val); /* Frame Truncation Length */ 1819 1820 if (sc->sc_rgmii == 0) 1821 miimode = ENET_RCR_RMII_MODE | ENET_RCR_MII_MODE; 1822 else 1823 miimode = ENET_RCR_RGMII_EN; 1824 ENET_REG_WRITE(sc, ENET_RCR, 1825 ENET_RCR_PADEN | /* RX frame padding remove */ 1826 miimode | 1827 (flowctrl ? ENET_RCR_FCE : 0) | /* flow control enable */ 1828 rcr_speed | 1829 (fulldup ? 0 : ENET_RCR_DRT) | 1830 ENET_RCR_MAX_FL(val)); 1831 1832 /* Maximum Receive BufSize per one descriptor */ 1833 ENET_REG_WRITE(sc, ENET_MRBR, RXDESC_MAXBUFSIZE); 1834 1835 1836 /* TX/RX Descriptor Physical Address */ 1837 paddr = sc->sc_txdesc_dmamap->dm_segs[0].ds_addr; 1838 ENET_REG_WRITE(sc, ENET_TDSR, paddr); 1839 paddr = sc->sc_rxdesc_dmamap->dm_segs[0].ds_addr; 1840 ENET_REG_WRITE(sc, ENET_RDSR, paddr); 1841 /* sync cache */ 1842 bus_dmamap_sync(sc->sc_dmat, sc->sc_txdesc_dmamap, 0, 1843 sc->sc_txdesc_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1844 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxdesc_dmamap, 0, 1845 sc->sc_rxdesc_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1846 1847 /* enable interrupts */ 1848 val = ENET_EIR_TXF | ENET_EIR_RXF | ENET_EIR_EBERR; 1849 if (sc->sc_imxtype == 7) 1850 val |= ENET_EIR_TXF2 | ENET_EIR_RXF2 | ENET_EIR_TXF1 | 1851 ENET_EIR_RXF1; 1852 ENET_REG_WRITE(sc, ENET_EIMR, val); 1853 1854 /* enable ether */ 1855 ENET_REG_WRITE(sc, ENET_ECR, 1856 #if _BYTE_ORDER == _LITTLE_ENDIAN 1857 ENET_ECR_DBSWP | 1858 #endif 1859 ecr_speed | 1860 ENET_ECR_EN1588 | /* use enhanced TX/RX descriptor */ 1861 ENET_ECR_ETHEREN); /* Ethernet Enable */ 1862 1863 return 0; 1864 } 1865 1866 static int 1867 enet_alloc_dma(struct enet_softc *sc, size_t size, void **addrp, 1868 bus_dmamap_t *mapp) 1869 { 1870 bus_dma_segment_t seglist[1]; 1871 int nsegs, error; 1872 1873 if ((error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, seglist, 1874 1, &nsegs, M_NOWAIT)) != 0) { 1875 device_printf(sc->sc_dev, 1876 "unable to allocate DMA buffer, error=%d\n", error); 1877 goto fail_alloc; 1878 } 1879 1880 if ((error = bus_dmamem_map(sc->sc_dmat, seglist, 1, size, addrp, 1881 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 1882 device_printf(sc->sc_dev, 1883 "unable to map DMA buffer, error=%d\n", 1884 error); 1885 goto fail_map; 1886 } 1887 1888 if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1889 BUS_DMA_NOWAIT, mapp)) != 0) { 1890 device_printf(sc->sc_dev, 1891 "unable to create DMA map, error=%d\n", error); 1892 goto fail_create; 1893 } 1894 1895 if ((error = bus_dmamap_load(sc->sc_dmat, *mapp, *addrp, size, NULL, 1896 BUS_DMA_NOWAIT)) != 0) { 1897 aprint_error_dev(sc->sc_dev, 1898 "unable to load DMA map, error=%d\n", error); 1899 goto fail_load; 1900 } 1901 1902 return 0; 1903 1904 fail_load: 1905 bus_dmamap_destroy(sc->sc_dmat, *mapp); 1906 fail_create: 1907 bus_dmamem_unmap(sc->sc_dmat, *addrp, size); 1908 fail_map: 1909 bus_dmamem_free(sc->sc_dmat, seglist, 1); 1910 fail_alloc: 1911 return error; 1912 } 1913
Indexes created Sun Sep 21 20:09:37 GMT 2025