| /src/sys/arch/arm/cortex/ |
| gic_v2m.c | 198 const uint64_t entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec; local in function:gic_v2m_msix_enable
199 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr);
200 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, (uint32_t)(addr >> 32));
201 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, data);
202 val = bus_space_read_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL);
204 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, val);
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| gicv3_its.c | 544 const uint64_t entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec; local in function:gicv3_its_msix_enable
545 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr);
546 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, (uint32_t)(addr >> 32));
547 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, lpi - its->its_pic->pic_irqbase);
548 val = bus_space_read_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL);
550 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, val);
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| /src/sys/arch/x86/pci/ |
| msipic.c | 517 uint64_t entry_base; local in function:msix_set_vecctl_mask
526 entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec;
531 entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL);
538 entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, vecctl);
570 uint64_t entry_base; local in function:msix_addroute
596 entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec;
613 entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, addr);
615 entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, 0);
617 entry_base + PCI_MSIX_TABLE_ENTRY_DATA, data);
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| /src/sys/arch/arm/apple/ |
| apple_pcie.c | 541 const uint64_t entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec; local in function:apple_pcie_msi_msix_enable
542 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO,
544 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI,
546 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA,
549 entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL);
551 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL,
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