1 /* $NetBSD: ast_post.c,v 1.3 2021/12/18 23:45:27 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 * 26 */ 27 /* 28 * Authors: Dave Airlie <airlied (at) redhat.com> 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: ast_post.c,v 1.3 2021/12/18 23:45:27 riastradh Exp $"); 33 34 #include <linux/delay.h> 35 #include <linux/pci.h> 36 37 #include <drm/drm_print.h> 38 39 #include "ast_dram_tables.h" 40 #include "ast_drv.h" 41 42 static void ast_post_chip_2300(struct drm_device *dev); 43 static void ast_post_chip_2500(struct drm_device *dev); 44 45 void ast_enable_vga(struct drm_device *dev) 46 { 47 struct ast_private *ast = dev->dev_private; 48 49 ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01); 50 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01); 51 } 52 53 void ast_enable_mmio(struct drm_device *dev) 54 { 55 struct ast_private *ast = dev->dev_private; 56 57 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06); 58 } 59 60 61 bool ast_is_vga_enabled(struct drm_device *dev) 62 { 63 struct ast_private *ast = dev->dev_private; 64 u8 ch; 65 66 if (ast->chip == AST1180) { 67 /* TODO 1180 */ 68 } else { 69 ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT); 70 return !!(ch & 0x01); 71 } 72 return false; 73 } 74 75 static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff }; 76 static const u8 extreginfo_ast2300a0[] = { 0x0f, 0x04, 0x1c, 0xff }; 77 static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff }; 78 79 static void 80 ast_set_def_ext_reg(struct drm_device *dev) 81 { 82 struct ast_private *ast = dev->dev_private; 83 u8 i, index, reg; 84 const u8 *ext_reg_info; 85 86 /* reset scratch */ 87 for (i = 0x81; i <= 0x9f; i++) 88 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00); 89 90 if (ast->chip == AST2300 || ast->chip == AST2400 || 91 ast->chip == AST2500) { 92 if (dev->pdev->revision >= 0x20) 93 ext_reg_info = extreginfo_ast2300; 94 else 95 ext_reg_info = extreginfo_ast2300a0; 96 } else 97 ext_reg_info = extreginfo; 98 99 index = 0xa0; 100 while (*ext_reg_info != 0xff) { 101 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info); 102 index++; 103 ext_reg_info++; 104 } 105 106 /* disable standard IO/MEM decode if secondary */ 107 /* ast_set_index_reg-mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x3); */ 108 109 /* Set Ext. Default */ 110 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01); 111 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00); 112 113 /* Enable RAMDAC for A1 */ 114 reg = 0x04; 115 if (ast->chip == AST2300 || ast->chip == AST2400 || 116 ast->chip == AST2500) 117 reg |= 0x20; 118 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg); 119 } 120 121 u32 ast_mindwm(struct ast_private *ast, u32 r) 122 { 123 uint32_t data; 124 125 ast_write32(ast, 0xf004, r & 0xffff0000); 126 ast_write32(ast, 0xf000, 0x1); 127 128 do { 129 data = ast_read32(ast, 0xf004) & 0xffff0000; 130 } while (data != (r & 0xffff0000)); 131 return ast_read32(ast, 0x10000 + (r & 0x0000ffff)); 132 } 133 134 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v) 135 { 136 uint32_t data; 137 ast_write32(ast, 0xf004, r & 0xffff0000); 138 ast_write32(ast, 0xf000, 0x1); 139 do { 140 data = ast_read32(ast, 0xf004) & 0xffff0000; 141 } while (data != (r & 0xffff0000)); 142 ast_write32(ast, 0x10000 + (r & 0x0000ffff), v); 143 } 144 145 /* 146 * AST2100/2150 DLL CBR Setting 147 */ 148 #define CBR_SIZE_AST2150 ((16 << 10) - 1) 149 #define CBR_PASSNUM_AST2150 5 150 #define CBR_THRESHOLD_AST2150 10 151 #define CBR_THRESHOLD2_AST2150 10 152 #define TIMEOUT_AST2150 5000000 153 154 #define CBR_PATNUM_AST2150 8 155 156 static const u32 pattern_AST2150[14] = { 157 0xFF00FF00, 158 0xCC33CC33, 159 0xAA55AA55, 160 0xFFFE0001, 161 0x683501FE, 162 0x0F1929B0, 163 0x2D0B4346, 164 0x60767F02, 165 0x6FBE36A6, 166 0x3A253035, 167 0x3019686D, 168 0x41C6167E, 169 0x620152BF, 170 0x20F050E0 171 }; 172 173 static u32 mmctestburst2_ast2150(struct ast_private *ast, u32 datagen) 174 { 175 u32 data, timeout; 176 177 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 178 ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3)); 179 timeout = 0; 180 do { 181 data = ast_mindwm(ast, 0x1e6e0070) & 0x40; 182 if (++timeout > TIMEOUT_AST2150) { 183 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 184 return 0xffffffff; 185 } 186 } while (!data); 187 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 188 ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3)); 189 timeout = 0; 190 do { 191 data = ast_mindwm(ast, 0x1e6e0070) & 0x40; 192 if (++timeout > TIMEOUT_AST2150) { 193 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 194 return 0xffffffff; 195 } 196 } while (!data); 197 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7; 198 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 199 return data; 200 } 201 202 #if 0 /* unused in DDX driver - here for completeness */ 203 static u32 mmctestsingle2_ast2150(struct ast_private *ast, u32 datagen) 204 { 205 u32 data, timeout; 206 207 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 208 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3)); 209 timeout = 0; 210 do { 211 data = ast_mindwm(ast, 0x1e6e0070) & 0x40; 212 if (++timeout > TIMEOUT_AST2150) { 213 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 214 return 0xffffffff; 215 } 216 } while (!data); 217 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7; 218 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 219 return data; 220 } 221 #endif 222 223 static int cbrtest_ast2150(struct ast_private *ast) 224 { 225 int i; 226 227 for (i = 0; i < 8; i++) 228 if (mmctestburst2_ast2150(ast, i)) 229 return 0; 230 return 1; 231 } 232 233 static int cbrscan_ast2150(struct ast_private *ast, int busw) 234 { 235 u32 patcnt, loop; 236 237 for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) { 238 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]); 239 for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) { 240 if (cbrtest_ast2150(ast)) 241 break; 242 } 243 if (loop == CBR_PASSNUM_AST2150) 244 return 0; 245 } 246 return 1; 247 } 248 249 250 static void cbrdlli_ast2150(struct ast_private *ast, int busw) 251 { 252 u32 dll_min[4], dll_max[4], dlli, data, passcnt; 253 254 cbr_start: 255 dll_min[0] = dll_min[1] = dll_min[2] = dll_min[3] = 0xff; 256 dll_max[0] = dll_max[1] = dll_max[2] = dll_max[3] = 0x0; 257 passcnt = 0; 258 259 for (dlli = 0; dlli < 100; dlli++) { 260 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); 261 data = cbrscan_ast2150(ast, busw); 262 if (data != 0) { 263 if (data & 0x1) { 264 if (dll_min[0] > dlli) 265 dll_min[0] = dlli; 266 if (dll_max[0] < dlli) 267 dll_max[0] = dlli; 268 } 269 passcnt++; 270 } else if (passcnt >= CBR_THRESHOLD_AST2150) 271 goto cbr_start; 272 } 273 if (dll_max[0] == 0 || (dll_max[0]-dll_min[0]) < CBR_THRESHOLD_AST2150) 274 goto cbr_start; 275 276 dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4); 277 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); 278 } 279 280 281 282 static void ast_init_dram_reg(struct drm_device *dev) 283 { 284 struct ast_private *ast = dev->dev_private; 285 u8 j; 286 u32 data, temp, i; 287 const struct ast_dramstruct *dram_reg_info; 288 289 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 290 291 if ((j & 0x80) == 0) { /* VGA only */ 292 if (ast->chip == AST2000) { 293 dram_reg_info = ast2000_dram_table_data; 294 ast_write32(ast, 0xf004, 0x1e6e0000); 295 ast_write32(ast, 0xf000, 0x1); 296 ast_write32(ast, 0x10100, 0xa8); 297 298 do { 299 ; 300 } while (ast_read32(ast, 0x10100) != 0xa8); 301 } else {/* AST2100/1100 */ 302 if (ast->chip == AST2100 || ast->chip == 2200) 303 dram_reg_info = ast2100_dram_table_data; 304 else 305 dram_reg_info = ast1100_dram_table_data; 306 307 ast_write32(ast, 0xf004, 0x1e6e0000); 308 ast_write32(ast, 0xf000, 0x1); 309 ast_write32(ast, 0x12000, 0x1688A8A8); 310 do { 311 ; 312 } while (ast_read32(ast, 0x12000) != 0x01); 313 314 ast_write32(ast, 0x10000, 0xfc600309); 315 do { 316 ; 317 } while (ast_read32(ast, 0x10000) != 0x01); 318 } 319 320 while (dram_reg_info->index != 0xffff) { 321 if (dram_reg_info->index == 0xff00) {/* delay fn */ 322 for (i = 0; i < 15; i++) 323 udelay(dram_reg_info->data); 324 } else if (dram_reg_info->index == 0x4 && ast->chip != AST2000) { 325 data = dram_reg_info->data; 326 if (ast->dram_type == AST_DRAM_1Gx16) 327 data = 0x00000d89; 328 else if (ast->dram_type == AST_DRAM_1Gx32) 329 data = 0x00000c8d; 330 331 temp = ast_read32(ast, 0x12070); 332 temp &= 0xc; 333 temp <<= 2; 334 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp); 335 } else 336 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data); 337 dram_reg_info++; 338 } 339 340 /* AST 2100/2150 DRAM calibration */ 341 data = ast_read32(ast, 0x10120); 342 if (data == 0x5061) { /* 266Mhz */ 343 data = ast_read32(ast, 0x10004); 344 if (data & 0x40) 345 cbrdlli_ast2150(ast, 16); /* 16 bits */ 346 else 347 cbrdlli_ast2150(ast, 32); /* 32 bits */ 348 } 349 350 switch (ast->chip) { 351 case AST2000: 352 temp = ast_read32(ast, 0x10140); 353 ast_write32(ast, 0x10140, temp | 0x40); 354 break; 355 case AST1100: 356 case AST2100: 357 case AST2200: 358 case AST2150: 359 temp = ast_read32(ast, 0x1200c); 360 ast_write32(ast, 0x1200c, temp & 0xfffffffd); 361 temp = ast_read32(ast, 0x12040); 362 ast_write32(ast, 0x12040, temp | 0x40); 363 break; 364 default: 365 break; 366 } 367 } 368 369 /* wait ready */ 370 do { 371 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 372 } while ((j & 0x40) == 0); 373 } 374 375 void ast_post_gpu(struct drm_device *dev) 376 { 377 u32 reg; 378 struct ast_private *ast = dev->dev_private; 379 380 pci_read_config_dword(ast->dev->pdev, 0x04, ®); 381 reg |= 0x3; 382 pci_write_config_dword(ast->dev->pdev, 0x04, reg); 383 384 ast_enable_vga(dev); 385 ast_open_key(ast); 386 ast_enable_mmio(dev); 387 ast_set_def_ext_reg(dev); 388 389 if (ast->config_mode == ast_use_p2a) { 390 if (ast->chip == AST2500) 391 ast_post_chip_2500(dev); 392 else if (ast->chip == AST2300 || ast->chip == AST2400) 393 ast_post_chip_2300(dev); 394 else 395 ast_init_dram_reg(dev); 396 397 ast_init_3rdtx(dev); 398 } else { 399 if (ast->tx_chip_type != AST_TX_NONE) 400 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); /* Enable DVO */ 401 } 402 } 403 404 /* AST 2300 DRAM settings */ 405 #define AST_DDR3 0 406 #define AST_DDR2 1 407 408 struct ast2300_dram_param { 409 u32 dram_type; 410 u32 dram_chipid; 411 u32 dram_freq; 412 u32 vram_size; 413 u32 odt; 414 u32 wodt; 415 u32 rodt; 416 u32 dram_config; 417 u32 reg_PERIOD; 418 u32 reg_MADJ; 419 u32 reg_SADJ; 420 u32 reg_MRS; 421 u32 reg_EMRS; 422 u32 reg_AC1; 423 u32 reg_AC2; 424 u32 reg_DQSIC; 425 u32 reg_DRV; 426 u32 reg_IOZ; 427 u32 reg_DQIDLY; 428 u32 reg_FREQ; 429 u32 madj_max; 430 u32 dll2_finetune_step; 431 }; 432 433 /* 434 * DQSI DLL CBR Setting 435 */ 436 #define CBR_SIZE0 ((1 << 10) - 1) 437 #define CBR_SIZE1 ((4 << 10) - 1) 438 #define CBR_SIZE2 ((64 << 10) - 1) 439 #define CBR_PASSNUM 5 440 #define CBR_PASSNUM2 5 441 #define CBR_THRESHOLD 10 442 #define CBR_THRESHOLD2 10 443 #define TIMEOUT 5000000 444 #define CBR_PATNUM 8 445 446 static const u32 pattern[8] = { 447 0xFF00FF00, 448 0xCC33CC33, 449 0xAA55AA55, 450 0x88778877, 451 0x92CC4D6E, 452 0x543D3CDE, 453 0xF1E843C7, 454 0x7C61D253 455 }; 456 457 static bool mmc_test(struct ast_private *ast, u32 datagen, u8 test_ctl) 458 { 459 u32 data, timeout; 460 461 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 462 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl); 463 timeout = 0; 464 do { 465 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000; 466 if (data & 0x2000) 467 return false; 468 if (++timeout > TIMEOUT) { 469 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 470 return false; 471 } 472 } while (!data); 473 ast_moutdwm(ast, 0x1e6e0070, 0x0); 474 return true; 475 } 476 477 static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl) 478 { 479 u32 data, timeout; 480 481 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 482 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl); 483 timeout = 0; 484 do { 485 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000; 486 if (++timeout > TIMEOUT) { 487 ast_moutdwm(ast, 0x1e6e0070, 0x0); 488 return 0xffffffff; 489 } 490 } while (!data); 491 data = ast_mindwm(ast, 0x1e6e0078); 492 data = (data | (data >> 16)) & 0xffff; 493 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 494 return data; 495 } 496 497 498 static bool mmc_test_burst(struct ast_private *ast, u32 datagen) 499 { 500 return mmc_test(ast, datagen, 0xc1); 501 } 502 503 static u32 mmc_test_burst2(struct ast_private *ast, u32 datagen) 504 { 505 return mmc_test2(ast, datagen, 0x41); 506 } 507 508 static bool mmc_test_single(struct ast_private *ast, u32 datagen) 509 { 510 return mmc_test(ast, datagen, 0xc5); 511 } 512 513 static u32 mmc_test_single2(struct ast_private *ast, u32 datagen) 514 { 515 return mmc_test2(ast, datagen, 0x05); 516 } 517 518 static bool mmc_test_single_2500(struct ast_private *ast, u32 datagen) 519 { 520 return mmc_test(ast, datagen, 0x85); 521 } 522 523 static int cbr_test(struct ast_private *ast) 524 { 525 u32 data; 526 int i; 527 data = mmc_test_single2(ast, 0); 528 if ((data & 0xff) && (data & 0xff00)) 529 return 0; 530 for (i = 0; i < 8; i++) { 531 data = mmc_test_burst2(ast, i); 532 if ((data & 0xff) && (data & 0xff00)) 533 return 0; 534 } 535 if (!data) 536 return 3; 537 else if (data & 0xff) 538 return 2; 539 return 1; 540 } 541 542 static int cbr_scan(struct ast_private *ast) 543 { 544 u32 data, data2, patcnt, loop; 545 546 data2 = 3; 547 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) { 548 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); 549 for (loop = 0; loop < CBR_PASSNUM2; loop++) { 550 if ((data = cbr_test(ast)) != 0) { 551 data2 &= data; 552 if (!data2) 553 return 0; 554 break; 555 } 556 } 557 if (loop == CBR_PASSNUM2) 558 return 0; 559 } 560 return data2; 561 } 562 563 static u32 cbr_test2(struct ast_private *ast) 564 { 565 u32 data; 566 567 data = mmc_test_burst2(ast, 0); 568 if (data == 0xffff) 569 return 0; 570 data |= mmc_test_single2(ast, 0); 571 if (data == 0xffff) 572 return 0; 573 574 return ~data & 0xffff; 575 } 576 577 static u32 cbr_scan2(struct ast_private *ast) 578 { 579 u32 data, data2, patcnt, loop; 580 581 data2 = 0xffff; 582 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) { 583 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); 584 for (loop = 0; loop < CBR_PASSNUM2; loop++) { 585 if ((data = cbr_test2(ast)) != 0) { 586 data2 &= data; 587 if (!data2) 588 return 0; 589 break; 590 } 591 } 592 if (loop == CBR_PASSNUM2) 593 return 0; 594 } 595 return data2; 596 } 597 598 static bool cbr_test3(struct ast_private *ast) 599 { 600 if (!mmc_test_burst(ast, 0)) 601 return false; 602 if (!mmc_test_single(ast, 0)) 603 return false; 604 return true; 605 } 606 607 static bool cbr_scan3(struct ast_private *ast) 608 { 609 u32 patcnt, loop; 610 611 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) { 612 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); 613 for (loop = 0; loop < 2; loop++) { 614 if (cbr_test3(ast)) 615 break; 616 } 617 if (loop == 2) 618 return false; 619 } 620 return true; 621 } 622 623 static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param) 624 { 625 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0; 626 bool status = false; 627 FINETUNE_START: 628 for (cnt = 0; cnt < 16; cnt++) { 629 dllmin[cnt] = 0xff; 630 dllmax[cnt] = 0x0; 631 } 632 passcnt = 0; 633 for (dlli = 0; dlli < 76; dlli++) { 634 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24)); 635 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1); 636 data = cbr_scan2(ast); 637 if (data != 0) { 638 mask = 0x00010001; 639 for (cnt = 0; cnt < 16; cnt++) { 640 if (data & mask) { 641 if (dllmin[cnt] > dlli) { 642 dllmin[cnt] = dlli; 643 } 644 if (dllmax[cnt] < dlli) { 645 dllmax[cnt] = dlli; 646 } 647 } 648 mask <<= 1; 649 } 650 passcnt++; 651 } else if (passcnt >= CBR_THRESHOLD2) { 652 break; 653 } 654 } 655 gold_sadj[0] = 0x0; 656 passcnt = 0; 657 for (cnt = 0; cnt < 16; cnt++) { 658 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) { 659 gold_sadj[0] += dllmin[cnt]; 660 passcnt++; 661 } 662 } 663 if (retry++ > 10) 664 goto FINETUNE_DONE; 665 if (passcnt != 16) { 666 goto FINETUNE_START; 667 } 668 status = true; 669 FINETUNE_DONE: 670 gold_sadj[0] = gold_sadj[0] >> 4; 671 gold_sadj[1] = gold_sadj[0]; 672 673 data = 0; 674 for (cnt = 0; cnt < 8; cnt++) { 675 data >>= 3; 676 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) { 677 dlli = dllmin[cnt]; 678 if (gold_sadj[0] >= dlli) { 679 dlli = ((gold_sadj[0] - dlli) * 19) >> 5; 680 if (dlli > 3) { 681 dlli = 3; 682 } 683 } else { 684 dlli = ((dlli - gold_sadj[0]) * 19) >> 5; 685 if (dlli > 4) { 686 dlli = 4; 687 } 688 dlli = (8 - dlli) & 0x7; 689 } 690 data |= dlli << 21; 691 } 692 } 693 ast_moutdwm(ast, 0x1E6E0080, data); 694 695 data = 0; 696 for (cnt = 8; cnt < 16; cnt++) { 697 data >>= 3; 698 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) { 699 dlli = dllmin[cnt]; 700 if (gold_sadj[1] >= dlli) { 701 dlli = ((gold_sadj[1] - dlli) * 19) >> 5; 702 if (dlli > 3) { 703 dlli = 3; 704 } else { 705 dlli = (dlli - 1) & 0x7; 706 } 707 } else { 708 dlli = ((dlli - gold_sadj[1]) * 19) >> 5; 709 dlli += 1; 710 if (dlli > 4) { 711 dlli = 4; 712 } 713 dlli = (8 - dlli) & 0x7; 714 } 715 data |= dlli << 21; 716 } 717 } 718 ast_moutdwm(ast, 0x1E6E0084, data); 719 return status; 720 } /* finetuneDQI_L */ 721 722 static void finetuneDQSI(struct ast_private *ast) 723 { 724 u32 dlli, dqsip, dqidly; 725 u32 reg_mcr18, reg_mcr0c, passcnt[2], diff; 726 u32 g_dqidly, g_dqsip, g_margin, g_side; 727 u16 pass[32][2][2]; 728 char tag[2][76]; 729 730 /* Disable DQI CBR */ 731 reg_mcr0c = ast_mindwm(ast, 0x1E6E000C); 732 reg_mcr18 = ast_mindwm(ast, 0x1E6E0018); 733 reg_mcr18 &= 0x0000ffff; 734 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18); 735 736 for (dlli = 0; dlli < 76; dlli++) { 737 tag[0][dlli] = 0x0; 738 tag[1][dlli] = 0x0; 739 } 740 for (dqidly = 0; dqidly < 32; dqidly++) { 741 pass[dqidly][0][0] = 0xff; 742 pass[dqidly][0][1] = 0x0; 743 pass[dqidly][1][0] = 0xff; 744 pass[dqidly][1][1] = 0x0; 745 } 746 for (dqidly = 0; dqidly < 32; dqidly++) { 747 passcnt[0] = passcnt[1] = 0; 748 for (dqsip = 0; dqsip < 2; dqsip++) { 749 ast_moutdwm(ast, 0x1E6E000C, 0); 750 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23)); 751 ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c); 752 for (dlli = 0; dlli < 76; dlli++) { 753 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); 754 ast_moutdwm(ast, 0x1E6E0070, 0); 755 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0); 756 if (cbr_scan3(ast)) { 757 if (dlli == 0) 758 break; 759 passcnt[dqsip]++; 760 tag[dqsip][dlli] = 'P'; 761 if (dlli < pass[dqidly][dqsip][0]) 762 pass[dqidly][dqsip][0] = (u16) dlli; 763 if (dlli > pass[dqidly][dqsip][1]) 764 pass[dqidly][dqsip][1] = (u16) dlli; 765 } else if (passcnt[dqsip] >= 5) 766 break; 767 else { 768 pass[dqidly][dqsip][0] = 0xff; 769 pass[dqidly][dqsip][1] = 0x0; 770 } 771 } 772 } 773 if (passcnt[0] == 0 && passcnt[1] == 0) 774 dqidly++; 775 } 776 /* Search margin */ 777 g_dqidly = g_dqsip = g_margin = g_side = 0; 778 779 for (dqidly = 0; dqidly < 32; dqidly++) { 780 for (dqsip = 0; dqsip < 2; dqsip++) { 781 if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1]) 782 continue; 783 diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0]; 784 if ((diff+2) < g_margin) 785 continue; 786 passcnt[0] = passcnt[1] = 0; 787 for (dlli = pass[dqidly][dqsip][0]; dlli > 0 && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++); 788 for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++); 789 if (passcnt[0] > passcnt[1]) 790 passcnt[0] = passcnt[1]; 791 passcnt[1] = 0; 792 if (passcnt[0] > g_side) 793 passcnt[1] = passcnt[0] - g_side; 794 if (diff > (g_margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) { 795 g_margin = diff; 796 g_dqidly = dqidly; 797 g_dqsip = dqsip; 798 g_side = passcnt[0]; 799 } else if (passcnt[1] > 1 && g_side < 8) { 800 if (diff > g_margin) 801 g_margin = diff; 802 g_dqidly = dqidly; 803 g_dqsip = dqsip; 804 g_side = passcnt[0]; 805 } 806 } 807 } 808 reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23); 809 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18); 810 811 } 812 static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param) 813 { 814 u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0; 815 bool status = false; 816 817 finetuneDQSI(ast); 818 if (finetuneDQI_L(ast, param) == false) 819 return status; 820 821 CBR_START2: 822 dllmin[0] = dllmin[1] = 0xff; 823 dllmax[0] = dllmax[1] = 0x0; 824 passcnt = 0; 825 for (dlli = 0; dlli < 76; dlli++) { 826 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); 827 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2); 828 data = cbr_scan(ast); 829 if (data != 0) { 830 if (data & 0x1) { 831 if (dllmin[0] > dlli) { 832 dllmin[0] = dlli; 833 } 834 if (dllmax[0] < dlli) { 835 dllmax[0] = dlli; 836 } 837 } 838 if (data & 0x2) { 839 if (dllmin[1] > dlli) { 840 dllmin[1] = dlli; 841 } 842 if (dllmax[1] < dlli) { 843 dllmax[1] = dlli; 844 } 845 } 846 passcnt++; 847 } else if (passcnt >= CBR_THRESHOLD) { 848 break; 849 } 850 } 851 if (retry++ > 10) 852 goto CBR_DONE2; 853 if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) { 854 goto CBR_START2; 855 } 856 if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) { 857 goto CBR_START2; 858 } 859 status = true; 860 CBR_DONE2: 861 dlli = (dllmin[1] + dllmax[1]) >> 1; 862 dlli <<= 8; 863 dlli += (dllmin[0] + dllmax[0]) >> 1; 864 ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16)); 865 return status; 866 } /* CBRDLL2 */ 867 868 static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *param) 869 { 870 u32 trap, trap_AC2, trap_MRS; 871 872 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); 873 874 /* Ger trap info */ 875 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3; 876 trap_AC2 = 0x00020000 + (trap << 16); 877 trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19); 878 trap_MRS = 0x00000010 + (trap << 4); 879 trap_MRS |= ((trap & 0x2) << 18); 880 881 param->reg_MADJ = 0x00034C4C; 882 param->reg_SADJ = 0x00001800; 883 param->reg_DRV = 0x000000F0; 884 param->reg_PERIOD = param->dram_freq; 885 param->rodt = 0; 886 887 switch (param->dram_freq) { 888 case 336: 889 ast_moutdwm(ast, 0x1E6E2020, 0x0190); 890 param->wodt = 0; 891 param->reg_AC1 = 0x22202725; 892 param->reg_AC2 = 0xAA007613 | trap_AC2; 893 param->reg_DQSIC = 0x000000BA; 894 param->reg_MRS = 0x04001400 | trap_MRS; 895 param->reg_EMRS = 0x00000000; 896 param->reg_IOZ = 0x00000023; 897 param->reg_DQIDLY = 0x00000074; 898 param->reg_FREQ = 0x00004DC0; 899 param->madj_max = 96; 900 param->dll2_finetune_step = 3; 901 switch (param->dram_chipid) { 902 default: 903 case AST_DRAM_512Mx16: 904 case AST_DRAM_1Gx16: 905 param->reg_AC2 = 0xAA007613 | trap_AC2; 906 break; 907 case AST_DRAM_2Gx16: 908 param->reg_AC2 = 0xAA00761C | trap_AC2; 909 break; 910 case AST_DRAM_4Gx16: 911 param->reg_AC2 = 0xAA007636 | trap_AC2; 912 break; 913 } 914 break; 915 default: 916 case 396: 917 ast_moutdwm(ast, 0x1E6E2020, 0x03F1); 918 param->wodt = 1; 919 param->reg_AC1 = 0x33302825; 920 param->reg_AC2 = 0xCC009617 | trap_AC2; 921 param->reg_DQSIC = 0x000000E2; 922 param->reg_MRS = 0x04001600 | trap_MRS; 923 param->reg_EMRS = 0x00000000; 924 param->reg_IOZ = 0x00000034; 925 param->reg_DRV = 0x000000FA; 926 param->reg_DQIDLY = 0x00000089; 927 param->reg_FREQ = 0x00005040; 928 param->madj_max = 96; 929 param->dll2_finetune_step = 4; 930 931 switch (param->dram_chipid) { 932 default: 933 case AST_DRAM_512Mx16: 934 case AST_DRAM_1Gx16: 935 param->reg_AC2 = 0xCC009617 | trap_AC2; 936 break; 937 case AST_DRAM_2Gx16: 938 param->reg_AC2 = 0xCC009622 | trap_AC2; 939 break; 940 case AST_DRAM_4Gx16: 941 param->reg_AC2 = 0xCC00963F | trap_AC2; 942 break; 943 } 944 break; 945 946 case 408: 947 ast_moutdwm(ast, 0x1E6E2020, 0x01F0); 948 param->wodt = 1; 949 param->reg_AC1 = 0x33302825; 950 param->reg_AC2 = 0xCC009617 | trap_AC2; 951 param->reg_DQSIC = 0x000000E2; 952 param->reg_MRS = 0x04001600 | trap_MRS; 953 param->reg_EMRS = 0x00000000; 954 param->reg_IOZ = 0x00000023; 955 param->reg_DRV = 0x000000FA; 956 param->reg_DQIDLY = 0x00000089; 957 param->reg_FREQ = 0x000050C0; 958 param->madj_max = 96; 959 param->dll2_finetune_step = 4; 960 961 switch (param->dram_chipid) { 962 default: 963 case AST_DRAM_512Mx16: 964 case AST_DRAM_1Gx16: 965 param->reg_AC2 = 0xCC009617 | trap_AC2; 966 break; 967 case AST_DRAM_2Gx16: 968 param->reg_AC2 = 0xCC009622 | trap_AC2; 969 break; 970 case AST_DRAM_4Gx16: 971 param->reg_AC2 = 0xCC00963F | trap_AC2; 972 break; 973 } 974 975 break; 976 case 456: 977 ast_moutdwm(ast, 0x1E6E2020, 0x0230); 978 param->wodt = 0; 979 param->reg_AC1 = 0x33302926; 980 param->reg_AC2 = 0xCD44961A; 981 param->reg_DQSIC = 0x000000FC; 982 param->reg_MRS = 0x00081830; 983 param->reg_EMRS = 0x00000000; 984 param->reg_IOZ = 0x00000045; 985 param->reg_DQIDLY = 0x00000097; 986 param->reg_FREQ = 0x000052C0; 987 param->madj_max = 88; 988 param->dll2_finetune_step = 4; 989 break; 990 case 504: 991 ast_moutdwm(ast, 0x1E6E2020, 0x0270); 992 param->wodt = 1; 993 param->reg_AC1 = 0x33302926; 994 param->reg_AC2 = 0xDE44A61D; 995 param->reg_DQSIC = 0x00000117; 996 param->reg_MRS = 0x00081A30; 997 param->reg_EMRS = 0x00000000; 998 param->reg_IOZ = 0x070000BB; 999 param->reg_DQIDLY = 0x000000A0; 1000 param->reg_FREQ = 0x000054C0; 1001 param->madj_max = 79; 1002 param->dll2_finetune_step = 4; 1003 break; 1004 case 528: 1005 ast_moutdwm(ast, 0x1E6E2020, 0x0290); 1006 param->wodt = 1; 1007 param->rodt = 1; 1008 param->reg_AC1 = 0x33302926; 1009 param->reg_AC2 = 0xEF44B61E; 1010 param->reg_DQSIC = 0x00000125; 1011 param->reg_MRS = 0x00081A30; 1012 param->reg_EMRS = 0x00000040; 1013 param->reg_DRV = 0x000000F5; 1014 param->reg_IOZ = 0x00000023; 1015 param->reg_DQIDLY = 0x00000088; 1016 param->reg_FREQ = 0x000055C0; 1017 param->madj_max = 76; 1018 param->dll2_finetune_step = 3; 1019 break; 1020 case 576: 1021 ast_moutdwm(ast, 0x1E6E2020, 0x0140); 1022 param->reg_MADJ = 0x00136868; 1023 param->reg_SADJ = 0x00004534; 1024 param->wodt = 1; 1025 param->rodt = 1; 1026 param->reg_AC1 = 0x33302A37; 1027 param->reg_AC2 = 0xEF56B61E; 1028 param->reg_DQSIC = 0x0000013F; 1029 param->reg_MRS = 0x00101A50; 1030 param->reg_EMRS = 0x00000040; 1031 param->reg_DRV = 0x000000FA; 1032 param->reg_IOZ = 0x00000023; 1033 param->reg_DQIDLY = 0x00000078; 1034 param->reg_FREQ = 0x000057C0; 1035 param->madj_max = 136; 1036 param->dll2_finetune_step = 3; 1037 break; 1038 case 600: 1039 ast_moutdwm(ast, 0x1E6E2020, 0x02E1); 1040 param->reg_MADJ = 0x00136868; 1041 param->reg_SADJ = 0x00004534; 1042 param->wodt = 1; 1043 param->rodt = 1; 1044 param->reg_AC1 = 0x32302A37; 1045 param->reg_AC2 = 0xDF56B61F; 1046 param->reg_DQSIC = 0x0000014D; 1047 param->reg_MRS = 0x00101A50; 1048 param->reg_EMRS = 0x00000004; 1049 param->reg_DRV = 0x000000F5; 1050 param->reg_IOZ = 0x00000023; 1051 param->reg_DQIDLY = 0x00000078; 1052 param->reg_FREQ = 0x000058C0; 1053 param->madj_max = 132; 1054 param->dll2_finetune_step = 3; 1055 break; 1056 case 624: 1057 ast_moutdwm(ast, 0x1E6E2020, 0x0160); 1058 param->reg_MADJ = 0x00136868; 1059 param->reg_SADJ = 0x00004534; 1060 param->wodt = 1; 1061 param->rodt = 1; 1062 param->reg_AC1 = 0x32302A37; 1063 param->reg_AC2 = 0xEF56B621; 1064 param->reg_DQSIC = 0x0000015A; 1065 param->reg_MRS = 0x02101A50; 1066 param->reg_EMRS = 0x00000004; 1067 param->reg_DRV = 0x000000F5; 1068 param->reg_IOZ = 0x00000034; 1069 param->reg_DQIDLY = 0x00000078; 1070 param->reg_FREQ = 0x000059C0; 1071 param->madj_max = 128; 1072 param->dll2_finetune_step = 3; 1073 break; 1074 } /* switch freq */ 1075 1076 switch (param->dram_chipid) { 1077 case AST_DRAM_512Mx16: 1078 param->dram_config = 0x130; 1079 break; 1080 default: 1081 case AST_DRAM_1Gx16: 1082 param->dram_config = 0x131; 1083 break; 1084 case AST_DRAM_2Gx16: 1085 param->dram_config = 0x132; 1086 break; 1087 case AST_DRAM_4Gx16: 1088 param->dram_config = 0x133; 1089 break; 1090 } /* switch size */ 1091 1092 switch (param->vram_size) { 1093 default: 1094 case AST_VIDMEM_SIZE_8M: 1095 param->dram_config |= 0x00; 1096 break; 1097 case AST_VIDMEM_SIZE_16M: 1098 param->dram_config |= 0x04; 1099 break; 1100 case AST_VIDMEM_SIZE_32M: 1101 param->dram_config |= 0x08; 1102 break; 1103 case AST_VIDMEM_SIZE_64M: 1104 param->dram_config |= 0x0c; 1105 break; 1106 } 1107 1108 } 1109 1110 static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param) 1111 { 1112 u32 data, data2, retry = 0; 1113 1114 ddr3_init_start: 1115 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); 1116 ast_moutdwm(ast, 0x1E6E0018, 0x00000100); 1117 ast_moutdwm(ast, 0x1E6E0024, 0x00000000); 1118 ast_moutdwm(ast, 0x1E6E0034, 0x00000000); 1119 udelay(10); 1120 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ); 1121 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ); 1122 udelay(10); 1123 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); 1124 udelay(10); 1125 1126 ast_moutdwm(ast, 0x1E6E0004, param->dram_config); 1127 ast_moutdwm(ast, 0x1E6E0008, 0x90040f); 1128 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1); 1129 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2); 1130 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); 1131 ast_moutdwm(ast, 0x1E6E0080, 0x00000000); 1132 ast_moutdwm(ast, 0x1E6E0084, 0x00000000); 1133 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); 1134 ast_moutdwm(ast, 0x1E6E0018, 0x4000A170); 1135 ast_moutdwm(ast, 0x1E6E0018, 0x00002370); 1136 ast_moutdwm(ast, 0x1E6E0038, 0x00000000); 1137 ast_moutdwm(ast, 0x1E6E0040, 0xFF444444); 1138 ast_moutdwm(ast, 0x1E6E0044, 0x22222222); 1139 ast_moutdwm(ast, 0x1E6E0048, 0x22222222); 1140 ast_moutdwm(ast, 0x1E6E004C, 0x00000002); 1141 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); 1142 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); 1143 ast_moutdwm(ast, 0x1E6E0054, 0); 1144 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV); 1145 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ); 1146 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); 1147 ast_moutdwm(ast, 0x1E6E0074, 0x00000000); 1148 ast_moutdwm(ast, 0x1E6E0078, 0x00000000); 1149 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); 1150 /* Wait MCLK2X lock to MCLK */ 1151 do { 1152 data = ast_mindwm(ast, 0x1E6E001C); 1153 } while (!(data & 0x08000000)); 1154 data = ast_mindwm(ast, 0x1E6E001C); 1155 data = (data >> 8) & 0xff; 1156 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) { 1157 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; 1158 if ((data2 & 0xff) > param->madj_max) { 1159 break; 1160 } 1161 ast_moutdwm(ast, 0x1E6E0064, data2); 1162 if (data2 & 0x00100000) { 1163 data2 = ((data2 & 0xff) >> 3) + 3; 1164 } else { 1165 data2 = ((data2 & 0xff) >> 2) + 5; 1166 } 1167 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff; 1168 data2 += data & 0xff; 1169 data = data | (data2 << 8); 1170 ast_moutdwm(ast, 0x1E6E0068, data); 1171 udelay(10); 1172 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000); 1173 udelay(10); 1174 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff; 1175 ast_moutdwm(ast, 0x1E6E0018, data); 1176 data = data | 0x200; 1177 ast_moutdwm(ast, 0x1E6E0018, data); 1178 do { 1179 data = ast_mindwm(ast, 0x1E6E001C); 1180 } while (!(data & 0x08000000)); 1181 1182 data = ast_mindwm(ast, 0x1E6E001C); 1183 data = (data >> 8) & 0xff; 1184 } 1185 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff); 1186 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00; 1187 ast_moutdwm(ast, 0x1E6E0018, data); 1188 1189 ast_moutdwm(ast, 0x1E6E0034, 0x00000001); 1190 ast_moutdwm(ast, 0x1E6E000C, 0x00000040); 1191 udelay(50); 1192 /* Mode Register Setting */ 1193 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); 1194 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); 1195 ast_moutdwm(ast, 0x1E6E0028, 0x00000005); 1196 ast_moutdwm(ast, 0x1E6E0028, 0x00000007); 1197 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); 1198 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); 1199 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS); 1200 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08); 1201 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); 1202 1203 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); 1204 data = 0; 1205 if (param->wodt) { 1206 data = 0x300; 1207 } 1208 if (param->rodt) { 1209 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3); 1210 } 1211 ast_moutdwm(ast, 0x1E6E0034, data | 0x3); 1212 1213 /* Calibrate the DQSI delay */ 1214 if ((cbr_dll2(ast, param) == false) && (retry++ < 10)) 1215 goto ddr3_init_start; 1216 1217 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ); 1218 /* ECC Memory Initialization */ 1219 #ifdef ECC 1220 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); 1221 ast_moutdwm(ast, 0x1E6E0070, 0x221); 1222 do { 1223 data = ast_mindwm(ast, 0x1E6E0070); 1224 } while (!(data & 0x00001000)); 1225 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); 1226 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); 1227 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); 1228 #endif 1229 1230 1231 } 1232 1233 static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *param) 1234 { 1235 u32 trap, trap_AC2, trap_MRS; 1236 1237 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); 1238 1239 /* Ger trap info */ 1240 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3; 1241 trap_AC2 = (trap << 20) | (trap << 16); 1242 trap_AC2 += 0x00110000; 1243 trap_MRS = 0x00000040 | (trap << 4); 1244 1245 1246 param->reg_MADJ = 0x00034C4C; 1247 param->reg_SADJ = 0x00001800; 1248 param->reg_DRV = 0x000000F0; 1249 param->reg_PERIOD = param->dram_freq; 1250 param->rodt = 0; 1251 1252 switch (param->dram_freq) { 1253 case 264: 1254 ast_moutdwm(ast, 0x1E6E2020, 0x0130); 1255 param->wodt = 0; 1256 param->reg_AC1 = 0x11101513; 1257 param->reg_AC2 = 0x78117011; 1258 param->reg_DQSIC = 0x00000092; 1259 param->reg_MRS = 0x00000842; 1260 param->reg_EMRS = 0x00000000; 1261 param->reg_DRV = 0x000000F0; 1262 param->reg_IOZ = 0x00000034; 1263 param->reg_DQIDLY = 0x0000005A; 1264 param->reg_FREQ = 0x00004AC0; 1265 param->madj_max = 138; 1266 param->dll2_finetune_step = 3; 1267 break; 1268 case 336: 1269 ast_moutdwm(ast, 0x1E6E2020, 0x0190); 1270 param->wodt = 1; 1271 param->reg_AC1 = 0x22202613; 1272 param->reg_AC2 = 0xAA009016 | trap_AC2; 1273 param->reg_DQSIC = 0x000000BA; 1274 param->reg_MRS = 0x00000A02 | trap_MRS; 1275 param->reg_EMRS = 0x00000040; 1276 param->reg_DRV = 0x000000FA; 1277 param->reg_IOZ = 0x00000034; 1278 param->reg_DQIDLY = 0x00000074; 1279 param->reg_FREQ = 0x00004DC0; 1280 param->madj_max = 96; 1281 param->dll2_finetune_step = 3; 1282 switch (param->dram_chipid) { 1283 default: 1284 case AST_DRAM_512Mx16: 1285 param->reg_AC2 = 0xAA009012 | trap_AC2; 1286 break; 1287 case AST_DRAM_1Gx16: 1288 param->reg_AC2 = 0xAA009016 | trap_AC2; 1289 break; 1290 case AST_DRAM_2Gx16: 1291 param->reg_AC2 = 0xAA009023 | trap_AC2; 1292 break; 1293 case AST_DRAM_4Gx16: 1294 param->reg_AC2 = 0xAA00903B | trap_AC2; 1295 break; 1296 } 1297 break; 1298 default: 1299 case 396: 1300 ast_moutdwm(ast, 0x1E6E2020, 0x03F1); 1301 param->wodt = 1; 1302 param->rodt = 0; 1303 param->reg_AC1 = 0x33302714; 1304 param->reg_AC2 = 0xCC00B01B | trap_AC2; 1305 param->reg_DQSIC = 0x000000E2; 1306 param->reg_MRS = 0x00000C02 | trap_MRS; 1307 param->reg_EMRS = 0x00000040; 1308 param->reg_DRV = 0x000000FA; 1309 param->reg_IOZ = 0x00000034; 1310 param->reg_DQIDLY = 0x00000089; 1311 param->reg_FREQ = 0x00005040; 1312 param->madj_max = 96; 1313 param->dll2_finetune_step = 4; 1314 1315 switch (param->dram_chipid) { 1316 case AST_DRAM_512Mx16: 1317 param->reg_AC2 = 0xCC00B016 | trap_AC2; 1318 break; 1319 default: 1320 case AST_DRAM_1Gx16: 1321 param->reg_AC2 = 0xCC00B01B | trap_AC2; 1322 break; 1323 case AST_DRAM_2Gx16: 1324 param->reg_AC2 = 0xCC00B02B | trap_AC2; 1325 break; 1326 case AST_DRAM_4Gx16: 1327 param->reg_AC2 = 0xCC00B03F | trap_AC2; 1328 break; 1329 } 1330 1331 break; 1332 1333 case 408: 1334 ast_moutdwm(ast, 0x1E6E2020, 0x01F0); 1335 param->wodt = 1; 1336 param->rodt = 0; 1337 param->reg_AC1 = 0x33302714; 1338 param->reg_AC2 = 0xCC00B01B | trap_AC2; 1339 param->reg_DQSIC = 0x000000E2; 1340 param->reg_MRS = 0x00000C02 | trap_MRS; 1341 param->reg_EMRS = 0x00000040; 1342 param->reg_DRV = 0x000000FA; 1343 param->reg_IOZ = 0x00000034; 1344 param->reg_DQIDLY = 0x00000089; 1345 param->reg_FREQ = 0x000050C0; 1346 param->madj_max = 96; 1347 param->dll2_finetune_step = 4; 1348 1349 switch (param->dram_chipid) { 1350 case AST_DRAM_512Mx16: 1351 param->reg_AC2 = 0xCC00B016 | trap_AC2; 1352 break; 1353 default: 1354 case AST_DRAM_1Gx16: 1355 param->reg_AC2 = 0xCC00B01B | trap_AC2; 1356 break; 1357 case AST_DRAM_2Gx16: 1358 param->reg_AC2 = 0xCC00B02B | trap_AC2; 1359 break; 1360 case AST_DRAM_4Gx16: 1361 param->reg_AC2 = 0xCC00B03F | trap_AC2; 1362 break; 1363 } 1364 1365 break; 1366 case 456: 1367 ast_moutdwm(ast, 0x1E6E2020, 0x0230); 1368 param->wodt = 0; 1369 param->reg_AC1 = 0x33302815; 1370 param->reg_AC2 = 0xCD44B01E; 1371 param->reg_DQSIC = 0x000000FC; 1372 param->reg_MRS = 0x00000E72; 1373 param->reg_EMRS = 0x00000000; 1374 param->reg_DRV = 0x00000000; 1375 param->reg_IOZ = 0x00000034; 1376 param->reg_DQIDLY = 0x00000097; 1377 param->reg_FREQ = 0x000052C0; 1378 param->madj_max = 88; 1379 param->dll2_finetune_step = 3; 1380 break; 1381 case 504: 1382 ast_moutdwm(ast, 0x1E6E2020, 0x0261); 1383 param->wodt = 1; 1384 param->rodt = 1; 1385 param->reg_AC1 = 0x33302815; 1386 param->reg_AC2 = 0xDE44C022; 1387 param->reg_DQSIC = 0x00000117; 1388 param->reg_MRS = 0x00000E72; 1389 param->reg_EMRS = 0x00000040; 1390 param->reg_DRV = 0x0000000A; 1391 param->reg_IOZ = 0x00000045; 1392 param->reg_DQIDLY = 0x000000A0; 1393 param->reg_FREQ = 0x000054C0; 1394 param->madj_max = 79; 1395 param->dll2_finetune_step = 3; 1396 break; 1397 case 528: 1398 ast_moutdwm(ast, 0x1E6E2020, 0x0120); 1399 param->wodt = 1; 1400 param->rodt = 1; 1401 param->reg_AC1 = 0x33302815; 1402 param->reg_AC2 = 0xEF44D024; 1403 param->reg_DQSIC = 0x00000125; 1404 param->reg_MRS = 0x00000E72; 1405 param->reg_EMRS = 0x00000004; 1406 param->reg_DRV = 0x000000F9; 1407 param->reg_IOZ = 0x00000045; 1408 param->reg_DQIDLY = 0x000000A7; 1409 param->reg_FREQ = 0x000055C0; 1410 param->madj_max = 76; 1411 param->dll2_finetune_step = 3; 1412 break; 1413 case 552: 1414 ast_moutdwm(ast, 0x1E6E2020, 0x02A1); 1415 param->wodt = 1; 1416 param->rodt = 1; 1417 param->reg_AC1 = 0x43402915; 1418 param->reg_AC2 = 0xFF44E025; 1419 param->reg_DQSIC = 0x00000132; 1420 param->reg_MRS = 0x00000E72; 1421 param->reg_EMRS = 0x00000040; 1422 param->reg_DRV = 0x0000000A; 1423 param->reg_IOZ = 0x00000045; 1424 param->reg_DQIDLY = 0x000000AD; 1425 param->reg_FREQ = 0x000056C0; 1426 param->madj_max = 76; 1427 param->dll2_finetune_step = 3; 1428 break; 1429 case 576: 1430 ast_moutdwm(ast, 0x1E6E2020, 0x0140); 1431 param->wodt = 1; 1432 param->rodt = 1; 1433 param->reg_AC1 = 0x43402915; 1434 param->reg_AC2 = 0xFF44E027; 1435 param->reg_DQSIC = 0x0000013F; 1436 param->reg_MRS = 0x00000E72; 1437 param->reg_EMRS = 0x00000004; 1438 param->reg_DRV = 0x000000F5; 1439 param->reg_IOZ = 0x00000045; 1440 param->reg_DQIDLY = 0x000000B3; 1441 param->reg_FREQ = 0x000057C0; 1442 param->madj_max = 76; 1443 param->dll2_finetune_step = 3; 1444 break; 1445 } 1446 1447 switch (param->dram_chipid) { 1448 case AST_DRAM_512Mx16: 1449 param->dram_config = 0x100; 1450 break; 1451 default: 1452 case AST_DRAM_1Gx16: 1453 param->dram_config = 0x121; 1454 break; 1455 case AST_DRAM_2Gx16: 1456 param->dram_config = 0x122; 1457 break; 1458 case AST_DRAM_4Gx16: 1459 param->dram_config = 0x123; 1460 break; 1461 } /* switch size */ 1462 1463 switch (param->vram_size) { 1464 default: 1465 case AST_VIDMEM_SIZE_8M: 1466 param->dram_config |= 0x00; 1467 break; 1468 case AST_VIDMEM_SIZE_16M: 1469 param->dram_config |= 0x04; 1470 break; 1471 case AST_VIDMEM_SIZE_32M: 1472 param->dram_config |= 0x08; 1473 break; 1474 case AST_VIDMEM_SIZE_64M: 1475 param->dram_config |= 0x0c; 1476 break; 1477 } 1478 } 1479 1480 static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param) 1481 { 1482 u32 data, data2, retry = 0; 1483 1484 ddr2_init_start: 1485 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); 1486 ast_moutdwm(ast, 0x1E6E0018, 0x00000100); 1487 ast_moutdwm(ast, 0x1E6E0024, 0x00000000); 1488 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ); 1489 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ); 1490 udelay(10); 1491 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); 1492 udelay(10); 1493 1494 ast_moutdwm(ast, 0x1E6E0004, param->dram_config); 1495 ast_moutdwm(ast, 0x1E6E0008, 0x90040f); 1496 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1); 1497 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2); 1498 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); 1499 ast_moutdwm(ast, 0x1E6E0080, 0x00000000); 1500 ast_moutdwm(ast, 0x1E6E0084, 0x00000000); 1501 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); 1502 ast_moutdwm(ast, 0x1E6E0018, 0x4000A130); 1503 ast_moutdwm(ast, 0x1E6E0018, 0x00002330); 1504 ast_moutdwm(ast, 0x1E6E0038, 0x00000000); 1505 ast_moutdwm(ast, 0x1E6E0040, 0xFF808000); 1506 ast_moutdwm(ast, 0x1E6E0044, 0x88848466); 1507 ast_moutdwm(ast, 0x1E6E0048, 0x44440008); 1508 ast_moutdwm(ast, 0x1E6E004C, 0x00000000); 1509 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); 1510 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); 1511 ast_moutdwm(ast, 0x1E6E0054, 0); 1512 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV); 1513 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ); 1514 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); 1515 ast_moutdwm(ast, 0x1E6E0074, 0x00000000); 1516 ast_moutdwm(ast, 0x1E6E0078, 0x00000000); 1517 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); 1518 1519 /* Wait MCLK2X lock to MCLK */ 1520 do { 1521 data = ast_mindwm(ast, 0x1E6E001C); 1522 } while (!(data & 0x08000000)); 1523 data = ast_mindwm(ast, 0x1E6E001C); 1524 data = (data >> 8) & 0xff; 1525 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) { 1526 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; 1527 if ((data2 & 0xff) > param->madj_max) { 1528 break; 1529 } 1530 ast_moutdwm(ast, 0x1E6E0064, data2); 1531 if (data2 & 0x00100000) { 1532 data2 = ((data2 & 0xff) >> 3) + 3; 1533 } else { 1534 data2 = ((data2 & 0xff) >> 2) + 5; 1535 } 1536 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff; 1537 data2 += data & 0xff; 1538 data = data | (data2 << 8); 1539 ast_moutdwm(ast, 0x1E6E0068, data); 1540 udelay(10); 1541 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000); 1542 udelay(10); 1543 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff; 1544 ast_moutdwm(ast, 0x1E6E0018, data); 1545 data = data | 0x200; 1546 ast_moutdwm(ast, 0x1E6E0018, data); 1547 do { 1548 data = ast_mindwm(ast, 0x1E6E001C); 1549 } while (!(data & 0x08000000)); 1550 1551 data = ast_mindwm(ast, 0x1E6E001C); 1552 data = (data >> 8) & 0xff; 1553 } 1554 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff); 1555 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00; 1556 ast_moutdwm(ast, 0x1E6E0018, data); 1557 1558 ast_moutdwm(ast, 0x1E6E0034, 0x00000001); 1559 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); 1560 udelay(50); 1561 /* Mode Register Setting */ 1562 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); 1563 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); 1564 ast_moutdwm(ast, 0x1E6E0028, 0x00000005); 1565 ast_moutdwm(ast, 0x1E6E0028, 0x00000007); 1566 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); 1567 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); 1568 1569 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08); 1570 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS); 1571 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); 1572 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380); 1573 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); 1574 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); 1575 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); 1576 1577 ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01); 1578 data = 0; 1579 if (param->wodt) { 1580 data = 0x500; 1581 } 1582 if (param->rodt) { 1583 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3); 1584 } 1585 ast_moutdwm(ast, 0x1E6E0034, data | 0x3); 1586 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ); 1587 1588 /* Calibrate the DQSI delay */ 1589 if ((cbr_dll2(ast, param) == false) && (retry++ < 10)) 1590 goto ddr2_init_start; 1591 1592 /* ECC Memory Initialization */ 1593 #ifdef ECC 1594 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); 1595 ast_moutdwm(ast, 0x1E6E0070, 0x221); 1596 do { 1597 data = ast_mindwm(ast, 0x1E6E0070); 1598 } while (!(data & 0x00001000)); 1599 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); 1600 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); 1601 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); 1602 #endif 1603 1604 } 1605 1606 static void ast_post_chip_2300(struct drm_device *dev) 1607 { 1608 struct ast_private *ast = dev->dev_private; 1609 struct ast2300_dram_param param; 1610 u32 temp; 1611 u8 reg; 1612 1613 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 1614 if ((reg & 0x80) == 0) {/* vga only */ 1615 ast_write32(ast, 0xf004, 0x1e6e0000); 1616 ast_write32(ast, 0xf000, 0x1); 1617 ast_write32(ast, 0x12000, 0x1688a8a8); 1618 do { 1619 ; 1620 } while (ast_read32(ast, 0x12000) != 0x1); 1621 1622 ast_write32(ast, 0x10000, 0xfc600309); 1623 do { 1624 ; 1625 } while (ast_read32(ast, 0x10000) != 0x1); 1626 1627 /* Slow down CPU/AHB CLK in VGA only mode */ 1628 temp = ast_read32(ast, 0x12008); 1629 temp |= 0x73; 1630 ast_write32(ast, 0x12008, temp); 1631 1632 param.dram_freq = 396; 1633 param.dram_type = AST_DDR3; 1634 temp = ast_mindwm(ast, 0x1e6e2070); 1635 if (temp & 0x01000000) 1636 param.dram_type = AST_DDR2; 1637 switch (temp & 0x18000000) { 1638 case 0: 1639 param.dram_chipid = AST_DRAM_512Mx16; 1640 break; 1641 default: 1642 case 0x08000000: 1643 param.dram_chipid = AST_DRAM_1Gx16; 1644 break; 1645 case 0x10000000: 1646 param.dram_chipid = AST_DRAM_2Gx16; 1647 break; 1648 case 0x18000000: 1649 param.dram_chipid = AST_DRAM_4Gx16; 1650 break; 1651 } 1652 switch (temp & 0x0c) { 1653 default: 1654 case 0x00: 1655 param.vram_size = AST_VIDMEM_SIZE_8M; 1656 break; 1657 1658 case 0x04: 1659 param.vram_size = AST_VIDMEM_SIZE_16M; 1660 break; 1661 1662 case 0x08: 1663 param.vram_size = AST_VIDMEM_SIZE_32M; 1664 break; 1665 1666 case 0x0c: 1667 param.vram_size = AST_VIDMEM_SIZE_64M; 1668 break; 1669 } 1670 1671 if (param.dram_type == AST_DDR3) { 1672 get_ddr3_info(ast, ¶m); 1673 ddr3_init(ast, ¶m); 1674 } else { 1675 get_ddr2_info(ast, ¶m); 1676 ddr2_init(ast, ¶m); 1677 } 1678 1679 temp = ast_mindwm(ast, 0x1e6e2040); 1680 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40); 1681 } 1682 1683 /* wait ready */ 1684 do { 1685 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 1686 } while ((reg & 0x40) == 0); 1687 } 1688 1689 static bool cbr_test_2500(struct ast_private *ast) 1690 { 1691 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF); 1692 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00); 1693 if (!mmc_test_burst(ast, 0)) 1694 return false; 1695 if (!mmc_test_single_2500(ast, 0)) 1696 return false; 1697 return true; 1698 } 1699 1700 static bool ddr_test_2500(struct ast_private *ast) 1701 { 1702 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF); 1703 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00); 1704 if (!mmc_test_burst(ast, 0)) 1705 return false; 1706 if (!mmc_test_burst(ast, 1)) 1707 return false; 1708 if (!mmc_test_burst(ast, 2)) 1709 return false; 1710 if (!mmc_test_burst(ast, 3)) 1711 return false; 1712 if (!mmc_test_single_2500(ast, 0)) 1713 return false; 1714 return true; 1715 } 1716 1717 static void ddr_init_common_2500(struct ast_private *ast) 1718 { 1719 ast_moutdwm(ast, 0x1E6E0034, 0x00020080); 1720 ast_moutdwm(ast, 0x1E6E0008, 0x2003000F); 1721 ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF); 1722 ast_moutdwm(ast, 0x1E6E0040, 0x88448844); 1723 ast_moutdwm(ast, 0x1E6E0044, 0x24422288); 1724 ast_moutdwm(ast, 0x1E6E0048, 0x22222222); 1725 ast_moutdwm(ast, 0x1E6E004C, 0x22222222); 1726 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); 1727 ast_moutdwm(ast, 0x1E6E0208, 0x00000000); 1728 ast_moutdwm(ast, 0x1E6E0218, 0x00000000); 1729 ast_moutdwm(ast, 0x1E6E0220, 0x00000000); 1730 ast_moutdwm(ast, 0x1E6E0228, 0x00000000); 1731 ast_moutdwm(ast, 0x1E6E0230, 0x00000000); 1732 ast_moutdwm(ast, 0x1E6E02A8, 0x00000000); 1733 ast_moutdwm(ast, 0x1E6E02B0, 0x00000000); 1734 ast_moutdwm(ast, 0x1E6E0240, 0x86000000); 1735 ast_moutdwm(ast, 0x1E6E0244, 0x00008600); 1736 ast_moutdwm(ast, 0x1E6E0248, 0x80000000); 1737 ast_moutdwm(ast, 0x1E6E024C, 0x80808080); 1738 } 1739 1740 static void ddr_phy_init_2500(struct ast_private *ast) 1741 { 1742 u32 data, pass, timecnt; 1743 1744 pass = 0; 1745 ast_moutdwm(ast, 0x1E6E0060, 0x00000005); 1746 while (!pass) { 1747 for (timecnt = 0; timecnt < TIMEOUT; timecnt++) { 1748 data = ast_mindwm(ast, 0x1E6E0060) & 0x1; 1749 if (!data) 1750 break; 1751 } 1752 if (timecnt != TIMEOUT) { 1753 data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000; 1754 if (!data) 1755 pass = 1; 1756 } 1757 if (!pass) { 1758 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); 1759 udelay(10); /* delay 10 us */ 1760 ast_moutdwm(ast, 0x1E6E0060, 0x00000005); 1761 } 1762 } 1763 1764 ast_moutdwm(ast, 0x1E6E0060, 0x00000006); 1765 } 1766 1767 /* 1768 * Check DRAM Size 1769 * 1Gb : 0x80000000 ~ 0x87FFFFFF 1770 * 2Gb : 0x80000000 ~ 0x8FFFFFFF 1771 * 4Gb : 0x80000000 ~ 0x9FFFFFFF 1772 * 8Gb : 0x80000000 ~ 0xBFFFFFFF 1773 */ 1774 static void check_dram_size_2500(struct ast_private *ast, u32 tRFC) 1775 { 1776 u32 reg_04, reg_14; 1777 1778 reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc; 1779 reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00; 1780 1781 ast_moutdwm(ast, 0xA0100000, 0x41424344); 1782 ast_moutdwm(ast, 0x90100000, 0x35363738); 1783 ast_moutdwm(ast, 0x88100000, 0x292A2B2C); 1784 ast_moutdwm(ast, 0x80100000, 0x1D1E1F10); 1785 1786 /* Check 8Gbit */ 1787 if (ast_mindwm(ast, 0xA0100000) == 0x41424344) { 1788 reg_04 |= 0x03; 1789 reg_14 |= (tRFC >> 24) & 0xFF; 1790 /* Check 4Gbit */ 1791 } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) { 1792 reg_04 |= 0x02; 1793 reg_14 |= (tRFC >> 16) & 0xFF; 1794 /* Check 2Gbit */ 1795 } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) { 1796 reg_04 |= 0x01; 1797 reg_14 |= (tRFC >> 8) & 0xFF; 1798 } else { 1799 reg_14 |= tRFC & 0xFF; 1800 } 1801 ast_moutdwm(ast, 0x1E6E0004, reg_04); 1802 ast_moutdwm(ast, 0x1E6E0014, reg_14); 1803 } 1804 1805 static void enable_cache_2500(struct ast_private *ast) 1806 { 1807 u32 reg_04, data; 1808 1809 reg_04 = ast_mindwm(ast, 0x1E6E0004); 1810 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000); 1811 1812 do 1813 data = ast_mindwm(ast, 0x1E6E0004); 1814 while (!(data & 0x80000)); 1815 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400); 1816 } 1817 1818 static void set_mpll_2500(struct ast_private *ast) 1819 { 1820 u32 addr, data, param; 1821 1822 /* Reset MMC */ 1823 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); 1824 ast_moutdwm(ast, 0x1E6E0034, 0x00020080); 1825 for (addr = 0x1e6e0004; addr < 0x1e6e0090;) { 1826 ast_moutdwm(ast, addr, 0x0); 1827 addr += 4; 1828 } 1829 ast_moutdwm(ast, 0x1E6E0034, 0x00020000); 1830 1831 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); 1832 data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000; 1833 if (data) { 1834 /* CLKIN = 25MHz */ 1835 param = 0x930023E0; 1836 ast_moutdwm(ast, 0x1E6E2160, 0x00011320); 1837 } else { 1838 /* CLKIN = 24MHz */ 1839 param = 0x93002400; 1840 } 1841 ast_moutdwm(ast, 0x1E6E2020, param); 1842 udelay(100); 1843 } 1844 1845 static void reset_mmc_2500(struct ast_private *ast) 1846 { 1847 ast_moutdwm(ast, 0x1E78505C, 0x00000004); 1848 ast_moutdwm(ast, 0x1E785044, 0x00000001); 1849 ast_moutdwm(ast, 0x1E785048, 0x00004755); 1850 ast_moutdwm(ast, 0x1E78504C, 0x00000013); 1851 mdelay(100); 1852 ast_moutdwm(ast, 0x1E785054, 0x00000077); 1853 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); 1854 } 1855 1856 static void ddr3_init_2500(struct ast_private *ast, const u32 *ddr_table) 1857 { 1858 1859 ast_moutdwm(ast, 0x1E6E0004, 0x00000303); 1860 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]); 1861 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]); 1862 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]); 1863 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */ 1864 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */ 1865 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ 1866 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */ 1867 1868 /* DDR PHY Setting */ 1869 ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE); 1870 ast_moutdwm(ast, 0x1E6E0204, 0x00001001); 1871 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B); 1872 ast_moutdwm(ast, 0x1E6E0210, 0x20000000); 1873 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]); 1874 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]); 1875 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]); 1876 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]); 1877 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]); 1878 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]); 1879 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]); 1880 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]); 1881 ast_moutdwm(ast, 0x1E6E0290, 0x00100008); 1882 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006); 1883 1884 /* Controller Setting */ 1885 ast_moutdwm(ast, 0x1E6E0034, 0x00020091); 1886 1887 /* Wait DDR PHY init done */ 1888 ddr_phy_init_2500(ast); 1889 1890 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]); 1891 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81); 1892 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93); 1893 1894 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]); 1895 enable_cache_2500(ast); 1896 ast_moutdwm(ast, 0x1E6E001C, 0x00000008); 1897 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00); 1898 } 1899 1900 static void ddr4_init_2500(struct ast_private *ast, const u32 *ddr_table) 1901 { 1902 u32 data, data2, pass, retrycnt; 1903 u32 ddr_vref, phy_vref; 1904 u32 min_ddr_vref = 0, min_phy_vref = 0; 1905 u32 max_ddr_vref = 0, max_phy_vref = 0; 1906 1907 ast_moutdwm(ast, 0x1E6E0004, 0x00000313); 1908 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]); 1909 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]); 1910 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]); 1911 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */ 1912 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */ 1913 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ 1914 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */ 1915 1916 /* DDR PHY Setting */ 1917 ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE); 1918 ast_moutdwm(ast, 0x1E6E0204, 0x09002000); 1919 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B); 1920 ast_moutdwm(ast, 0x1E6E0210, 0x20000000); 1921 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]); 1922 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]); 1923 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]); 1924 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]); 1925 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]); 1926 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]); 1927 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]); 1928 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]); 1929 ast_moutdwm(ast, 0x1E6E0290, 0x00100008); 1930 ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C); 1931 ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E); 1932 1933 /* Controller Setting */ 1934 ast_moutdwm(ast, 0x1E6E0034, 0x0001A991); 1935 1936 /* Train PHY Vref first */ 1937 pass = 0; 1938 1939 for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) { 1940 max_phy_vref = 0x0; 1941 pass = 0; 1942 ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06); 1943 for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) { 1944 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); 1945 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); 1946 ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8)); 1947 /* Fire DFI Init */ 1948 ddr_phy_init_2500(ast); 1949 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); 1950 if (cbr_test_2500(ast)) { 1951 pass++; 1952 data = ast_mindwm(ast, 0x1E6E03D0); 1953 data2 = data >> 8; 1954 data = data & 0xff; 1955 if (data > data2) 1956 data = data2; 1957 if (max_phy_vref < data) { 1958 max_phy_vref = data; 1959 min_phy_vref = phy_vref; 1960 } 1961 } else if (pass > 0) 1962 break; 1963 } 1964 } 1965 ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8)); 1966 1967 /* Train DDR Vref next */ 1968 pass = 0; 1969 1970 for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) { 1971 min_ddr_vref = 0xFF; 1972 max_ddr_vref = 0x0; 1973 pass = 0; 1974 for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) { 1975 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); 1976 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); 1977 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8)); 1978 /* Fire DFI Init */ 1979 ddr_phy_init_2500(ast); 1980 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); 1981 if (cbr_test_2500(ast)) { 1982 pass++; 1983 if (min_ddr_vref > ddr_vref) 1984 min_ddr_vref = ddr_vref; 1985 if (max_ddr_vref < ddr_vref) 1986 max_ddr_vref = ddr_vref; 1987 } else if (pass != 0) 1988 break; 1989 } 1990 } 1991 1992 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); 1993 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); 1994 ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1; 1995 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8)); 1996 1997 /* Wait DDR PHY init done */ 1998 ddr_phy_init_2500(ast); 1999 2000 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]); 2001 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81); 2002 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93); 2003 2004 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]); 2005 enable_cache_2500(ast); 2006 ast_moutdwm(ast, 0x1E6E001C, 0x00000008); 2007 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00); 2008 } 2009 2010 static bool ast_dram_init_2500(struct ast_private *ast) 2011 { 2012 u32 data; 2013 u32 max_tries = 5; 2014 2015 do { 2016 if (max_tries-- == 0) 2017 return false; 2018 set_mpll_2500(ast); 2019 reset_mmc_2500(ast); 2020 ddr_init_common_2500(ast); 2021 2022 data = ast_mindwm(ast, 0x1E6E2070); 2023 if (data & 0x01000000) 2024 ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table); 2025 else 2026 ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table); 2027 } while (!ddr_test_2500(ast)); 2028 2029 ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41); 2030 2031 /* Patch code */ 2032 data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF; 2033 ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000); 2034 2035 return true; 2036 } 2037 2038 void ast_post_chip_2500(struct drm_device *dev) 2039 { 2040 struct ast_private *ast = dev->dev_private; 2041 u32 temp; 2042 u8 reg; 2043 2044 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 2045 if ((reg & 0x80) == 0) {/* vga only */ 2046 /* Clear bus lock condition */ 2047 ast_moutdwm(ast, 0x1e600000, 0xAEED1A03); 2048 ast_moutdwm(ast, 0x1e600084, 0x00010000); 2049 ast_moutdwm(ast, 0x1e600088, 0x00000000); 2050 ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); 2051 ast_write32(ast, 0xf004, 0x1e6e0000); 2052 ast_write32(ast, 0xf000, 0x1); 2053 ast_write32(ast, 0x12000, 0x1688a8a8); 2054 while (ast_read32(ast, 0x12000) != 0x1) 2055 ; 2056 2057 ast_write32(ast, 0x10000, 0xfc600309); 2058 while (ast_read32(ast, 0x10000) != 0x1) 2059 ; 2060 2061 /* Slow down CPU/AHB CLK in VGA only mode */ 2062 temp = ast_read32(ast, 0x12008); 2063 temp |= 0x73; 2064 ast_write32(ast, 0x12008, temp); 2065 2066 /* Reset USB port to patch USB unknown device issue */ 2067 ast_moutdwm(ast, 0x1e6e2090, 0x20000000); 2068 temp = ast_mindwm(ast, 0x1e6e2094); 2069 temp |= 0x00004000; 2070 ast_moutdwm(ast, 0x1e6e2094, temp); 2071 temp = ast_mindwm(ast, 0x1e6e2070); 2072 if (temp & 0x00800000) { 2073 ast_moutdwm(ast, 0x1e6e207c, 0x00800000); 2074 mdelay(100); 2075 ast_moutdwm(ast, 0x1e6e2070, 0x00800000); 2076 } 2077 2078 if (!ast_dram_init_2500(ast)) 2079 DRM_ERROR("DRAM init failed !\n"); 2080 2081 temp = ast_mindwm(ast, 0x1e6e2040); 2082 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40); 2083 } 2084 2085 /* wait ready */ 2086 do { 2087 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 2088 } while ((reg & 0x40) == 0); 2089 } 2090
Indexes created Wed Sep 24 15:09:51 GMT 2025