1 /* $NetBSD: gem.c,v 1.139 2025/04/27 16:03:16 gson Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * Copyright (c) 2001-2003 Thomas Moestl 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 35 * See `GEM Gigabit Ethernet ASIC Specification' 36 * https://web.archive.org/web/20090701010806/http://www.sun.com/processors/manuals/ge.pdf 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.139 2025/04/27 16:03:16 gson Exp $"); 41 42 #include "opt_inet.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/callout.h> 47 #include <sys/mbuf.h> 48 #include <sys/syslog.h> 49 #include <sys/kernel.h> 50 #include <sys/socket.h> 51 #include <sys/ioctl.h> 52 #include <sys/errno.h> 53 #include <sys/device.h> 54 55 #include <machine/endian.h> 56 57 #include <net/if.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_ether.h> 61 62 #ifdef INET 63 #include <netinet/in.h> 64 #include <netinet/in_systm.h> 65 #include <netinet/in_var.h> 66 #include <netinet/ip.h> 67 #include <netinet/tcp.h> 68 #include <netinet/udp.h> 69 #endif 70 71 #include <net/bpf.h> 72 73 #include <sys/bus.h> 74 #include <sys/intr.h> 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 #include <dev/mii/mii_bitbang.h> 79 80 #include <dev/ic/gemreg.h> 81 #include <dev/ic/gemvar.h> 82 83 #define TRIES 10000 84 85 static void gem_inten(struct gem_softc *); 86 static void gem_start(struct ifnet *); 87 static void gem_stop(struct ifnet *, int); 88 int gem_ioctl(struct ifnet *, u_long, void *); 89 void gem_tick(void *); 90 void gem_watchdog(struct ifnet *); 91 void gem_rx_watchdog(void *); 92 void gem_pcs_start(struct gem_softc *sc); 93 void gem_pcs_stop(struct gem_softc *sc, int); 94 int gem_init(struct ifnet *); 95 void gem_init_regs(struct gem_softc *sc); 96 static int gem_ringsize(int sz); 97 static int gem_meminit(struct gem_softc *); 98 void gem_mifinit(struct gem_softc *); 99 static int gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int, 100 uint32_t, uint32_t); 101 void gem_reset(struct gem_softc *); 102 int gem_reset_rx(struct gem_softc *sc); 103 static void gem_reset_rxdma(struct gem_softc *sc); 104 static void gem_rx_common(struct gem_softc *sc); 105 int gem_reset_tx(struct gem_softc *sc); 106 int gem_disable_rx(struct gem_softc *sc); 107 int gem_disable_tx(struct gem_softc *sc); 108 static void gem_rxdrain(struct gem_softc *sc); 109 int gem_add_rxbuf(struct gem_softc *sc, int idx); 110 void gem_setladrf(struct gem_softc *); 111 112 /* MII methods & callbacks */ 113 static int gem_mii_readreg(device_t, int, int, uint16_t *); 114 static int gem_mii_writereg(device_t, int, int, uint16_t); 115 static void gem_mii_statchg(struct ifnet *); 116 117 static int gem_ifflags_cb(struct ethercom *); 118 119 void gem_statuschange(struct gem_softc *); 120 121 int gem_ser_mediachange(struct ifnet *); 122 void gem_ser_mediastatus(struct ifnet *, struct ifmediareq *); 123 124 static void gem_partial_detach(struct gem_softc *, enum gem_attach_stage); 125 126 struct mbuf *gem_get(struct gem_softc *, int, int); 127 int gem_put(struct gem_softc *, int, struct mbuf *); 128 void gem_read(struct gem_softc *, int, int); 129 int gem_pint(struct gem_softc *); 130 int gem_eint(struct gem_softc *, u_int); 131 int gem_rint(struct gem_softc *); 132 int gem_tint(struct gem_softc *); 133 void gem_power(int, void *); 134 135 #ifdef GEM_DEBUG 136 static void gem_txsoft_print(const struct gem_softc *, int, int); 137 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 138 printf x 139 #else 140 #define DPRINTF(sc, x) /* nothing */ 141 #endif 142 143 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 144 145 int 146 gem_detach(struct gem_softc *sc, int flags) 147 { 148 int i; 149 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 150 bus_space_tag_t t = sc->sc_bustag; 151 bus_space_handle_t h = sc->sc_h1; 152 153 /* 154 * Free any resources we've allocated during the attach. 155 * Do this in reverse order and fall through. 156 */ 157 switch (sc->sc_att_stage) { 158 case GEM_ATT_BACKEND_2: 159 case GEM_ATT_BACKEND_1: 160 case GEM_ATT_FINISHED: 161 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 162 gem_stop(&sc->sc_ethercom.ec_if, 1); 163 164 #ifdef GEM_COUNTERS 165 for (i = __arraycount(sc->sc_ev_rxhist); --i >= 0; ) 166 evcnt_detach(&sc->sc_ev_rxhist[i]); 167 evcnt_detach(&sc->sc_ev_rxnobuf); 168 evcnt_detach(&sc->sc_ev_rxfull); 169 evcnt_detach(&sc->sc_ev_rxint); 170 evcnt_detach(&sc->sc_ev_txint); 171 evcnt_detach(&sc->sc_ev_rxoverflow); 172 #endif 173 evcnt_detach(&sc->sc_ev_intr); 174 175 rnd_detach_source(&sc->rnd_source); 176 ether_ifdetach(ifp); 177 if_detach(ifp); 178 179 callout_destroy(&sc->sc_tick_ch); 180 callout_destroy(&sc->sc_rx_watchdog); 181 182 /*FALLTHROUGH*/ 183 case GEM_ATT_MII: 184 sc->sc_att_stage = GEM_ATT_MII; 185 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 186 ifmedia_fini(&sc->sc_mii.mii_media); 187 188 /*FALLTHROUGH*/ 189 case GEM_ATT_7: 190 for (i = 0; i < GEM_NRXDESC; i++) { 191 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 192 bus_dmamap_destroy(sc->sc_dmatag, 193 sc->sc_rxsoft[i].rxs_dmamap); 194 } 195 /*FALLTHROUGH*/ 196 case GEM_ATT_6: 197 for (i = 0; i < GEM_TXQUEUELEN; i++) { 198 if (sc->sc_txsoft[i].txs_dmamap != NULL) 199 bus_dmamap_destroy(sc->sc_dmatag, 200 sc->sc_txsoft[i].txs_dmamap); 201 } 202 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 203 /*FALLTHROUGH*/ 204 case GEM_ATT_5: 205 bus_dmamap_unload(sc->sc_dmatag, sc->sc_nulldmamap); 206 /*FALLTHROUGH*/ 207 case GEM_ATT_4: 208 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 209 /*FALLTHROUGH*/ 210 case GEM_ATT_3: 211 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 212 /*FALLTHROUGH*/ 213 case GEM_ATT_2: 214 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 215 sizeof(struct gem_control_data)); 216 /*FALLTHROUGH*/ 217 case GEM_ATT_1: 218 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 219 /*FALLTHROUGH*/ 220 case GEM_ATT_0: 221 sc->sc_att_stage = GEM_ATT_0; 222 /*FALLTHROUGH*/ 223 case GEM_ATT_BACKEND_0: 224 break; 225 } 226 return 0; 227 } 228 229 static void 230 gem_partial_detach(struct gem_softc *sc, enum gem_attach_stage stage) 231 { 232 cfattach_t ca = device_cfattach(sc->sc_dev); 233 234 sc->sc_att_stage = stage; 235 (*ca->ca_detach)(sc->sc_dev, 0); 236 } 237 238 /* 239 * gem_attach: 240 * 241 * Attach a Gem interface to the system. 242 */ 243 void 244 gem_attach(struct gem_softc *sc, const uint8_t *enaddr) 245 { 246 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 247 struct mii_data *mii = &sc->sc_mii; 248 bus_space_tag_t t = sc->sc_bustag; 249 bus_space_handle_t h = sc->sc_h1; 250 struct ifmedia_entry *ife; 251 int i, error, phyaddr; 252 uint32_t v; 253 char *nullbuf; 254 255 /* Make sure the chip is stopped. */ 256 ifp->if_softc = sc; 257 gem_reset(sc); 258 259 /* 260 * Allocate the control data structures, and create and load the 261 * DMA map for it. gem_control_data is 9216 bytes, we have space for 262 * the padding buffer in the bus_dmamem_alloc()'d memory. 263 */ 264 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 265 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 266 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 267 aprint_error_dev(sc->sc_dev, 268 "unable to allocate control data, error = %d\n", 269 error); 270 gem_partial_detach(sc, GEM_ATT_0); 271 return; 272 } 273 274 /* XXX should map this in with correct endianness */ 275 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 276 sizeof(struct gem_control_data), (void **)&sc->sc_control_data, 277 BUS_DMA_COHERENT)) != 0) { 278 aprint_error_dev(sc->sc_dev, 279 "unable to map control data, error = %d\n", error); 280 gem_partial_detach(sc, GEM_ATT_1); 281 return; 282 } 283 284 nullbuf = 285 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 286 287 if ((error = bus_dmamap_create(sc->sc_dmatag, 288 sizeof(struct gem_control_data), 1, 289 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 290 aprint_error_dev(sc->sc_dev, 291 "unable to create control data DMA map, error = %d\n", 292 error); 293 gem_partial_detach(sc, GEM_ATT_2); 294 return; 295 } 296 297 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 298 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 299 0)) != 0) { 300 aprint_error_dev(sc->sc_dev, 301 "unable to load control data DMA map, error = %d\n", 302 error); 303 gem_partial_detach(sc, GEM_ATT_3); 304 return; 305 } 306 307 memset(nullbuf, 0, ETHER_MIN_TX); 308 if ((error = bus_dmamap_create(sc->sc_dmatag, 309 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 310 aprint_error_dev(sc->sc_dev, 311 "unable to create padding DMA map, error = %d\n", error); 312 gem_partial_detach(sc, GEM_ATT_4); 313 return; 314 } 315 316 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 317 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 318 aprint_error_dev(sc->sc_dev, 319 "unable to load padding DMA map, error = %d\n", error); 320 gem_partial_detach(sc, GEM_ATT_5); 321 return; 322 } 323 324 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 325 BUS_DMASYNC_PREWRITE); 326 327 /* 328 * Initialize the transmit job descriptors. 329 */ 330 SIMPLEQ_INIT(&sc->sc_txfreeq); 331 SIMPLEQ_INIT(&sc->sc_txdirtyq); 332 333 /* 334 * Create the transmit buffer DMA maps. 335 */ 336 for (i = 0; i < GEM_TXQUEUELEN; i++) { 337 struct gem_txsoft *txs; 338 339 txs = &sc->sc_txsoft[i]; 340 txs->txs_mbuf = NULL; 341 if ((error = bus_dmamap_create(sc->sc_dmatag, 342 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 343 ETHER_MAX_LEN_JUMBO, 0, 0, 344 &txs->txs_dmamap)) != 0) { 345 aprint_error_dev(sc->sc_dev, 346 "unable to create tx DMA map %d, error = %d\n", 347 i, error); 348 gem_partial_detach(sc, GEM_ATT_6); 349 return; 350 } 351 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 352 } 353 354 /* 355 * Create the receive buffer DMA maps. 356 */ 357 for (i = 0; i < GEM_NRXDESC; i++) { 358 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 359 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 360 aprint_error_dev(sc->sc_dev, 361 "unable to create rx DMA map %d, error = %d\n", 362 i, error); 363 gem_partial_detach(sc, GEM_ATT_7); 364 return; 365 } 366 sc->sc_rxsoft[i].rxs_mbuf = NULL; 367 } 368 369 /* Initialize ifmedia structures and MII info */ 370 mii->mii_ifp = ifp; 371 mii->mii_readreg = gem_mii_readreg; 372 mii->mii_writereg = gem_mii_writereg; 373 mii->mii_statchg = gem_mii_statchg; 374 375 sc->sc_ethercom.ec_mii = mii; 376 377 /* 378 * Initialization based on `GEM Gigabit Ethernet ASIC Specification' 379 * Section 3.2.1 `Initialization Sequence'. 380 * However, we can't assume SERDES or Serialink if neither 381 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set 382 * being set, as both are set on Sun X1141A (with SERDES). So, 383 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL. 384 * Also, for variants that report 2 PHY's, we prefer the external 385 * PHY over the internal PHY, so we look for that first. 386 */ 387 gem_mifinit(sc); 388 389 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 390 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 391 ether_mediastatus); 392 /* Look for external PHY */ 393 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 394 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 395 bus_space_write_4(t, h, GEM_MIF_CONFIG, 396 sc->sc_mif_config); 397 switch (sc->sc_variant) { 398 case GEM_SUN_ERI: 399 phyaddr = GEM_PHYAD_EXTERNAL; 400 break; 401 default: 402 phyaddr = MII_PHY_ANY; 403 break; 404 } 405 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 406 MII_OFFSET_ANY, MIIF_FORCEANEG); 407 } 408 #ifdef GEM_DEBUG 409 else 410 aprint_debug_dev(sc->sc_dev, "using external PHY\n"); 411 #endif 412 /* Look for internal PHY if no external PHY was found */ 413 if (LIST_EMPTY(&mii->mii_phys) && 414 ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI0) || 415 (sc->sc_variant == GEM_APPLE_K2_GMAC))) { 416 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 417 bus_space_write_4(t, h, GEM_MIF_CONFIG, 418 sc->sc_mif_config); 419 switch (sc->sc_variant) { 420 case GEM_SUN_ERI: 421 case GEM_APPLE_K2_GMAC: 422 phyaddr = GEM_PHYAD_INTERNAL; 423 break; 424 case GEM_APPLE_GMAC: 425 phyaddr = GEM_PHYAD_EXTERNAL; 426 break; 427 default: 428 phyaddr = MII_PHY_ANY; 429 break; 430 } 431 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 432 MII_OFFSET_ANY, MIIF_FORCEANEG); 433 #ifdef GEM_DEBUG 434 if (!LIST_EMPTY(&mii->mii_phys)) 435 aprint_debug_dev(sc->sc_dev, 436 "using internal PHY\n"); 437 #endif 438 } 439 if (LIST_EMPTY(&mii->mii_phys)) { 440 /* No PHY attached */ 441 aprint_error_dev(sc->sc_dev, 442 "PHY probe failed\n"); 443 gem_partial_detach(sc, GEM_ATT_MII); 444 return; 445 } else { 446 struct mii_softc *child; 447 448 /* 449 * Walk along the list of attached MII devices and 450 * establish an `MII instance' to `PHY number' 451 * mapping. 452 */ 453 LIST_FOREACH(child, &mii->mii_phys, mii_list) { 454 /* 455 * Note: we support just one PHY: the internal 456 * or external MII is already selected for us 457 * by the GEM_MIF_CONFIG register. 458 */ 459 if (child->mii_phy > 1 || child->mii_inst > 0) { 460 aprint_error_dev(sc->sc_dev, 461 "cannot accommodate MII device" 462 " %s at PHY %d, instance %d\n", 463 device_xname(child->mii_dev), 464 child->mii_phy, child->mii_inst); 465 continue; 466 } 467 sc->sc_phys[child->mii_inst] = child->mii_phy; 468 } 469 470 if (sc->sc_variant != GEM_SUN_ERI) 471 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 472 GEM_MII_DATAPATH_MII); 473 474 /* 475 * XXX - we can really do the following ONLY if the 476 * PHY indeed has the auto negotiation capability!! 477 */ 478 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 479 } 480 } else { 481 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange, 482 gem_ser_mediastatus); 483 /* SERDES or Serialink */ 484 if (sc->sc_flags & GEM_SERDES) { 485 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 486 GEM_MII_DATAPATH_SERDES); 487 } else { 488 sc->sc_flags |= GEM_SERIAL; 489 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 490 GEM_MII_DATAPATH_SERIAL); 491 } 492 493 aprint_normal_dev(sc->sc_dev, "using external PCS %s: ", 494 sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink"); 495 496 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_AUTO, 0, NULL); 497 /* Check for FDX and HDX capabilities */ 498 sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR); 499 if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) { 500 ifmedia_add(&mii->mii_media, IFM_ETHER | 501 IFM_1000_SX | IFM_MANUAL | IFM_FDX, 0, NULL); 502 aprint_normal("1000baseSX-FDX, "); 503 } 504 if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) { 505 ifmedia_add(&mii->mii_media, IFM_ETHER | 506 IFM_1000_SX | IFM_MANUAL | IFM_HDX, 0, NULL); 507 aprint_normal("1000baseSX-HDX, "); 508 } 509 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 510 sc->sc_mii_media = IFM_AUTO; 511 aprint_normal("auto\n"); 512 513 gem_pcs_stop(sc, 1); 514 } 515 516 /* 517 * From this point forward, the attachment cannot fail. A failure 518 * before this point releases all resources that may have been 519 * allocated. 520 */ 521 522 /* Announce ourselves. */ 523 aprint_normal_dev(sc->sc_dev, "Ethernet address %s", 524 ether_sprintf(enaddr)); 525 526 /* Get RX FIFO size */ 527 sc->sc_rxfifosize = 64 * 528 bus_space_read_4(t, h, GEM_RX_FIFO_SIZE); 529 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 530 531 /* Get TX FIFO size */ 532 v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE); 533 aprint_normal(", %uKB TX fifo\n", v / 16); 534 535 /* Initialize ifnet structure. */ 536 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 537 ifp->if_softc = sc; 538 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 539 sc->sc_if_flags = ifp->if_flags; 540 #if 0 541 /* 542 * The GEM hardware supports basic TCP checksum offloading only. 543 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80) 544 * have bugs in the receive checksum, so don't enable it for now. 545 */ 546 if ((GEM_IS_SUN(sc) && sc->sc_chiprev != 1) || 547 (GEM_IS_APPLE(sc) && 548 (sc->sc_chiprev != 0 && sc->sc_chiprev != 0x80))) 549 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 550 #endif 551 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 552 ifp->if_start = gem_start; 553 ifp->if_ioctl = gem_ioctl; 554 ifp->if_watchdog = gem_watchdog; 555 ifp->if_stop = gem_stop; 556 ifp->if_init = gem_init; 557 IFQ_SET_READY(&ifp->if_snd); 558 559 /* 560 * If we support GigE media, we support jumbo frames too. 561 * Unless we are Apple. 562 */ 563 TAILQ_FOREACH(ife, &mii->mii_media.ifm_list, ifm_list) { 564 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T || 565 IFM_SUBTYPE(ife->ifm_media) == IFM_1000_SX || 566 IFM_SUBTYPE(ife->ifm_media) == IFM_1000_LX || 567 IFM_SUBTYPE(ife->ifm_media) == IFM_1000_CX) { 568 if (!GEM_IS_APPLE(sc)) 569 sc->sc_ethercom.ec_capabilities 570 |= ETHERCAP_JUMBO_MTU; 571 sc->sc_flags |= GEM_GIGABIT; 572 break; 573 } 574 } 575 576 /* claim 802.1q capability */ 577 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 578 579 /* Attach the interface. */ 580 if_attach(ifp); 581 if_deferred_start_init(ifp, NULL); 582 ether_ifattach(ifp, enaddr); 583 ether_set_ifflags_cb(&sc->sc_ethercom, gem_ifflags_cb); 584 585 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 586 RND_TYPE_NET, RND_FLAG_DEFAULT); 587 588 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 589 NULL, device_xname(sc->sc_dev), "interrupts"); 590 #ifdef GEM_COUNTERS 591 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 592 &sc->sc_ev_intr, device_xname(sc->sc_dev), "tx interrupts"); 593 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 594 &sc->sc_ev_intr, device_xname(sc->sc_dev), "rx interrupts"); 595 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 596 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx ring full"); 597 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 598 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx malloc failure"); 599 evcnt_attach_dynamic(&sc->sc_ev_rxoverflow, EVCNT_TYPE_INTR, 600 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx overflow"); 601 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 602 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 0desc"); 603 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 604 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 1desc"); 605 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 606 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 2desc"); 607 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 608 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 3desc"); 609 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 610 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >3desc"); 611 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 612 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >7desc"); 613 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 614 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >15desc"); 615 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 616 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >31desc"); 617 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 618 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >63desc"); 619 #endif 620 621 callout_init(&sc->sc_tick_ch, 0); 622 callout_setfunc(&sc->sc_tick_ch, gem_tick, sc); 623 624 callout_init(&sc->sc_rx_watchdog, 0); 625 callout_setfunc(&sc->sc_rx_watchdog, gem_rx_watchdog, sc); 626 627 sc->sc_att_stage = GEM_ATT_FINISHED; 628 629 return; 630 } 631 632 void 633 gem_tick(void *arg) 634 { 635 struct gem_softc *sc = arg; 636 int s; 637 638 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) { 639 /* 640 * We have to reset everything if we failed to get a 641 * PCS interrupt. Restarting the callout is handled 642 * in gem_pcs_start(). 643 */ 644 gem_init(&sc->sc_ethercom.ec_if); 645 } else { 646 s = splnet(); 647 mii_tick(&sc->sc_mii); 648 splx(s); 649 callout_schedule(&sc->sc_tick_ch, hz); 650 } 651 } 652 653 static int 654 gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r, uint32_t clr, 655 uint32_t set) 656 { 657 int i; 658 uint32_t reg; 659 660 for (i = TRIES; i--; DELAY(100)) { 661 reg = bus_space_read_4(sc->sc_bustag, h, r); 662 if ((reg & clr) == 0 && (reg & set) == set) 663 return (1); 664 } 665 return (0); 666 } 667 668 void 669 gem_reset(struct gem_softc *sc) 670 { 671 bus_space_tag_t t = sc->sc_bustag; 672 bus_space_handle_t h = sc->sc_h2; 673 int s; 674 675 s = splnet(); 676 DPRINTF(sc, ("%s: gem_reset\n", device_xname(sc->sc_dev))); 677 gem_reset_rx(sc); 678 gem_reset_tx(sc); 679 680 /* Do a full reset */ 681 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX); 682 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 683 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 684 splx(s); 685 } 686 687 688 /* 689 * gem_rxdrain: 690 * 691 * Drain the receive queue. 692 */ 693 static void 694 gem_rxdrain(struct gem_softc *sc) 695 { 696 struct gem_rxsoft *rxs; 697 int i; 698 699 for (i = 0; i < GEM_NRXDESC; i++) { 700 rxs = &sc->sc_rxsoft[i]; 701 if (rxs->rxs_mbuf != NULL) { 702 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 703 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 704 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 705 m_freem(rxs->rxs_mbuf); 706 rxs->rxs_mbuf = NULL; 707 } 708 } 709 } 710 711 /* 712 * Reset the whole thing. 713 */ 714 static void 715 gem_stop(struct ifnet *ifp, int disable) 716 { 717 struct gem_softc *sc = ifp->if_softc; 718 struct gem_txsoft *txs; 719 720 DPRINTF(sc, ("%s: gem_stop\n", device_xname(sc->sc_dev))); 721 722 callout_halt(&sc->sc_tick_ch, NULL); 723 callout_halt(&sc->sc_rx_watchdog, NULL); 724 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 725 gem_pcs_stop(sc, disable); 726 else 727 mii_down(&sc->sc_mii); 728 729 /* XXX - Should we reset these instead? */ 730 gem_disable_tx(sc); 731 gem_disable_rx(sc); 732 733 /* 734 * Release any queued transmit buffers. 735 */ 736 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 737 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 738 if (txs->txs_mbuf != NULL) { 739 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 740 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 741 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 742 m_freem(txs->txs_mbuf); 743 txs->txs_mbuf = NULL; 744 } 745 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 746 } 747 748 /* 749 * Mark the interface down and cancel the watchdog timer. 750 */ 751 ifp->if_flags &= ~IFF_RUNNING; 752 sc->sc_if_flags = ifp->if_flags; 753 ifp->if_timer = 0; 754 755 if (disable) 756 gem_rxdrain(sc); 757 } 758 759 760 /* 761 * Reset the receiver 762 */ 763 int 764 gem_reset_rx(struct gem_softc *sc) 765 { 766 bus_space_tag_t t = sc->sc_bustag; 767 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 768 769 /* 770 * Resetting while DMA is in progress can cause a bus hang, so we 771 * disable DMA first. 772 */ 773 gem_disable_rx(sc); 774 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 775 bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 776 /* Wait till it finishes */ 777 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 778 aprint_error_dev(sc->sc_dev, "cannot disable rx dma\n"); 779 /* Wait 5ms extra. */ 780 delay(5000); 781 782 /* Finally, reset the ERX */ 783 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 784 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 785 /* Wait till it finishes */ 786 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 787 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 788 return (1); 789 } 790 return (0); 791 } 792 793 794 /* 795 * Reset the receiver DMA engine. 796 * 797 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 798 * etc in order to reset the receiver DMA engine only and not do a full 799 * reset which amongst others also downs the link and clears the FIFOs. 800 */ 801 static void 802 gem_reset_rxdma(struct gem_softc *sc) 803 { 804 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 805 bus_space_tag_t t = sc->sc_bustag; 806 bus_space_handle_t h = sc->sc_h1; 807 int i; 808 809 if (gem_reset_rx(sc) != 0) { 810 gem_init(ifp); 811 return; 812 } 813 for (i = 0; i < GEM_NRXDESC; i++) 814 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 815 GEM_UPDATE_RXDESC(sc, i); 816 sc->sc_rxptr = 0; 817 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 818 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 819 820 /* Reprogram Descriptor Ring Base Addresses */ 821 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 822 ((uint64_t)GEM_CDRXADDR(sc, 0)) >> 32); 823 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 824 825 /* Redo ERX Configuration */ 826 gem_rx_common(sc); 827 828 /* Give the receiver a swift kick */ 829 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4); 830 } 831 832 /* 833 * Common RX configuration for gem_init() and gem_reset_rxdma(). 834 */ 835 static void 836 gem_rx_common(struct gem_softc *sc) 837 { 838 bus_space_tag_t t = sc->sc_bustag; 839 bus_space_handle_t h = sc->sc_h1; 840 uint32_t v; 841 842 /* Encode Receive Descriptor ring size: four possible values */ 843 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 844 845 /* Set receive h/w checksum offset */ 846 #ifdef INET 847 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 848 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 849 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 850 #endif 851 852 /* Enable RX DMA */ 853 bus_space_write_4(t, h, GEM_RX_CONFIG, 854 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 855 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN); 856 857 /* 858 * The following value is for an OFF Threshold of about 3/4 full 859 * and an ON Threshold of 1/4 full. 860 */ 861 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 862 (3 * sc->sc_rxfifosize / 256) | 863 ((sc->sc_rxfifosize / 256) << 12)); 864 bus_space_write_4(t, h, GEM_RX_BLANKING, 865 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 8); 866 } 867 868 /* 869 * Reset the transmitter 870 */ 871 int 872 gem_reset_tx(struct gem_softc *sc) 873 { 874 bus_space_tag_t t = sc->sc_bustag; 875 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 876 877 /* 878 * Resetting while DMA is in progress can cause a bus hang, so we 879 * disable DMA first. 880 */ 881 gem_disable_tx(sc); 882 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 883 bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 884 /* Wait till it finishes */ 885 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 886 aprint_error_dev(sc->sc_dev, "cannot disable tx dma\n"); 887 /* Wait 5ms extra. */ 888 delay(5000); 889 890 /* Finally, reset the ETX */ 891 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 892 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 893 /* Wait till it finishes */ 894 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 895 aprint_error_dev(sc->sc_dev, "cannot reset transmitter\n"); 896 return (1); 897 } 898 return (0); 899 } 900 901 /* 902 * disable receiver. 903 */ 904 int 905 gem_disable_rx(struct gem_softc *sc) 906 { 907 bus_space_tag_t t = sc->sc_bustag; 908 bus_space_handle_t h = sc->sc_h1; 909 uint32_t cfg; 910 911 /* Flip the enable bit */ 912 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 913 cfg &= ~GEM_MAC_RX_ENABLE; 914 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 915 bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 916 /* Wait for it to finish */ 917 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 918 } 919 920 /* 921 * disable transmitter. 922 */ 923 int 924 gem_disable_tx(struct gem_softc *sc) 925 { 926 bus_space_tag_t t = sc->sc_bustag; 927 bus_space_handle_t h = sc->sc_h1; 928 uint32_t cfg; 929 930 /* Flip the enable bit */ 931 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 932 cfg &= ~GEM_MAC_TX_ENABLE; 933 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 934 bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 935 /* Wait for it to finish */ 936 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 937 } 938 939 /* 940 * Initialize interface. 941 */ 942 int 943 gem_meminit(struct gem_softc *sc) 944 { 945 struct gem_rxsoft *rxs; 946 int i, error; 947 948 /* 949 * Initialize the transmit descriptor ring. 950 */ 951 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 952 for (i = 0; i < GEM_NTXDESC; i++) { 953 sc->sc_txdescs[i].gd_flags = 0; 954 sc->sc_txdescs[i].gd_addr = 0; 955 } 956 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 957 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 958 sc->sc_txfree = GEM_NTXDESC-1; 959 sc->sc_txnext = 0; 960 sc->sc_txwin = 0; 961 962 /* 963 * Initialize the receive descriptor and receive job 964 * descriptor rings. 965 */ 966 for (i = 0; i < GEM_NRXDESC; i++) { 967 rxs = &sc->sc_rxsoft[i]; 968 if (rxs->rxs_mbuf == NULL) { 969 if ((error = gem_add_rxbuf(sc, i)) != 0) { 970 aprint_error_dev(sc->sc_dev, 971 "unable to allocate or map rx " 972 "buffer %d, error = %d\n", 973 i, error); 974 /* 975 * XXX Should attempt to run with fewer receive 976 * XXX buffers instead of just failing. 977 */ 978 gem_rxdrain(sc); 979 return (1); 980 } 981 } else 982 GEM_INIT_RXDESC(sc, i); 983 } 984 sc->sc_rxptr = 0; 985 sc->sc_meminited = 1; 986 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 987 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 988 989 return (0); 990 } 991 992 static int 993 gem_ringsize(int sz) 994 { 995 switch (sz) { 996 case 32: 997 return GEM_RING_SZ_32; 998 case 64: 999 return GEM_RING_SZ_64; 1000 case 128: 1001 return GEM_RING_SZ_128; 1002 case 256: 1003 return GEM_RING_SZ_256; 1004 case 512: 1005 return GEM_RING_SZ_512; 1006 case 1024: 1007 return GEM_RING_SZ_1024; 1008 case 2048: 1009 return GEM_RING_SZ_2048; 1010 case 4096: 1011 return GEM_RING_SZ_4096; 1012 case 8192: 1013 return GEM_RING_SZ_8192; 1014 default: 1015 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 1016 return GEM_RING_SZ_32; 1017 } 1018 } 1019 1020 1021 /* 1022 * Start PCS 1023 */ 1024 void 1025 gem_pcs_start(struct gem_softc *sc) 1026 { 1027 bus_space_tag_t t = sc->sc_bustag; 1028 bus_space_handle_t h = sc->sc_h1; 1029 uint32_t v; 1030 1031 #ifdef GEM_DEBUG 1032 aprint_debug_dev(sc->sc_dev, "gem_pcs_start()\n"); 1033 #endif 1034 1035 /* 1036 * Set up. We must disable the MII before modifying the 1037 * GEM_MII_ANAR register 1038 */ 1039 if (sc->sc_flags & GEM_SERDES) { 1040 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1041 GEM_MII_DATAPATH_SERDES); 1042 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1043 GEM_MII_SLINK_LOOPBACK); 1044 } else { 1045 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1046 GEM_MII_DATAPATH_SERIAL); 1047 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0); 1048 } 1049 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1050 v = bus_space_read_4(t, h, GEM_MII_ANAR); 1051 v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE); 1052 if (IFM_SUBTYPE(sc->sc_mii_media) == IFM_AUTO) 1053 v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX); 1054 else if ((IFM_OPTIONS(sc->sc_mii_media) & IFM_FDX) != 0) { 1055 v |= GEM_MII_ANEG_FUL_DUPLX; 1056 v &= ~GEM_MII_ANEG_HLF_DUPLX; 1057 } else if ((IFM_OPTIONS(sc->sc_mii_media) & IFM_HDX) != 0) { 1058 v &= ~GEM_MII_ANEG_FUL_DUPLX; 1059 v |= GEM_MII_ANEG_HLF_DUPLX; 1060 } 1061 1062 /* Configure link. */ 1063 bus_space_write_4(t, h, GEM_MII_ANAR, v); 1064 bus_space_write_4(t, h, GEM_MII_CONTROL, 1065 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1066 bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 1067 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT); 1068 1069 /* Start the 10 second timer */ 1070 callout_schedule(&sc->sc_tick_ch, hz * 10); 1071 } 1072 1073 /* 1074 * Stop PCS 1075 */ 1076 void 1077 gem_pcs_stop(struct gem_softc *sc, int disable) 1078 { 1079 bus_space_tag_t t = sc->sc_bustag; 1080 bus_space_handle_t h = sc->sc_h1; 1081 1082 #ifdef GEM_DEBUG 1083 aprint_debug_dev(sc->sc_dev, "gem_pcs_stop()\n"); 1084 #endif 1085 1086 /* Tell link partner that we're going away */ 1087 bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF); 1088 1089 /* 1090 * Disable PCS MII. The documentation suggests that setting 1091 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto- 1092 * negotiation will shut down the link. However, it appears 1093 * that we also need to unset the datapath mode. 1094 */ 1095 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1096 bus_space_write_4(t, h, GEM_MII_CONTROL, 1097 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1098 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII); 1099 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1100 1101 if (disable) { 1102 if (sc->sc_flags & GEM_SERDES) 1103 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1104 GEM_MII_SLINK_POWER_OFF); 1105 else 1106 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1107 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF); 1108 } 1109 1110 sc->sc_flags &= ~GEM_LINK; 1111 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 1112 sc->sc_mii.mii_media_status = IFM_AVALID; 1113 } 1114 1115 1116 /* 1117 * Initialization of interface; set up initialization block 1118 * and transmit/receive descriptor rings. 1119 */ 1120 int 1121 gem_init(struct ifnet *ifp) 1122 { 1123 struct gem_softc *sc = ifp->if_softc; 1124 bus_space_tag_t t = sc->sc_bustag; 1125 bus_space_handle_t h = sc->sc_h1; 1126 int rc = 0, s; 1127 u_int max_frame_size; 1128 uint32_t v; 1129 1130 s = splnet(); 1131 1132 DPRINTF(sc, ("%s: gem_init: calling stop\n", device_xname(sc->sc_dev))); 1133 /* 1134 * Initialization sequence. The numbered steps below correspond 1135 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1136 * Channel Engine manual (part of the PCIO manual). 1137 * See also the STP2002-STQ document from Sun Microsystems. 1138 */ 1139 1140 /* step 1 & 2. Reset the Ethernet Channel */ 1141 gem_stop(ifp, 0); 1142 gem_reset(sc); 1143 DPRINTF(sc, ("%s: gem_init: restarting\n", device_xname(sc->sc_dev))); 1144 1145 /* Re-initialize the MIF */ 1146 gem_mifinit(sc); 1147 1148 /* Set up correct datapath for non-SERDES/Serialink */ 1149 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1150 sc->sc_variant != GEM_SUN_ERI) 1151 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1152 GEM_MII_DATAPATH_MII); 1153 1154 /* Call MI reset function if any */ 1155 if (sc->sc_hwreset) 1156 (*sc->sc_hwreset)(sc); 1157 1158 /* step 3. Setup data structures in host memory */ 1159 if (gem_meminit(sc) != 0) { 1160 splx(s); 1161 return 1; 1162 } 1163 1164 /* step 4. TX MAC registers & counters */ 1165 gem_init_regs(sc); 1166 max_frame_size = uimax(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 1167 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 1168 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1169 max_frame_size += ETHER_VLAN_ENCAP_LEN; 1170 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1171 max_frame_size|/* burst size */(0x2000<<16)); 1172 1173 /* step 5. RX MAC registers & counters */ 1174 gem_setladrf(sc); 1175 1176 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1177 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 1178 ((uint64_t)GEM_CDTXADDR(sc, 0)) >> 32); 1179 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 1180 1181 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 1182 ((uint64_t)GEM_CDRXADDR(sc, 0)) >> 32); 1183 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 1184 1185 /* step 8. Global Configuration & Interrupt Mask */ 1186 gem_inten(sc); 1187 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 1188 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1189 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */ 1190 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 1191 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1192 1193 /* step 9. ETX Configuration: use mostly default values */ 1194 1195 /* Enable TX DMA */ 1196 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 1197 bus_space_write_4(t, h, GEM_TX_CONFIG, 1198 v | GEM_TX_CONFIG_TXDMA_EN | 1199 (((sc->sc_flags & GEM_GIGABIT ? 0x4FF : 0x100) << 10) & 1200 GEM_TX_CONFIG_TXFIFO_TH)); 1201 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 1202 1203 /* step 10. ERX Configuration */ 1204 gem_rx_common(sc); 1205 1206 /* step 11. Configure Media */ 1207 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1208 (rc = mii_ifmedia_change(&sc->sc_mii)) != 0) 1209 goto out; 1210 1211 /* step 12. RX_MAC Configuration Register */ 1212 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1213 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1214 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1215 1216 /* step 14. Issue Transmit Pending command */ 1217 1218 /* Call MI initialization function if any */ 1219 if (sc->sc_hwinit) 1220 (*sc->sc_hwinit)(sc); 1221 1222 /* step 15. Give the receiver a swift kick */ 1223 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 1224 1225 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1226 /* Configure PCS */ 1227 gem_pcs_start(sc); 1228 else 1229 /* Start the one second timer. */ 1230 callout_schedule(&sc->sc_tick_ch, hz); 1231 1232 sc->sc_flags &= ~GEM_LINK; 1233 ifp->if_flags |= IFF_RUNNING; 1234 ifp->if_timer = 0; 1235 sc->sc_if_flags = ifp->if_flags; 1236 out: 1237 splx(s); 1238 1239 return (0); 1240 } 1241 1242 void 1243 gem_init_regs(struct gem_softc *sc) 1244 { 1245 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1246 bus_space_tag_t t = sc->sc_bustag; 1247 bus_space_handle_t h = sc->sc_h1; 1248 const u_char *laddr = CLLADDR(ifp->if_sadl); 1249 uint32_t v; 1250 1251 /* These regs are not cleared on reset */ 1252 if (!sc->sc_inited) { 1253 1254 /* Load recommended values */ 1255 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 1256 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 1257 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 1258 1259 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1260 /* Max frame and max burst size */ 1261 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1262 ETHER_MAX_LEN | (0x2000<<16)); 1263 1264 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 1265 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 1266 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1267 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1268 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1269 ((laddr[5]<<8)|laddr[4])&0x3ff); 1270 1271 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1272 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1273 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1274 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1275 1276 /* MAC control addr set to 01:80:c2:00:00:01 */ 1277 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1278 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1279 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1280 1281 /* MAC filter addr set to 0:0:0:0:0:0 */ 1282 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1283 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1284 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1285 1286 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1287 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1288 1289 sc->sc_inited = 1; 1290 } 1291 1292 /* Counters need to be zeroed */ 1293 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1294 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1295 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1296 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1297 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1298 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1299 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1300 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1301 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1302 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1303 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1304 1305 /* Set XOFF PAUSE time. */ 1306 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1307 1308 /* 1309 * Set the internal arbitration to "infinite" bursts of the 1310 * maximum length of 31 * 64 bytes so DMA transfers aren't 1311 * split up in cache line size chunks. This greatly improves 1312 * especially RX performance. 1313 * Enable silicon bug workarounds for the Apple variants. 1314 */ 1315 bus_space_write_4(t, h, GEM_CONFIG, 1316 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1317 ((sc->sc_flags & GEM_PCI) ? 1318 GEM_CONFIG_BURST_INF : GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 1319 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1320 1321 /* 1322 * Set the station address. 1323 */ 1324 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1325 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1326 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1327 1328 /* 1329 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1330 */ 1331 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1332 v = GEM_MAC_XIF_TX_MII_ENA; 1333 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 1334 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1335 v |= GEM_MAC_XIF_FDPLX_LED; 1336 if (sc->sc_flags & GEM_GIGABIT) 1337 v |= GEM_MAC_XIF_GMII_MODE; 1338 } 1339 } else { 1340 v |= GEM_MAC_XIF_GMII_MODE; 1341 } 1342 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1343 } 1344 1345 #ifdef GEM_DEBUG 1346 static void 1347 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc) 1348 { 1349 int i; 1350 1351 for (i = firstdesc;; i = GEM_NEXTTX(i)) { 1352 printf("descriptor %d:\t", i); 1353 printf("gd_flags: 0x%016" PRIx64 "\t", 1354 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1355 printf("gd_addr: 0x%016" PRIx64 "\n", 1356 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1357 if (i == lastdesc) 1358 break; 1359 } 1360 } 1361 #endif 1362 1363 static void 1364 gem_start(struct ifnet *ifp) 1365 { 1366 struct gem_softc *sc = ifp->if_softc; 1367 struct mbuf *m0, *m; 1368 struct gem_txsoft *txs; 1369 bus_dmamap_t dmamap; 1370 int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg; 1371 #ifdef GEM_DEBUG 1372 int otxnext; 1373 #endif 1374 uint64_t flags = 0; 1375 1376 if ((ifp->if_flags & IFF_RUNNING) != IFF_RUNNING) 1377 return; 1378 1379 /* 1380 * Remember the previous number of free descriptors and 1381 * the first descriptor we'll use. 1382 */ 1383 ofree = sc->sc_txfree; 1384 #ifdef GEM_DEBUG 1385 otxnext = sc->sc_txnext; 1386 #endif 1387 1388 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1389 device_xname(sc->sc_dev), ofree, otxnext)); 1390 1391 /* 1392 * Loop through the send queue, setting up transmit descriptors 1393 * until we drain the queue, or use up all available transmit 1394 * descriptors. 1395 */ 1396 #ifdef INET 1397 next: 1398 #endif 1399 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1400 sc->sc_txfree != 0) { 1401 /* 1402 * Grab a packet off the queue. 1403 */ 1404 IFQ_POLL(&ifp->if_snd, m0); 1405 if (m0 == NULL) 1406 break; 1407 m = NULL; 1408 1409 dmamap = txs->txs_dmamap; 1410 1411 /* 1412 * Load the DMA map. If this fails, the packet either 1413 * didn't fit in the allotted number of segments, or we were 1414 * short on resources. In this case, we'll copy and try 1415 * again. 1416 */ 1417 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1418 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0 || 1419 (m0->m_pkthdr.len < ETHER_MIN_TX && 1420 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1421 if (m0->m_pkthdr.len > MCLBYTES) { 1422 aprint_error_dev(sc->sc_dev, 1423 "unable to allocate jumbo Tx cluster\n"); 1424 IFQ_DEQUEUE(&ifp->if_snd, m0); 1425 m_freem(m0); 1426 continue; 1427 } 1428 MGETHDR(m, M_DONTWAIT, MT_DATA); 1429 if (m == NULL) { 1430 aprint_error_dev(sc->sc_dev, 1431 "unable to allocate Tx mbuf\n"); 1432 break; 1433 } 1434 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1435 if (m0->m_pkthdr.len > MHLEN) { 1436 MCLGET(m, M_DONTWAIT); 1437 if ((m->m_flags & M_EXT) == 0) { 1438 aprint_error_dev(sc->sc_dev, 1439 "unable to allocate Tx cluster\n"); 1440 m_freem(m); 1441 break; 1442 } 1443 } 1444 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1445 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1446 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1447 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1448 if (error) { 1449 aprint_error_dev(sc->sc_dev, 1450 "unable to load Tx buffer, error = %d\n", 1451 error); 1452 break; 1453 } 1454 } 1455 1456 /* 1457 * Ensure we have enough descriptors free to describe 1458 * the packet. 1459 */ 1460 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1461 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1462 /* 1463 * Not enough free descriptors to transmit this 1464 * packet. 1465 */ 1466 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1467 m_freem(m); 1468 break; 1469 } 1470 1471 IFQ_DEQUEUE(&ifp->if_snd, m0); 1472 if (m != NULL) { 1473 m_freem(m0); 1474 m0 = m; 1475 } 1476 1477 /* 1478 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1479 */ 1480 1481 /* Sync the DMA map. */ 1482 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1483 BUS_DMASYNC_PREWRITE); 1484 1485 /* 1486 * Initialize the transmit descriptors. 1487 */ 1488 firsttx = sc->sc_txnext; 1489 for (nexttx = firsttx, seg = 0; 1490 seg < dmamap->dm_nsegs; 1491 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1492 1493 /* 1494 * If this is the first descriptor we're 1495 * enqueueing, set the start of packet flag, 1496 * and the checksum stuff if we want the hardware 1497 * to do it. 1498 */ 1499 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1500 if (nexttx == firsttx) { 1501 flags |= GEM_TD_START_OF_PACKET; 1502 #ifdef INET 1503 /* h/w checksum */ 1504 if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 && 1505 m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1506 struct ether_header *eh; 1507 uint16_t offset, start; 1508 1509 eh = mtod(m0, struct ether_header *); 1510 switch (ntohs(eh->ether_type)) { 1511 case ETHERTYPE_IP: 1512 start = ETHER_HDR_LEN; 1513 break; 1514 case ETHERTYPE_VLAN: 1515 start = ETHER_HDR_LEN + 1516 ETHER_VLAN_ENCAP_LEN; 1517 break; 1518 default: 1519 /* unsupported, drop it */ 1520 bus_dmamap_unload(sc->sc_dmatag, 1521 dmamap); 1522 m_freem(m0); 1523 goto next; 1524 } 1525 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1526 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1527 flags |= (start << 1528 GEM_TD_CXSUM_STARTSHFT) | 1529 (offset << 1530 GEM_TD_CXSUM_STUFFSHFT) | 1531 GEM_TD_CXSUM_ENABLE; 1532 } 1533 #endif 1534 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1535 sc->sc_txwin = 0; 1536 flags |= GEM_TD_INTERRUPT_ME; 1537 } 1538 } 1539 sc->sc_txdescs[nexttx].gd_addr = 1540 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1541 if (seg == dmamap->dm_nsegs - 1) { 1542 flags |= GEM_TD_END_OF_PACKET; 1543 } else { 1544 /* last flag set outside of loop */ 1545 sc->sc_txdescs[nexttx].gd_flags = 1546 GEM_DMA_WRITE(sc, flags); 1547 } 1548 lasttx = nexttx; 1549 } 1550 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1551 /* add padding buffer at end of chain */ 1552 flags &= ~GEM_TD_END_OF_PACKET; 1553 sc->sc_txdescs[lasttx].gd_flags = 1554 GEM_DMA_WRITE(sc, flags); 1555 1556 sc->sc_txdescs[nexttx].gd_addr = 1557 GEM_DMA_WRITE(sc, 1558 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1559 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1560 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1561 lasttx = nexttx; 1562 nexttx = GEM_NEXTTX(nexttx); 1563 seg++; 1564 } 1565 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1566 1567 KASSERT(lasttx != -1); 1568 1569 /* 1570 * Store a pointer to the packet so we can free it later, 1571 * and remember what txdirty will be once the packet is 1572 * done. 1573 */ 1574 txs->txs_mbuf = m0; 1575 txs->txs_firstdesc = sc->sc_txnext; 1576 txs->txs_lastdesc = lasttx; 1577 txs->txs_ndescs = seg; 1578 1579 #ifdef GEM_DEBUG 1580 if (ifp->if_flags & IFF_DEBUG) { 1581 printf(" gem_start %p transmit chain:\n", txs); 1582 gem_txsoft_print(sc, txs->txs_firstdesc, 1583 txs->txs_lastdesc); 1584 } 1585 #endif 1586 1587 /* Sync the descriptors we're using. */ 1588 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1589 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1590 1591 /* Advance the tx pointer. */ 1592 sc->sc_txfree -= txs->txs_ndescs; 1593 sc->sc_txnext = nexttx; 1594 1595 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1596 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1597 1598 /* 1599 * Pass the packet to any BPF listeners. 1600 */ 1601 bpf_mtap(ifp, m0, BPF_D_OUT); 1602 } 1603 1604 if (sc->sc_txfree != ofree) { 1605 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1606 device_xname(sc->sc_dev), lasttx, otxnext)); 1607 /* 1608 * The entire packet chain is set up. 1609 * Kick the transmitter. 1610 */ 1611 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1612 device_xname(sc->sc_dev), nexttx)); 1613 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, 1614 sc->sc_txnext); 1615 1616 /* Set a watchdog timer in case the chip flakes out. */ 1617 ifp->if_timer = 5; 1618 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1619 device_xname(sc->sc_dev), ifp->if_timer)); 1620 } 1621 } 1622 1623 /* 1624 * Transmit interrupt. 1625 */ 1626 int 1627 gem_tint(struct gem_softc *sc) 1628 { 1629 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1630 bus_space_tag_t t = sc->sc_bustag; 1631 bus_space_handle_t mac = sc->sc_h1; 1632 struct gem_txsoft *txs; 1633 int txlast; 1634 int progress = 0; 1635 uint32_t v; 1636 1637 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1638 1639 DPRINTF(sc, ("%s: gem_tint\n", device_xname(sc->sc_dev))); 1640 1641 /* Unload collision counters ... */ 1642 v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1643 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1644 if_statadd_ref(ifp, nsr, if_collisions, v + 1645 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1646 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT)); 1647 if_statadd_ref(ifp, nsr, if_oerrors, v); 1648 1649 /* ... then clear the hardware counters. */ 1650 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1651 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1652 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1653 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1654 1655 /* 1656 * Go through our Tx list and free mbufs for those 1657 * frames that have been transmitted. 1658 */ 1659 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1660 /* 1661 * In theory, we could harvest some descriptors before 1662 * the ring is empty, but that's a bit complicated. 1663 * 1664 * GEM_TX_COMPLETION points to the last descriptor 1665 * processed +1. 1666 * 1667 * Let's assume that the NIC writes back to the Tx 1668 * descriptors before it updates the completion 1669 * register. If the NIC has posted writes to the 1670 * Tx descriptors, PCI ordering requires that the 1671 * posted writes flush to RAM before the register-read 1672 * finishes. So let's read the completion register, 1673 * before syncing the descriptors, so that we 1674 * examine Tx descriptors that are at least as 1675 * current as the completion register. 1676 */ 1677 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1678 DPRINTF(sc, 1679 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1680 txs->txs_lastdesc, txlast)); 1681 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1682 if (txlast >= txs->txs_firstdesc && 1683 txlast <= txs->txs_lastdesc) 1684 break; 1685 } else if (txlast >= txs->txs_firstdesc || 1686 txlast <= txs->txs_lastdesc) 1687 break; 1688 1689 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1690 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1691 1692 #ifdef GEM_DEBUG /* XXX DMA synchronization? */ 1693 if (ifp->if_flags & IFF_DEBUG) { 1694 printf(" txsoft %p transmit chain:\n", txs); 1695 gem_txsoft_print(sc, txs->txs_firstdesc, 1696 txs->txs_lastdesc); 1697 } 1698 #endif 1699 1700 1701 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1702 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1703 1704 sc->sc_txfree += txs->txs_ndescs; 1705 1706 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1707 0, txs->txs_dmamap->dm_mapsize, 1708 BUS_DMASYNC_POSTWRITE); 1709 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1710 m_freem(txs->txs_mbuf); 1711 txs->txs_mbuf = NULL; 1712 1713 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1714 1715 if_statinc_ref(ifp, nsr, if_opackets); 1716 progress = 1; 1717 } 1718 1719 IF_STAT_PUTREF(ifp); 1720 1721 #if 0 1722 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1723 "GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n", 1724 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE), 1725 ((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1726 GEM_TX_DATA_PTR_HI) << 32) | 1727 bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1728 GEM_TX_DATA_PTR_LO), 1729 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION))); 1730 #endif 1731 1732 if (progress) { 1733 if (sc->sc_txfree == GEM_NTXDESC - 1) 1734 sc->sc_txwin = 0; 1735 1736 ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 1737 if_schedule_deferred_start(ifp); 1738 } 1739 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1740 device_xname(sc->sc_dev), ifp->if_timer)); 1741 1742 return (1); 1743 } 1744 1745 /* 1746 * Receive interrupt. 1747 */ 1748 int 1749 gem_rint(struct gem_softc *sc) 1750 { 1751 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1752 bus_space_tag_t t = sc->sc_bustag; 1753 bus_space_handle_t h = sc->sc_h1; 1754 struct gem_rxsoft *rxs; 1755 struct mbuf *m; 1756 uint64_t rxstat; 1757 uint32_t rxcomp; 1758 int i, len, progress = 0; 1759 1760 DPRINTF(sc, ("%s: gem_rint\n", device_xname(sc->sc_dev))); 1761 1762 /* 1763 * Ignore spurious interrupt that sometimes occurs before 1764 * we are set up when we network boot. 1765 */ 1766 if (!sc->sc_meminited) 1767 return 1; 1768 1769 /* 1770 * Read the completion register once. This limits 1771 * how long the following loop can execute. 1772 */ 1773 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1774 1775 /* 1776 * XXX Read the lastrx only once at the top for speed. 1777 */ 1778 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1779 sc->sc_rxptr, rxcomp)); 1780 1781 /* 1782 * Go into the loop at least once. 1783 */ 1784 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1785 i = GEM_NEXTRX(i)) { 1786 rxs = &sc->sc_rxsoft[i]; 1787 1788 GEM_CDRXSYNC(sc, i, 1789 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1790 1791 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1792 1793 if (rxstat & GEM_RD_OWN) { 1794 GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1795 /* 1796 * We have processed all of the receive buffers. 1797 */ 1798 break; 1799 } 1800 1801 progress++; 1802 1803 if (rxstat & GEM_RD_BAD_CRC) { 1804 if_statinc(ifp, if_ierrors); 1805 DPRINTF(sc, ("%s: receive error: CRC error\n", 1806 device_xname(sc->sc_dev))); 1807 GEM_INIT_RXDESC(sc, i); 1808 continue; 1809 } 1810 1811 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1812 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1813 #ifdef GEM_DEBUG 1814 if (ifp->if_flags & IFF_DEBUG) { 1815 printf(" rxsoft %p descriptor %d: ", rxs, i); 1816 printf("gd_flags: 0x%016llx\t", (long long) 1817 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1818 printf("gd_addr: 0x%016llx\n", (long long) 1819 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1820 } 1821 #endif 1822 1823 /* No errors; receive the packet. */ 1824 len = GEM_RD_BUFLEN(rxstat); 1825 1826 /* 1827 * Allocate a new mbuf cluster. If that fails, we are 1828 * out of memory, and must drop the packet and recycle 1829 * the buffer that's already attached to this descriptor. 1830 */ 1831 m = rxs->rxs_mbuf; 1832 if (gem_add_rxbuf(sc, i) != 0) { 1833 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1834 if_statinc(ifp, if_ierrors); 1835 aprint_error_dev(sc->sc_dev, 1836 "receive error: RX no buffer space\n"); 1837 GEM_INIT_RXDESC(sc, i); 1838 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1839 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1840 continue; 1841 } 1842 m->m_data += 2; /* We're already off by two */ 1843 1844 m_set_rcvif(m, ifp); 1845 m->m_pkthdr.len = m->m_len = len; 1846 1847 #ifdef INET 1848 /* hardware checksum */ 1849 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1850 struct ether_header *eh; 1851 struct ip *ip; 1852 int32_t hlen, pktlen; 1853 1854 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1855 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1856 ETHER_VLAN_ENCAP_LEN; 1857 eh = (struct ether_header *) (mtod(m, char *) + 1858 ETHER_VLAN_ENCAP_LEN); 1859 } else { 1860 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1861 eh = mtod(m, struct ether_header *); 1862 } 1863 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1864 goto swcsum; 1865 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 1866 1867 /* IPv4 only */ 1868 if (ip->ip_v != IPVERSION) 1869 goto swcsum; 1870 1871 hlen = ip->ip_hl << 2; 1872 if (hlen < sizeof(struct ip)) 1873 goto swcsum; 1874 1875 /* 1876 * bail if too short, has random trailing garbage, 1877 * truncated, fragment, or has ethernet pad. 1878 */ 1879 if ((ntohs(ip->ip_len) < hlen) || 1880 (ntohs(ip->ip_len) != pktlen) || 1881 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1882 goto swcsum; 1883 1884 switch (ip->ip_p) { 1885 case IPPROTO_TCP: 1886 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1887 goto swcsum; 1888 if (pktlen < (hlen + sizeof(struct tcphdr))) 1889 goto swcsum; 1890 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1891 break; 1892 case IPPROTO_UDP: 1893 /* FALLTHROUGH */ 1894 default: 1895 goto swcsum; 1896 } 1897 1898 /* the uncomplemented sum is expected */ 1899 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1900 1901 /* if the pkt had ip options, we have to deduct them */ 1902 if (hlen > sizeof(struct ip)) { 1903 uint16_t *opts; 1904 uint32_t optsum, temp; 1905 1906 optsum = 0; 1907 temp = hlen - sizeof(struct ip); 1908 opts = (uint16_t *) ((char *) ip + 1909 sizeof(struct ip)); 1910 1911 while (temp > 1) { 1912 optsum += ntohs(*opts++); 1913 temp -= 2; 1914 } 1915 while (optsum >> 16) 1916 optsum = (optsum >> 16) + 1917 (optsum & 0xffff); 1918 1919 /* Deduct ip opts sum from hwsum. */ 1920 m->m_pkthdr.csum_data += (uint16_t)~optsum; 1921 1922 while (m->m_pkthdr.csum_data >> 16) 1923 m->m_pkthdr.csum_data = 1924 (m->m_pkthdr.csum_data >> 16) + 1925 (m->m_pkthdr.csum_data & 1926 0xffff); 1927 } 1928 1929 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1930 M_CSUM_NO_PSEUDOHDR; 1931 } else 1932 swcsum: 1933 m->m_pkthdr.csum_flags = 0; 1934 #endif 1935 /* Pass it on. */ 1936 if_percpuq_enqueue(ifp->if_percpuq, m); 1937 } 1938 1939 if (progress) { 1940 /* Update the receive pointer. */ 1941 if (i == sc->sc_rxptr) { 1942 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1943 #ifdef GEM_DEBUG 1944 if (ifp->if_flags & IFF_DEBUG) 1945 printf("%s: rint: ring wrap\n", 1946 device_xname(sc->sc_dev)); 1947 #endif 1948 } 1949 sc->sc_rxptr = i; 1950 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1951 } 1952 #ifdef GEM_COUNTERS 1953 if (progress <= 4) { 1954 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1955 } else if (progress < 32) { 1956 if (progress < 16) 1957 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1958 else 1959 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1960 1961 } else { 1962 if (progress < 64) 1963 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1964 else 1965 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1966 } 1967 #endif 1968 1969 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1970 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1971 1972 /* Read error counters ... */ 1973 if_statadd(ifp, if_ierrors, 1974 bus_space_read_4(t, h, GEM_MAC_RX_LEN_ERR_CNT) + 1975 bus_space_read_4(t, h, GEM_MAC_RX_ALIGN_ERR) + 1976 bus_space_read_4(t, h, GEM_MAC_RX_CRC_ERR_CNT) + 1977 bus_space_read_4(t, h, GEM_MAC_RX_CODE_VIOL)); 1978 1979 /* ... then clear the hardware counters. */ 1980 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1981 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1982 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1983 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1984 1985 return (1); 1986 } 1987 1988 1989 /* 1990 * gem_add_rxbuf: 1991 * 1992 * Add a receive buffer to the indicated descriptor. 1993 */ 1994 int 1995 gem_add_rxbuf(struct gem_softc *sc, int idx) 1996 { 1997 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1998 struct mbuf *m; 1999 int error; 2000 2001 MGETHDR(m, M_DONTWAIT, MT_DATA); 2002 if (m == NULL) 2003 return (ENOBUFS); 2004 2005 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2006 MCLGET(m, M_DONTWAIT); 2007 if ((m->m_flags & M_EXT) == 0) { 2008 m_freem(m); 2009 return (ENOBUFS); 2010 } 2011 2012 #ifdef GEM_DEBUG 2013 /* bzero the packet to check DMA */ 2014 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 2015 #endif 2016 2017 if (rxs->rxs_mbuf != NULL) 2018 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 2019 2020 rxs->rxs_mbuf = m; 2021 2022 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 2023 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2024 BUS_DMA_READ | BUS_DMA_NOWAIT); 2025 if (error) { 2026 aprint_error_dev(sc->sc_dev, 2027 "can't load rx DMA map %d, error = %d\n", idx, error); 2028 panic("gem_add_rxbuf"); /* XXX */ 2029 } 2030 2031 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 2032 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2033 2034 GEM_INIT_RXDESC(sc, idx); 2035 2036 return (0); 2037 } 2038 2039 2040 int 2041 gem_eint(struct gem_softc *sc, u_int status) 2042 { 2043 char bits[128]; 2044 uint32_t r, v; 2045 2046 if ((status & GEM_INTR_MIF) != 0) { 2047 printf("%s: XXXlink status changed\n", device_xname(sc->sc_dev)); 2048 return (1); 2049 } 2050 2051 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 2052 gem_reset_rxdma(sc); 2053 return (1); 2054 } 2055 2056 if (status & GEM_INTR_BERR) { 2057 if (sc->sc_flags & GEM_PCI) 2058 r = GEM_ERROR_STATUS; 2059 else 2060 r = GEM_SBUS_ERROR_STATUS; 2061 bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2062 v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2063 aprint_error_dev(sc->sc_dev, "bus error interrupt: 0x%02x\n", 2064 v); 2065 return (1); 2066 } 2067 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2068 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 2069 2070 return (1); 2071 } 2072 2073 2074 /* 2075 * PCS interrupts. 2076 * We should receive these when the link status changes, but sometimes 2077 * we don't receive them for link up. We compensate for this in the 2078 * gem_tick() callout. 2079 */ 2080 int 2081 gem_pint(struct gem_softc *sc) 2082 { 2083 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2084 bus_space_tag_t t = sc->sc_bustag; 2085 bus_space_handle_t h = sc->sc_h1; 2086 uint32_t v, v2; 2087 2088 /* 2089 * Clear the PCS interrupt from GEM_STATUS. The PCS register is 2090 * latched, so we have to read it twice. There is only one bit in 2091 * use, so the value is meaningless. 2092 */ 2093 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2094 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2095 2096 if ((ifp->if_flags & IFF_UP) == 0) 2097 return 1; 2098 2099 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) 2100 return 1; 2101 2102 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2103 /* If we see remote fault, our link partner is probably going away */ 2104 if ((v & GEM_MII_STATUS_REM_FLT) != 0) { 2105 gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0); 2106 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2107 /* Otherwise, we may need to wait after auto-negotiation completes */ 2108 } else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) == 2109 GEM_MII_STATUS_ANEG_CPT) { 2110 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS); 2111 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2112 } 2113 if ((v & GEM_MII_STATUS_LINK_STS) != 0) { 2114 if (sc->sc_flags & GEM_LINK) { 2115 return 1; 2116 } 2117 callout_stop(&sc->sc_tick_ch); 2118 v = bus_space_read_4(t, h, GEM_MII_ANAR); 2119 v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR); 2120 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX; 2121 sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 2122 v &= v2; 2123 if (v & GEM_MII_ANEG_FUL_DUPLX) { 2124 sc->sc_mii.mii_media_active |= IFM_FDX; 2125 #ifdef GEM_DEBUG 2126 aprint_debug_dev(sc->sc_dev, "link up: full duplex\n"); 2127 #endif 2128 } else if (v & GEM_MII_ANEG_HLF_DUPLX) { 2129 sc->sc_mii.mii_media_active |= IFM_HDX; 2130 #ifdef GEM_DEBUG 2131 aprint_debug_dev(sc->sc_dev, "link up: half duplex\n"); 2132 #endif 2133 } else { 2134 #ifdef GEM_DEBUG 2135 aprint_debug_dev(sc->sc_dev, "duplex mismatch\n"); 2136 #endif 2137 } 2138 gem_statuschange(sc); 2139 } else { 2140 if ((sc->sc_flags & GEM_LINK) == 0) { 2141 return 1; 2142 } 2143 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 2144 sc->sc_mii.mii_media_status = IFM_AVALID; 2145 #ifdef GEM_DEBUG 2146 aprint_debug_dev(sc->sc_dev, "link down\n"); 2147 #endif 2148 gem_statuschange(sc); 2149 2150 /* Start the 10 second timer */ 2151 callout_schedule(&sc->sc_tick_ch, hz * 10); 2152 } 2153 return 1; 2154 } 2155 2156 2157 2158 int 2159 gem_intr(void *v) 2160 { 2161 struct gem_softc *sc = v; 2162 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2163 bus_space_tag_t t = sc->sc_bustag; 2164 bus_space_handle_t h = sc->sc_h1; 2165 uint32_t status; 2166 int r = 0; 2167 #ifdef GEM_DEBUG 2168 char bits[128]; 2169 #endif 2170 2171 /* XXX We should probably mask out interrupts until we're done */ 2172 2173 sc->sc_ev_intr.ev_count++; 2174 2175 status = bus_space_read_4(t, h, GEM_STATUS); 2176 #ifdef GEM_DEBUG 2177 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2178 #endif 2179 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 2180 device_xname(sc->sc_dev), (status >> 19), bits)); 2181 2182 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 2183 r |= gem_eint(sc, status); 2184 2185 /* We don't bother with GEM_INTR_TX_DONE */ 2186 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 2187 GEM_COUNTER_INCR(sc, sc_ev_txint); 2188 r |= gem_tint(sc); 2189 } 2190 2191 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 2192 GEM_COUNTER_INCR(sc, sc_ev_rxint); 2193 r |= gem_rint(sc); 2194 } 2195 2196 /* We should eventually do more than just print out error stats. */ 2197 if (status & GEM_INTR_TX_MAC) { 2198 int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS); 2199 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 2200 printf("%s: MAC tx fault, status %x\n", 2201 device_xname(sc->sc_dev), txstat); 2202 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 2203 gem_init(ifp); 2204 } 2205 if (status & GEM_INTR_RX_MAC) { 2206 int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS); 2207 /* 2208 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 2209 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 2210 * silicon bug so handle them silently. So if we detect 2211 * an RX FIFO overflow, we fire off a timer, and check 2212 * whether we're still making progress by looking at the 2213 * RX FIFO write and read pointers. 2214 */ 2215 if (rxstat & GEM_MAC_RX_OVERFLOW) { 2216 if_statinc(ifp, if_ierrors); 2217 GEM_COUNTER_INCR(sc, sc_ev_rxoverflow); 2218 #ifdef GEM_DEBUG 2219 aprint_error_dev(sc->sc_dev, 2220 "receive error: RX overflow sc->rxptr %d, complete %d\n", sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)); 2221 #endif 2222 sc->sc_rx_fifo_wr_ptr = 2223 bus_space_read_4(t, h, GEM_RX_FIFO_WR_PTR); 2224 sc->sc_rx_fifo_rd_ptr = 2225 bus_space_read_4(t, h, GEM_RX_FIFO_RD_PTR); 2226 callout_schedule(&sc->sc_rx_watchdog, 400); 2227 } else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 2228 printf("%s: MAC rx fault, status 0x%02x\n", 2229 device_xname(sc->sc_dev), rxstat); 2230 } 2231 if (status & GEM_INTR_PCS) { 2232 r |= gem_pint(sc); 2233 } 2234 2235 /* Do we need to do anything with these? 2236 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 2237 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS); 2238 if ((status2 & GEM_MAC_PAUSED) != 0) 2239 aprintf_debug_dev(sc->sc_dev, "PAUSE received (%d slots)\n", 2240 GEM_MAC_PAUSE_TIME(status2)); 2241 if ((status2 & GEM_MAC_PAUSE) != 0) 2242 aprintf_debug_dev(sc->sc_dev, "transited to PAUSE state\n"); 2243 if ((status2 & GEM_MAC_RESUME) != 0) 2244 aprintf_debug_dev(sc->sc_dev, "transited to non-PAUSE state\n"); 2245 } 2246 if ((status & GEM_INTR_MIF) != 0) 2247 aprintf_debug_dev(sc->sc_dev, "MIF interrupt\n"); 2248 */ 2249 rnd_add_uint32(&sc->rnd_source, status); 2250 return (r); 2251 } 2252 2253 void 2254 gem_rx_watchdog(void *arg) 2255 { 2256 struct gem_softc *sc = arg; 2257 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2258 bus_space_tag_t t = sc->sc_bustag; 2259 bus_space_handle_t h = sc->sc_h1; 2260 uint32_t rx_fifo_wr_ptr; 2261 uint32_t rx_fifo_rd_ptr; 2262 uint32_t state; 2263 2264 if ((ifp->if_flags & IFF_RUNNING) == 0) { 2265 aprint_error_dev(sc->sc_dev, "receiver not running\n"); 2266 return; 2267 } 2268 2269 rx_fifo_wr_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_WR_PTR); 2270 rx_fifo_rd_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_RD_PTR); 2271 state = bus_space_read_4(t, h, GEM_MAC_MAC_STATE); 2272 if ((state & GEM_MAC_STATE_OVERFLOW) == GEM_MAC_STATE_OVERFLOW && 2273 ((rx_fifo_wr_ptr == rx_fifo_rd_ptr) || 2274 ((sc->sc_rx_fifo_wr_ptr == rx_fifo_wr_ptr) && 2275 (sc->sc_rx_fifo_rd_ptr == rx_fifo_rd_ptr)))) 2276 { 2277 /* 2278 * The RX state machine is still in overflow state and 2279 * the RX FIFO write and read pointers seem to be 2280 * stuck. Whack the chip over the head to get things 2281 * going again. 2282 */ 2283 aprint_error_dev(sc->sc_dev, 2284 "receiver stuck in overflow, resetting\n"); 2285 gem_init(ifp); 2286 } else { 2287 int needreset = 1; 2288 if ((state & GEM_MAC_STATE_OVERFLOW) != GEM_MAC_STATE_OVERFLOW) { 2289 DPRINTF(sc, 2290 ("%s: rx_watchdog: not in overflow state: 0x%x\n", 2291 device_xname(sc->sc_dev), state)); 2292 } 2293 if (rx_fifo_wr_ptr != rx_fifo_rd_ptr) { 2294 DPRINTF(sc, 2295 ("%s: rx_watchdog: wr & rd ptr different\n", 2296 device_xname(sc->sc_dev))); 2297 needreset = 0; 2298 } 2299 if (sc->sc_rx_fifo_wr_ptr != rx_fifo_wr_ptr) { 2300 DPRINTF(sc, ("%s: rx_watchdog: wr pointer != saved\n", 2301 device_xname(sc->sc_dev))); 2302 needreset = 0; 2303 } 2304 if (sc->sc_rx_fifo_rd_ptr != rx_fifo_rd_ptr) { 2305 DPRINTF(sc, ("%s: rx_watchdog: rd pointer != saved\n", 2306 device_xname(sc->sc_dev))); 2307 needreset = 0; 2308 } 2309 if (needreset) { 2310 aprint_error_dev(sc->sc_dev, 2311 "rx_watchdog: resetting anyway\n"); 2312 gem_init(ifp); 2313 } 2314 } 2315 } 2316 2317 void 2318 gem_watchdog(struct ifnet *ifp) 2319 { 2320 struct gem_softc *sc = ifp->if_softc; 2321 2322 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 2323 "GEM_MAC_RX_CONFIG %x\n", 2324 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 2325 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 2326 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 2327 2328 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 2329 if_statinc(ifp, if_oerrors); 2330 2331 /* Try to get more packets going. */ 2332 gem_init(ifp); 2333 gem_start(ifp); 2334 } 2335 2336 /* 2337 * Initialize the MII Management Interface 2338 */ 2339 void 2340 gem_mifinit(struct gem_softc *sc) 2341 { 2342 bus_space_tag_t t = sc->sc_bustag; 2343 bus_space_handle_t mif = sc->sc_h1; 2344 2345 /* Configure the MIF in frame mode */ 2346 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 2347 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 2348 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 2349 } 2350 2351 /* 2352 * MII interface 2353 * 2354 * The GEM MII interface supports at least three different operating modes: 2355 * 2356 * Bitbang mode is implemented using data, clock and output enable registers. 2357 * 2358 * Frame mode is implemented by loading a complete frame into the frame 2359 * register and polling the valid bit for completion. 2360 * 2361 * Polling mode uses the frame register but completion is indicated by 2362 * an interrupt. 2363 * 2364 */ 2365 static int 2366 gem_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 2367 { 2368 struct gem_softc *sc = device_private(self); 2369 bus_space_tag_t t = sc->sc_bustag; 2370 bus_space_handle_t mif = sc->sc_h1; 2371 int n; 2372 uint32_t v; 2373 2374 #ifdef GEM_DEBUG1 2375 if (sc->sc_debug) 2376 printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg); 2377 #endif 2378 2379 /* Construct the frame command */ 2380 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 2381 GEM_MIF_FRAME_READ; 2382 2383 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2384 for (n = 0; n < 100; n++) { 2385 DELAY(1); 2386 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2387 if (v & GEM_MIF_FRAME_TA0) { 2388 *val = v & GEM_MIF_FRAME_DATA; 2389 return 0; 2390 } 2391 } 2392 2393 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 2394 return ETIMEDOUT; 2395 } 2396 2397 static int 2398 gem_mii_writereg(device_t self, int phy, int reg, uint16_t val) 2399 { 2400 struct gem_softc *sc = device_private(self); 2401 bus_space_tag_t t = sc->sc_bustag; 2402 bus_space_handle_t mif = sc->sc_h1; 2403 int n; 2404 uint32_t v; 2405 2406 #ifdef GEM_DEBUG1 2407 if (sc->sc_debug) 2408 printf("gem_mii_writereg: PHY %d reg %d val %x\n", 2409 phy, reg, val); 2410 #endif 2411 2412 /* Construct the frame command */ 2413 v = GEM_MIF_FRAME_WRITE | 2414 (phy << GEM_MIF_PHY_SHIFT) | 2415 (reg << GEM_MIF_REG_SHIFT) | 2416 (val & GEM_MIF_FRAME_DATA); 2417 2418 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2419 for (n = 0; n < 100; n++) { 2420 DELAY(1); 2421 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2422 if (v & GEM_MIF_FRAME_TA0) 2423 return 0; 2424 } 2425 2426 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 2427 return ETIMEDOUT; 2428 } 2429 2430 static void 2431 gem_mii_statchg(struct ifnet *ifp) 2432 { 2433 struct gem_softc *sc = ifp->if_softc; 2434 #ifdef GEM_DEBUG 2435 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 2436 #endif 2437 2438 #ifdef GEM_DEBUG 2439 if (sc->sc_debug) 2440 printf("gem_mii_statchg: status change: phy = %d\n", 2441 sc->sc_phys[instance]); 2442 #endif 2443 gem_statuschange(sc); 2444 } 2445 2446 /* 2447 * Common status change for gem_mii_statchg() and gem_pint() 2448 */ 2449 void 2450 gem_statuschange(struct gem_softc* sc) 2451 { 2452 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2453 bus_space_tag_t t = sc->sc_bustag; 2454 bus_space_handle_t mac = sc->sc_h1; 2455 int gigabit; 2456 uint32_t rxcfg, txcfg, v; 2457 2458 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 && 2459 IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE) 2460 sc->sc_flags |= GEM_LINK; 2461 else 2462 sc->sc_flags &= ~GEM_LINK; 2463 2464 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2465 gigabit = 1; 2466 else 2467 gigabit = 0; 2468 2469 /* 2470 * The configuration done here corresponds to the steps F) and 2471 * G) and as far as enabling of RX and TX MAC goes also step H) 2472 * of the initialization sequence outlined in section 3.2.1 of 2473 * the GEM Gigabit Ethernet ASIC Specification. 2474 */ 2475 2476 rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG); 2477 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2478 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2479 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2480 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2481 else if (gigabit) { 2482 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2483 txcfg |= GEM_MAC_RX_CARR_EXTEND; 2484 } 2485 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 2486 bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4, 2487 BUS_SPACE_BARRIER_WRITE); 2488 if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2489 aprint_normal_dev(sc->sc_dev, "cannot disable TX MAC\n"); 2490 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg); 2491 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0); 2492 bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4, 2493 BUS_SPACE_BARRIER_WRITE); 2494 if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2495 aprint_normal_dev(sc->sc_dev, "cannot disable RX MAC\n"); 2496 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg); 2497 2498 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) & 2499 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2500 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 2501 2502 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 && 2503 gigabit != 0) 2504 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2505 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2506 else 2507 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2508 GEM_MAC_SLOT_TIME_NORMAL); 2509 2510 /* XIF Configuration */ 2511 if (sc->sc_flags & GEM_LINK) 2512 v = GEM_MAC_XIF_LINK_LED; 2513 else 2514 v = 0; 2515 v |= GEM_MAC_XIF_TX_MII_ENA; 2516 2517 /* If an external transceiver is connected, enable its MII drivers */ 2518 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 2519 if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) { 2520 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 2521 if (gigabit) 2522 v |= GEM_MAC_XIF_GMII_MODE; 2523 else 2524 v &= ~GEM_MAC_XIF_GMII_MODE; 2525 } else 2526 /* Internal MII needs buf enable */ 2527 v |= GEM_MAC_XIF_MII_BUF_ENA; 2528 /* MII needs echo disable if half duplex. */ 2529 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2530 /* turn on full duplex LED */ 2531 v |= GEM_MAC_XIF_FDPLX_LED; 2532 else 2533 /* half duplex -- disable echo */ 2534 v |= GEM_MAC_XIF_ECHO_DISABL; 2535 } else { 2536 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2537 v |= GEM_MAC_XIF_FDPLX_LED; 2538 v |= GEM_MAC_XIF_GMII_MODE; 2539 } 2540 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 2541 2542 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2543 (sc->sc_flags & GEM_LINK) != 0) { 2544 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 2545 txcfg | GEM_MAC_TX_ENABLE); 2546 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 2547 rxcfg | GEM_MAC_RX_ENABLE); 2548 } 2549 } 2550 2551 int 2552 gem_ser_mediachange(struct ifnet *ifp) 2553 { 2554 struct gem_softc *sc = ifp->if_softc; 2555 u_int s, t; 2556 2557 if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER) 2558 return EINVAL; 2559 2560 s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media); 2561 if (s == IFM_AUTO) { 2562 if (sc->sc_mii_media != s) { 2563 #ifdef GEM_DEBUG 2564 aprint_debug_dev(sc->sc_dev, "setting media to auto\n"); 2565 #endif 2566 sc->sc_mii_media = s; 2567 if (ifp->if_flags & IFF_UP) { 2568 gem_pcs_stop(sc, 0); 2569 gem_pcs_start(sc); 2570 } 2571 } 2572 return 0; 2573 } 2574 if (s == IFM_1000_SX) { 2575 t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media) 2576 & (IFM_FDX | IFM_HDX); 2577 if ((sc->sc_mii_media & (IFM_FDX | IFM_HDX)) != t) { 2578 sc->sc_mii_media &= ~(IFM_FDX | IFM_HDX); 2579 sc->sc_mii_media |= t; 2580 #ifdef GEM_DEBUG 2581 aprint_debug_dev(sc->sc_dev, 2582 "setting media to 1000baseSX-%s\n", 2583 t == IFM_FDX ? "FDX" : "HDX"); 2584 #endif 2585 if (ifp->if_flags & IFF_UP) { 2586 gem_pcs_stop(sc, 0); 2587 gem_pcs_start(sc); 2588 } 2589 } 2590 return 0; 2591 } 2592 return EINVAL; 2593 } 2594 2595 void 2596 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2597 { 2598 struct gem_softc *sc = ifp->if_softc; 2599 2600 if ((ifp->if_flags & IFF_UP) == 0) 2601 return; 2602 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2603 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2604 } 2605 2606 static int 2607 gem_ifflags_cb(struct ethercom *ec) 2608 { 2609 struct ifnet *ifp = &ec->ec_if; 2610 struct gem_softc *sc = ifp->if_softc; 2611 u_short change = ifp->if_flags ^ sc->sc_if_flags; 2612 2613 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 2614 return ENETRESET; 2615 else if ((change & IFF_PROMISC) != 0) 2616 gem_setladrf(sc); 2617 return 0; 2618 } 2619 2620 /* 2621 * Process an ioctl request. 2622 */ 2623 int 2624 gem_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 2625 { 2626 struct gem_softc *sc = ifp->if_softc; 2627 int s, error = 0; 2628 2629 s = splnet(); 2630 2631 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2632 error = 0; 2633 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2634 ; 2635 else if (ifp->if_flags & IFF_RUNNING) { 2636 /* 2637 * Multicast list has changed; set the hardware filter 2638 * accordingly. 2639 */ 2640 gem_setladrf(sc); 2641 } 2642 } 2643 2644 /* Try to get things going again */ 2645 if (ifp->if_flags & IFF_UP) 2646 gem_start(ifp); 2647 splx(s); 2648 return (error); 2649 } 2650 2651 static void 2652 gem_inten(struct gem_softc *sc) 2653 { 2654 bus_space_tag_t t = sc->sc_bustag; 2655 bus_space_handle_t h = sc->sc_h1; 2656 uint32_t v; 2657 2658 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 2659 v = GEM_INTR_PCS; 2660 else 2661 v = GEM_INTR_MIF; 2662 bus_space_write_4(t, h, GEM_INTMASK, 2663 ~(GEM_INTR_TX_INTME | 2664 GEM_INTR_TX_EMPTY | 2665 GEM_INTR_TX_MAC | 2666 GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF | 2667 GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL | 2668 GEM_INTR_BERR | v)); 2669 } 2670 2671 bool 2672 gem_resume(device_t self, const pmf_qual_t *qual) 2673 { 2674 struct gem_softc *sc = device_private(self); 2675 2676 gem_inten(sc); 2677 2678 return true; 2679 } 2680 2681 bool 2682 gem_suspend(device_t self, const pmf_qual_t *qual) 2683 { 2684 struct gem_softc *sc = device_private(self); 2685 bus_space_tag_t t = sc->sc_bustag; 2686 bus_space_handle_t h = sc->sc_h1; 2687 2688 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 2689 2690 return true; 2691 } 2692 2693 bool 2694 gem_shutdown(device_t self, int howto) 2695 { 2696 struct gem_softc *sc = device_private(self); 2697 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2698 2699 gem_stop(ifp, 1); 2700 2701 return true; 2702 } 2703 2704 /* 2705 * Set up the logical address filter. 2706 */ 2707 void 2708 gem_setladrf(struct gem_softc *sc) 2709 { 2710 struct ethercom *ec = &sc->sc_ethercom; 2711 struct ifnet *ifp = &ec->ec_if; 2712 struct ether_multi *enm; 2713 struct ether_multistep step; 2714 bus_space_tag_t t = sc->sc_bustag; 2715 bus_space_handle_t h = sc->sc_h1; 2716 uint32_t crc; 2717 uint32_t hash[16]; 2718 uint32_t v; 2719 int i; 2720 2721 /* Get current RX configuration */ 2722 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2723 2724 /* 2725 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2726 * and hash filter. Depending on the case, the right bit will be 2727 * enabled. 2728 */ 2729 v &= ~(GEM_MAC_RX_PROMISCUOUS | GEM_MAC_RX_HASH_FILTER | 2730 GEM_MAC_RX_PROMISC_GRP); 2731 2732 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2733 /* Turn on promiscuous mode */ 2734 v |= GEM_MAC_RX_PROMISCUOUS; 2735 ifp->if_flags |= IFF_ALLMULTI; 2736 goto chipit; 2737 } 2738 2739 /* 2740 * Set up multicast address filter by passing all multicast addresses 2741 * through a crc generator, and then using the high order 8 bits as an 2742 * index into the 256 bit logical address filter. The high order 4 2743 * bits selects the word, while the other 4 bits select the bit within 2744 * the word (where bit 0 is the MSB). 2745 */ 2746 2747 /* Clear hash table */ 2748 memset(hash, 0, sizeof(hash)); 2749 2750 ETHER_LOCK(ec); 2751 ETHER_FIRST_MULTI(step, ec, enm); 2752 while (enm != NULL) { 2753 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2754 /* 2755 * We must listen to a range of multicast addresses. 2756 * For now, just accept all multicasts, rather than 2757 * trying to set only those filter bits needed to match 2758 * the range. (At this time, the only use of address 2759 * ranges is for IP multicast routing, for which the 2760 * range is big enough to require all bits set.) 2761 * XXX should use the address filters for this 2762 */ 2763 ifp->if_flags |= IFF_ALLMULTI; 2764 v |= GEM_MAC_RX_PROMISC_GRP; 2765 ETHER_UNLOCK(ec); 2766 goto chipit; 2767 } 2768 2769 /* Get the LE CRC32 of the address */ 2770 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2771 2772 /* Just want the 8 most significant bits. */ 2773 crc >>= 24; 2774 2775 /* Set the corresponding bit in the filter. */ 2776 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2777 2778 ETHER_NEXT_MULTI(step, enm); 2779 } 2780 ETHER_UNLOCK(ec); 2781 2782 v |= GEM_MAC_RX_HASH_FILTER; 2783 ifp->if_flags &= ~IFF_ALLMULTI; 2784 2785 /* Now load the hash table into the chip (if we are using it) */ 2786 for (i = 0; i < 16; i++) { 2787 bus_space_write_4(t, h, 2788 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2789 hash[i]); 2790 } 2791 2792 chipit: 2793 sc->sc_if_flags = ifp->if_flags; 2794 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2795 } 2796
Indexes created Mon Sep 22 13:09:51 GMT 2025