1 /* $NetBSD: gic_fdt.c,v 1.26 2024/12/02 12:53:07 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2015-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "pci.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: gic_fdt.c,v 1.26 2024/12/02 12:53:07 skrll Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/lwp.h> 41 #include <sys/kmem.h> 42 #include <sys/queue.h> 43 44 #include <dev/pci/pcivar.h> 45 46 #include <arm/cortex/gic_intr.h> 47 #include <arm/cortex/gic_reg.h> 48 #include <arm/cortex/gic_v2m.h> 49 #include <arm/cortex/mpcore_var.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 #define GIC_MAXIRQ 1020 54 55 extern struct pic_softc *pic_list[]; 56 57 struct gic_fdt_softc; 58 struct gic_fdt_irq; 59 60 static int gic_fdt_match(device_t, cfdata_t, void *); 61 static void gic_fdt_attach(device_t, device_t, void *); 62 #if NPCI > 0 && defined(__HAVE_PCI_MSI_MSIX) 63 static void gic_fdt_attach_v2m(struct gic_fdt_softc *, bus_space_tag_t, int); 64 #endif 65 66 static int gic_fdt_intr(void *); 67 68 static void * gic_fdt_establish(device_t, u_int *, int, int, 69 int (*)(void *), void *, const char *); 70 static void gic_fdt_disestablish(device_t, void *); 71 static bool gic_fdt_intrstr(device_t, u_int *, char *, size_t); 72 73 struct fdtbus_interrupt_controller_func gic_fdt_funcs = { 74 .establish = gic_fdt_establish, 75 .disestablish = gic_fdt_disestablish, 76 .intrstr = gic_fdt_intrstr 77 }; 78 79 struct gic_fdt_irqhandler { 80 struct gic_fdt_irq *ih_irq; 81 int (*ih_fn)(void *); 82 void *ih_arg; 83 bool ih_mpsafe; 84 TAILQ_ENTRY(gic_fdt_irqhandler) ih_next; 85 }; 86 87 struct gic_fdt_irq { 88 struct gic_fdt_softc *intr_sc; 89 void *intr_ih; 90 void *intr_arg; 91 int intr_refcnt; 92 int intr_ipl; 93 int intr_level; 94 int intr_mpsafe; 95 TAILQ_HEAD(, gic_fdt_irqhandler) intr_handlers; 96 int intr_irq; 97 }; 98 99 struct gic_fdt_softc { 100 device_t sc_dev; 101 device_t sc_gicdev; 102 int sc_phandle; 103 104 int sc_v2m_count; 105 106 struct gic_fdt_irq *sc_irq[GIC_MAXIRQ]; 107 }; 108 109 CFATTACH_DECL_NEW(gic_fdt, sizeof(struct gic_fdt_softc), 110 gic_fdt_match, gic_fdt_attach, NULL, NULL); 111 112 static const struct device_compatible_entry compat_data[] = { 113 { .compat = "arm,gic-400" }, 114 { .compat = "arm,cortex-a15-gic" }, 115 { .compat = "arm,cortex-a9-gic" }, 116 { .compat = "arm,cortex-a7-gic" }, 117 DEVICE_COMPAT_EOL 118 }; 119 120 #if NPCI > 0 && defined(__HAVE_PCI_MSI_MSIX) 121 static const struct device_compatible_entry v2m_compat_data[] = { 122 { .compat = "arm,gic-v2m-frame" }, 123 DEVICE_COMPAT_EOL 124 }; 125 #endif 126 127 static int 128 gic_fdt_match(device_t parent, cfdata_t cf, void *aux) 129 { 130 struct fdt_attach_args * const faa = aux; 131 132 return of_compatible_match(faa->faa_phandle, compat_data); 133 } 134 135 static void 136 gic_fdt_attach(device_t parent, device_t self, void *aux) 137 { 138 struct gic_fdt_softc * const sc = device_private(self); 139 struct fdt_attach_args * const faa = aux; 140 const int phandle = faa->faa_phandle; 141 bus_addr_t addr_d, addr_c; 142 bus_size_t size_d, size_c; 143 bus_space_handle_t bsh; 144 int error; 145 146 sc->sc_dev = self; 147 sc->sc_phandle = phandle; 148 149 error = fdtbus_register_interrupt_controller(self, phandle, 150 &gic_fdt_funcs); 151 if (error) { 152 aprint_error(": couldn't register with fdtbus: %d\n", error); 153 return; 154 } 155 156 aprint_naive("\n"); 157 aprint_normal(": GIC\n"); 158 159 if (fdtbus_get_reg(sc->sc_phandle, 0, &addr_d, &size_d) != 0) { 160 aprint_error(": couldn't get distributor address\n"); 161 return; 162 } 163 if (fdtbus_get_reg(sc->sc_phandle, 1, &addr_c, &size_c) != 0) { 164 aprint_error(": couldn't get cpu interface address\n"); 165 return; 166 } 167 168 const bus_addr_t addr = ulmin(addr_d, addr_c); 169 const bus_size_t end = ulmax(addr_d + size_d, addr_c + size_c); 170 const bus_size_t size = end - addr; 171 172 error = bus_space_map(faa->faa_bst, addr, size, 0, &bsh); 173 if (error) { 174 aprint_error(": couldn't map registers: %d\n", error); 175 return; 176 } 177 178 struct mpcore_attach_args mpcaa = { 179 .mpcaa_name = "armgic", 180 .mpcaa_memt = faa->faa_bst, 181 .mpcaa_memh = bsh, 182 .mpcaa_off1 = addr_d - addr, 183 .mpcaa_off2 = addr_c - addr, 184 }; 185 186 sc->sc_gicdev = config_found(self, &mpcaa, NULL, CFARGS_NONE); 187 188 arm_fdt_irq_set_handler(armgic_irq_handler); 189 190 #if NPCI > 0 && defined(__HAVE_PCI_MSI_MSIX) 191 for (int child = OF_child(phandle); child; child = OF_peer(child)) { 192 if (!fdtbus_status_okay(child)) 193 continue; 194 if (of_compatible_match(child, v2m_compat_data)) 195 gic_fdt_attach_v2m(sc, faa->faa_bst, child); 196 } 197 #endif 198 } 199 200 #if NPCI > 0 && defined(__HAVE_PCI_MSI_MSIX) 201 static void 202 gic_fdt_attach_v2m(struct gic_fdt_softc *sc, bus_space_tag_t bst, int phandle) 203 { 204 struct gic_v2m_frame *frame; 205 u_int base_spi, num_spis; 206 bus_space_handle_t bsh; 207 bus_addr_t addr; 208 bus_size_t size; 209 210 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 211 aprint_error_dev(sc->sc_gicdev, "couldn't get V2M address\n"); 212 return; 213 } 214 215 if (bus_space_map(bst, addr, size, 0, &bsh) != 0) { 216 aprint_error_dev(sc->sc_gicdev, "couldn't map V2M frame\n"); 217 return; 218 } 219 const uint32_t typer = bus_space_read_4(bst, bsh, GIC_MSI_TYPER); 220 bus_space_unmap(bst, bsh, size); 221 222 if (of_getprop_uint32(phandle, "arm,msi-base-spi", &base_spi)) 223 base_spi = __SHIFTOUT(typer, GIC_MSI_TYPER_BASE); 224 if (of_getprop_uint32(phandle, "arm,msi-num-spis", &num_spis)) 225 num_spis = __SHIFTOUT(typer, GIC_MSI_TYPER_NUMBER); 226 227 frame = kmem_zalloc(sizeof(*frame), KM_SLEEP); 228 frame->frame_reg = addr; 229 frame->frame_pic = pic_list[0]; 230 frame->frame_base = base_spi; 231 frame->frame_count = num_spis; 232 233 if (gic_v2m_init(frame, sc->sc_gicdev, sc->sc_v2m_count++) != 0) { 234 aprint_error_dev(sc->sc_gicdev, "failed to initialize GICv2m\n"); 235 } else { 236 aprint_normal_dev(sc->sc_gicdev, "GICv2m @ %#" PRIx64 237 ", SPIs %u-%u\n", frame->frame_reg, frame->frame_base, 238 frame->frame_base + frame->frame_count - 1); 239 } 240 } 241 #endif 242 243 static void * 244 gic_fdt_establish(device_t dev, u_int *specifier, int ipl, int flags, 245 int (*func)(void *), void *arg, const char *xname) 246 { 247 struct gic_fdt_softc * const sc = device_private(dev); 248 struct gic_fdt_irq *firq; 249 struct gic_fdt_irqhandler *firqh; 250 251 /* 1st cell is the interrupt type; 0 is SPI, 1 is PPI */ 252 /* 2nd cell is the interrupt number */ 253 /* 3rd cell is flags */ 254 255 const u_int type = be32toh(specifier[0]); 256 const u_int intr = be32toh(specifier[1]); 257 const u_int irq = type == 0 ? IRQ_SPI(intr) : IRQ_PPI(intr); 258 const u_int trig = be32toh(specifier[2]) & 0xf; 259 const u_int level = (trig & FDT_INTR_TYPE_DOUBLE_EDGE) 260 ? IST_EDGE : IST_LEVEL; 261 262 const u_int mpsafe = (flags & FDT_INTR_MPSAFE) ? IST_MPSAFE : 0; 263 264 firq = sc->sc_irq[irq]; 265 if (firq == NULL) { 266 firq = kmem_alloc(sizeof(*firq), KM_SLEEP); 267 firq->intr_sc = sc; 268 firq->intr_refcnt = 0; 269 firq->intr_arg = arg; 270 firq->intr_ipl = ipl; 271 firq->intr_level = level; 272 firq->intr_mpsafe = mpsafe; 273 TAILQ_INIT(&firq->intr_handlers); 274 firq->intr_irq = irq; 275 if (arg == NULL) { 276 firq->intr_ih = intr_establish_xname(irq, ipl, 277 level | mpsafe, func, NULL, xname); 278 } else { 279 firq->intr_ih = intr_establish_xname(irq, ipl, 280 level | mpsafe, gic_fdt_intr, firq, xname); 281 } 282 if (firq->intr_ih == NULL) { 283 kmem_free(firq, sizeof(*firq)); 284 return NULL; 285 } 286 sc->sc_irq[irq] = firq; 287 } else { 288 if (firq->intr_arg == NULL && arg != NULL) { 289 device_printf(dev, "cannot share irq with NULL arg\n"); 290 return NULL; 291 } 292 if (firq->intr_ipl != ipl) { 293 device_printf(dev, "cannot share irq with different " 294 "ipl\n"); 295 return NULL; 296 } 297 if (firq->intr_level != level) { 298 device_printf(dev, "cannot share edge and level " 299 "interrupts\n"); 300 return NULL; 301 } 302 if (firq->intr_mpsafe != mpsafe) { 303 device_printf(dev, "cannot share between " 304 "mpsafe/non-mpsafe\n"); 305 return NULL; 306 } 307 } 308 309 firq->intr_refcnt++; 310 311 firqh = kmem_alloc(sizeof(*firqh), KM_SLEEP); 312 firqh->ih_mpsafe = (flags & FDT_INTR_MPSAFE) != 0; 313 firqh->ih_irq = firq; 314 firqh->ih_fn = func; 315 firqh->ih_arg = arg; 316 TAILQ_INSERT_TAIL(&firq->intr_handlers, firqh, ih_next); 317 318 return firq->intr_ih; 319 } 320 321 static void 322 gic_fdt_disestablish(device_t dev, void *ih) 323 { 324 struct gic_fdt_softc * const sc = device_private(dev); 325 struct gic_fdt_irqhandler *firqh; 326 struct gic_fdt_irq *firq; 327 u_int n; 328 329 for (n = 0; n < GIC_MAXIRQ; n++) { 330 firq = sc->sc_irq[n]; 331 if (firq == NULL || firq->intr_ih != ih) 332 continue; 333 334 KASSERT(firq->intr_refcnt > 0); 335 336 if (firq->intr_refcnt > 1) 337 panic("%s: cannot disestablish shared irq", __func__); 338 339 firqh = TAILQ_FIRST(&firq->intr_handlers); 340 kmem_free(firqh, sizeof(*firqh)); 341 intr_disestablish(firq->intr_ih); 342 kmem_free(firq, sizeof(*firq)); 343 sc->sc_irq[n] = NULL; 344 return; 345 } 346 347 panic("%s: interrupt not established", __func__); 348 } 349 350 static int 351 gic_fdt_intr(void *priv) 352 { 353 struct gic_fdt_irq *firq = priv; 354 struct gic_fdt_irqhandler *firqh; 355 int handled = 0; 356 357 TAILQ_FOREACH(firqh, &firq->intr_handlers, ih_next) 358 handled += firqh->ih_fn(firqh->ih_arg); 359 360 return handled; 361 } 362 363 static bool 364 gic_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 365 { 366 /* 1st cell is the interrupt type; 0 is SPI, 1 is PPI */ 367 /* 2nd cell is the interrupt number */ 368 /* 3rd cell is flags */ 369 370 if (!specifier) 371 return false; 372 const u_int type = be32toh(specifier[0]); 373 const u_int intr = be32toh(specifier[1]); 374 const u_int irq = type == 0 ? IRQ_SPI(intr) : IRQ_PPI(intr); 375 376 snprintf(buf, buflen, "GIC irq %d", irq); 377 378 return true; 379 } 380
Indexes created Thu Oct 02 07:10:07 GMT 2025