| /src/sys/arch/emips/stand/common/ |
| start.h | 47 uint32_t gpr[32]; member in struct:_CXTINFO
|
| /src/tests/lib/libc/sys/ |
| t_ptrace_register_wait.h | 40 struct reg gpr; local
79 SYSCALL_REQUIRE(ptrace(PT_GETREGS, child, &gpr, 0) != -1);
84 rgstr = PTRACE_REG_PC(&gpr);
87 rgstr = PTRACE_REG_PC(&gpr);
97 PTRACE_REG_SET_PC(&gpr, rgstr);
100 ptrace(PT_SETREGS, child, &gpr, 0);
103 rgstr = PTRACE_REG_SP(&gpr);
106 rgstr = PTRACE_REG_INTRV(&gpr);
111 ptrace(PT_SETREGS, child, &gpr, 0) != -1);
|
| t_ptrace_x86_wait.h | 2933 struct reg gpr; local
3560 SYSCALL_REQUIRE(ptrace(PT_GETREGS, child, &gpr, 0)
3629 "NetBSD-CORE@*", PT_GETREGS, &gpr, sizeof(gpr)),
3630 sizeof(gpr));
3694 ATF_CHECK_EQ((uint32_t)gpr.r_eax, expected[0].u32);
3695 ATF_CHECK_EQ((uint32_t)gpr.r_ebx, expected[1].u32);
3696 ATF_CHECK_EQ((uint32_t)gpr.r_ecx, expected[2].u32);
3697 ATF_CHECK_EQ((uint32_t)gpr.r_edx, expected[3].u32);
3698 ATF_CHECK_EQ((uint32_t)gpr.r_esi, expected[4].u32)
[all...] |
| /src/sys/arch/sandpoint/stand/altboot/ |
| exception.c | 41 uint32_t gpr[32]; member in struct:cpu_state
98 printf("GPR%02d:", i);
99 printf("%c%08x", (i & 7) == 4 ? ':' : ' ', st->gpr[i]);
107 fp = (uint32_t *)st->gpr[1];
|
| /src/external/gpl3/gcc/dist/libgcc/config/rs6000/ |
| darwin-fallback.c | 279 uint32_t gpr[32]; member in struct:gcc_mcontext32
302 uint32_t gpr[32][2]; member in struct:gcc_mcontext64
389 new_cfa = m64->gpr[1][1];
393 set_offset (i, m64->gpr[i] + 1);
417 new_cfa = m->gpr[1];
421 set_offset (i, m->gpr + i);
|
| linux-unwind.h | 57 unsigned long gpr[32]; member in struct:gcc_regs
212 new_cfa = regs->gpr[__LIBGCC_STACK_POINTER_REGNUM__];
219 fs->regs.reg[2].loc.offset = (long) ®s->gpr[2] - new_cfa;
224 fs->regs.reg[i].loc.offset = (long) ®s->gpr[i] - new_cfa;
428 current = (void *) sigframe->uc.rsave.gpr[1];
|
| /src/external/gpl3/gcc.old/dist/libgcc/config/rs6000/ |
| darwin-fallback.c | 279 uint32_t gpr[32]; member in struct:gcc_mcontext32
302 uint32_t gpr[32][2]; member in struct:gcc_mcontext64
389 new_cfa = m64->gpr[1][1];
393 set_offset (i, m64->gpr[i] + 1);
417 new_cfa = m->gpr[1];
421 set_offset (i, m->gpr + i);
|
| linux-unwind.h | 57 unsigned long gpr[32]; member in struct:gcc_regs
212 new_cfa = regs->gpr[__LIBGCC_STACK_POINTER_REGNUM__];
219 fs->regs.reg[2].loc.offset = (long) ®s->gpr[2] - new_cfa;
224 fs->regs.reg[i].loc.offset = (long) ®s->gpr[i] - new_cfa;
428 current = (void *) sigframe->uc.rsave.gpr[1];
|
| /src/sys/arch/amiga/dev/ |
| if_esreg.h | 47 volatile u_short gpr; /* General Purpose Register */ member in struct:smcregs::__anon955
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| ni_dpm.h | 162 u32 gpr; member in struct:ni_cac_weights
|
| /src/external/gpl3/gcc/dist/gcc/config/nds32/ |
| nds32_isr.h | 423 NDS32_REG16_TAB gpr; member in struct:__anon13394
425 NDS32_REG32_TAB gpr; member in struct:__anon13394
|
| /src/external/gpl3/gcc/dist/gcc/config/rs6000/ |
| rs6000-call.cc | 917 of the GPR, and the other half is empty (typically due to
997 us, because they are smaller than an 8-byte GPR, and so
1493 /* Optimize the simple case where the arg fits in one gpr, except in
1835 passed in the first "half" of the first GPR was already
1948 the GPR code below to compute the appropriate value. */
2425 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
2470 tree gpr, fpr, ovf, sav, t;
2486 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
2508 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
2465 tree gpr, fpr, ovf, sav, t; local
2554 tree gpr, fpr, ovf, sav, reg, t, u; local
[all...] |
| /src/external/gpl3/gcc.old/dist/gcc/config/nds32/ |
| nds32_isr.h | 423 NDS32_REG16_TAB gpr; member in struct:__anon15828
425 NDS32_REG32_TAB gpr; member in struct:__anon15828
|
| /src/external/gpl3/gcc.old/dist/gcc/config/rs6000/ |
| rs6000-call.cc | 925 of the GPR, and the other half is empty (typically due to
1005 us, because they are smaller than an 8-byte GPR, and so
1501 /* Optimize the simple case where the arg fits in one gpr, except in
1843 passed in the first "half" of the first GPR was already
1956 the GPR code below to compute the appropriate value. */
2429 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
2474 tree gpr, fpr, ovf, sav, t;
2490 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
2512 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
2469 tree gpr, fpr, ovf, sav, t; local
2558 tree gpr, fpr, ovf, sav, reg, t, u; local
[all...] |
| /src/external/gpl3/gdb/dist/sim/ppc/ |
| registers.h | 264 gpreg gpr[32]; member in struct:_registers
333 #define GPR(N) cpu_registers(processor)->gpr[N]
|
| /src/external/gpl3/gdb.old/dist/sim/ppc/ |
| registers.h | 264 gpreg gpr[32]; member in struct:_registers
333 #define GPR(N) cpu_registers(processor)->gpr[N]
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| arm-dis.c | 2567 /* Vector VMOV between gpr and half precision register, op == 0. */
2573 /* Vector VMOV between gpr and half precision register, op == 1. */
2690 /* Vector VMOV Vector lane to gpr. */
5683 unsigned long p, w, gpr, imm, add, mod_imm;
5692 gpr = arm_decode_field (given, 16, 18);
5697 gpr = arm_decode_field (given, 16, 18);
5703 gpr = arm_decode_field (given, 16, 19);
5709 gpr = arm_decode_field (given, 16, 19);
5715 gpr = arm_decode_field (given, 16, 19);
5736 func (stream, dis_style_register, "%s", arm_regnames[gpr]);
5682 unsigned long p, w, gpr, imm, add, mod_imm; local
6213 unsigned long gpr = arm_decode_field (given, 12, 15); local
6255 unsigned long gpr = arm_decode_field (given, 0, 3); local
6522 unsigned long gpr = arm_decode_field (given, 0, 3); local
6661 unsigned long gpr = arm_decode_field (given, 9, 11); local
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| arm-dis.c | 2567 /* Vector VMOV between gpr and half precision register, op == 0. */
2573 /* Vector VMOV between gpr and half precision register, op == 1. */
2690 /* Vector VMOV Vector lane to gpr. */
5683 unsigned long p, w, gpr, imm, add, mod_imm;
5692 gpr = arm_decode_field (given, 16, 18);
5697 gpr = arm_decode_field (given, 16, 18);
5703 gpr = arm_decode_field (given, 16, 19);
5709 gpr = arm_decode_field (given, 16, 19);
5715 gpr = arm_decode_field (given, 16, 19);
5736 func (stream, dis_style_register, "%s", arm_regnames[gpr]);
5682 unsigned long p, w, gpr, imm, add, mod_imm; local
6213 unsigned long gpr = arm_decode_field (given, 12, 15); local
6255 unsigned long gpr = arm_decode_field (given, 0, 3); local
6522 unsigned long gpr = arm_decode_field (given, 0, 3); local
6661 unsigned long gpr = arm_decode_field (given, 9, 11); local
[all...] |
| /src/external/gpl3/gcc/dist/gcc/config/i386/ |
| i386.cc | 4541 /* GPR size of varargs save area. */
4698 tree gpr, fpr, ovf, sav, t;
4762 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), unshare_expr (valist),
4778 type = TREE_TYPE (gpr);
4780 gpr, build_int_cst (type, n_gpr * 8));
4831 tree gpr, fpr, ovf, sav, t;
4851 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
4925 GPR save area which guarantees only 8-byte alignment. */
4981 t = build_int_cst (TREE_TYPE (gpr),
4983 t = build2 (GE_EXPR, boolean_type_node, gpr, t)
4685 tree gpr, fpr, ovf, sav, t; local
4818 tree gpr, fpr, ovf, sav, t; local
[all...] |
| /src/external/gpl3/gcc.old/dist/gcc/config/i386/ |
| i386.cc | 4426 /* GPR size of varargs save area. */
4581 tree gpr, fpr, ovf, sav, t;
4645 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), unshare_expr (valist),
4661 type = TREE_TYPE (gpr);
4663 gpr, build_int_cst (type, n_gpr * 8));
4714 tree gpr, fpr, ovf, sav, t;
4734 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
4806 GPR save area which guarantees only 8-byte alignment. */
4862 t = build_int_cst (TREE_TYPE (gpr),
4864 t = build2 (GE_EXPR, boolean_type_node, gpr, t)
4568 tree gpr, fpr, ovf, sav, t; local
4701 tree gpr, fpr, ovf, sav, t; local
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| arm-dis.c | 2567 /* Vector VMOV between gpr and half precision register, op == 0. */
2573 /* Vector VMOV between gpr and half precision register, op == 1. */
2690 /* Vector VMOV Vector lane to gpr. */
5683 unsigned long p, w, gpr, imm, add, mod_imm;
5692 gpr = arm_decode_field (given, 16, 18);
5697 gpr = arm_decode_field (given, 16, 18);
5703 gpr = arm_decode_field (given, 16, 19);
5709 gpr = arm_decode_field (given, 16, 19);
5715 gpr = arm_decode_field (given, 16, 19);
5736 func (stream, dis_style_register, "%s", arm_regnames[gpr]);
5682 unsigned long p, w, gpr, imm, add, mod_imm; local
6213 unsigned long gpr = arm_decode_field (given, 12, 15); local
6255 unsigned long gpr = arm_decode_field (given, 0, 3); local
6522 unsigned long gpr = arm_decode_field (given, 0, 3); local
6661 unsigned long gpr = arm_decode_field (given, 9, 11); local
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| arm-dis.c | 2567 /* Vector VMOV between gpr and half precision register, op == 0. */
2573 /* Vector VMOV between gpr and half precision register, op == 1. */
2690 /* Vector VMOV Vector lane to gpr. */
5683 unsigned long p, w, gpr, imm, add, mod_imm;
5692 gpr = arm_decode_field (given, 16, 18);
5697 gpr = arm_decode_field (given, 16, 18);
5703 gpr = arm_decode_field (given, 16, 19);
5709 gpr = arm_decode_field (given, 16, 19);
5715 gpr = arm_decode_field (given, 16, 19);
5736 func (stream, dis_style_register, "%s", arm_regnames[gpr]);
5682 unsigned long p, w, gpr, imm, add, mod_imm; local
6213 unsigned long gpr = arm_decode_field (given, 12, 15); local
6255 unsigned long gpr = arm_decode_field (given, 0, 3); local
6522 unsigned long gpr = arm_decode_field (given, 0, 3); local
6661 unsigned long gpr = arm_decode_field (given, 9, 11); local
[all...] |
| /src/external/gpl3/gcc.old/dist/gcc/config/s390/ |
| s390.cc | 4237 into a GPR. */
4269 /* Accept floating-point zero operands that fit into a single GPR. */
4706 64 bit value in GPR would be a register pair so here we still
7560 /* Make sure not to return DImode for any GPR with -m31 -mzarch. */
9718 /* Ignore GPR restore insns. */
9793 FPRs as GPR save slots.
9817 GPR save slot. */
9826 stm/lm entirely. So undo the gpr slot allocation in
9869 /* Reserve the GPR save slots for GPRs which need to be saved due to
9890 /* GPR argument regs start at r2. *
12724 tree gpr, fpr, ovf, sav, t; local
[all...] |
| /src/sys/dev/nvmm/x86/ |
| nvmm_x86_vmx.c | 1627 uint64_t type, gpr, oldcr0, realcr0, fakecr0; local
1635 gpr = __SHIFTOUT(qual, VMX_QUAL_CR_GPR);
1636 KASSERT(gpr < 16);
1638 if (gpr == NVMM_X64_GPR_RSP) {
1641 fakecr0 = cpudata->gprs[gpr];
1696 uint64_t type, gpr, oldcr4, cr4; local
1703 gpr = __SHIFTOUT(qual, VMX_QUAL_CR_GPR);
1704 KASSERT(gpr < 16);
1706 if (gpr == NVMM_X64_GPR_RSP) {
1707 gpr = vmx_vmread(VMCS_GUEST_RSP)
1735 uint64_t type, gpr; local
[all...] |
| /src/external/gpl3/gcc/dist/gcc/config/s390/ |
| s390.cc | 417 /* Return TRUE if GPR REGNO is supposed to be restored in the function
4431 into a GPR. */
4463 /* Accept floating-point zero operands that fit into a single GPR. */
4900 64 bit value in GPR would be a register pair so here we still
6022 the price for an overlap is negligible compared to an extra GPR which is
7999 /* Make sure not to return DImode for any GPR with -m31 -mzarch. */
10167 /* Ignore GPR restore insns. */
10242 FPRs as GPR save slots.
10266 GPR save slot. */
10275 stm/lm entirely. So undo the gpr slot allocation i
13242 tree gpr, fpr, ovf, sav, t; local
[all...] |
