| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_ni.c | 1672 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1678 RREG32(GRBM_SOFT_RESET);
1680 WREG32(GRBM_SOFT_RESET, 0);
1681 RREG32(GRBM_SOFT_RESET);
1834 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; local in function:cayman_gpu_soft_reset
1877 grbm_soft_reset = SOFT_RESET_CB |
1892 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
1926 if (grbm_soft_reset) {
1927 tmp = RREG32(GRBM_SOFT_RESET);
1928 tmp |= grbm_soft_reset;
[all...] |
| radeon_r600.c | 1721 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; local in function:r600_gpu_soft_reset
1756 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
1768 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
1784 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
1817 if (grbm_soft_reset) {
1819 tmp |= grbm_soft_reset;
1826 tmp &= ~grbm_soft_reset;
2693 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2694 RREG32(GRBM_SOFT_RESET);
2696 WREG32(GRBM_SOFT_RESET, 0)
[all...] |
| radeon_evergreen.c | 3076 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
3082 RREG32(GRBM_SOFT_RESET);
3084 WREG32(GRBM_SOFT_RESET, 0);
3085 RREG32(GRBM_SOFT_RESET);
3903 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; local in function:evergreen_gpu_soft_reset
3931 grbm_soft_reset |= SOFT_RESET_DB |
3945 grbm_soft_reset |= SOFT_RESET_CP |
3977 if (grbm_soft_reset) {
3978 tmp = RREG32(GRBM_SOFT_RESET);
3979 tmp |= grbm_soft_reset;
[all...] |
| radeon_si.c | 3865 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; local in function:si_gpu_soft_reset
3910 grbm_soft_reset = SOFT_RESET_CB |
3925 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
3940 grbm_soft_reset |= SOFT_RESET_RLC;
3957 if (grbm_soft_reset) {
3958 tmp = RREG32(GRBM_SOFT_RESET);
3959 tmp |= grbm_soft_reset;
3960 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3961 WREG32(GRBM_SOFT_RESET, tmp);
3962 tmp = RREG32(GRBM_SOFT_RESET);
[all...] |
| radeon_cik.c | 4952 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; local in function:cik_gpu_soft_reset
4998 grbm_soft_reset = SOFT_RESET_CP | SOFT_RESET_GFX;
5001 grbm_soft_reset |= SOFT_RESET_CP;
5016 grbm_soft_reset |= SOFT_RESET_RLC;
5035 if (grbm_soft_reset) {
5036 tmp = RREG32(GRBM_SOFT_RESET);
5037 tmp |= grbm_soft_reset;
5038 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5039 WREG32(GRBM_SOFT_RESET, tmp);
5040 tmp = RREG32(GRBM_SOFT_RESET);
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_gfx.h | 301 uint32_t grbm_soft_reset; member in struct:amdgpu_gfx
|
| amdgpu_gfx_v10_0.c | 1812 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1814 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
3866 u32 grbm_soft_reset = 0; local in function:gfx_v10_0_soft_reset
3878 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3879 GRBM_SOFT_RESET, SOFT_RESET_CP,
3881 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3882 GRBM_SOFT_RESET, SOFT_RESET_GFX,
3887 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset
[all...] |
| amdgpu_gfx_v7_0.c | 4634 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; local in function:gfx_v7_0_soft_reset
4646 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4650 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4657 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4664 if (grbm_soft_reset || srbm_soft_reset) {
4678 if (grbm_soft_reset) {
4680 tmp |= grbm_soft_reset;
4681 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4687 tmp &= ~grbm_soft_reset;
|
| amdgpu_gfx_v8_0.c | 4087 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4090 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4951 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; local in function:gfx_v8_0_check_soft_reset
4963 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4964 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4965 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4966 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
4974 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset
5013 u32 grbm_soft_reset = 0; local in function:gfx_v8_0_pre_soft_reset
5054 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; local in function:gfx_v8_0_soft_reset
5116 u32 grbm_soft_reset = 0; local in function:gfx_v8_0_post_soft_reset
[all...] |
| amdgpu_gfx_v9_0.c | 2933 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2935 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
3911 u32 grbm_soft_reset = 0; local in function:gfx_v9_0_soft_reset
3923 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3924 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3925 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3926 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3930 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset
[all...] |
