1 /* $NetBSD: gtmr.c,v 1.50 2025/01/09 06:55:25 rin Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.50 2025/01/09 06:55:25 rin Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/kernel.h> 40 #include <sys/lock.h> 41 #include <sys/percpu.h> 42 #include <sys/proc.h> 43 #include <sys/systm.h> 44 #include <sys/timetc.h> 45 #include <sys/cpu.h> 46 47 #include <prop/proplib.h> 48 49 #include <arm/locore.h> 50 #include <arm/cpufunc.h> 51 52 #include <arm/cortex/gtmr_var.h> 53 #include <arm/cortex/mpcore_var.h> 54 55 static int gtmr_match(device_t, cfdata_t, void *); 56 static void gtmr_attach(device_t, device_t, void *); 57 58 static u_int gtmr_get_timecount(struct timecounter *); 59 60 static uint64_t gtmr_read_cntct(struct gtmr_softc *); 61 static uint32_t gtmr_read_ctl(struct gtmr_softc *); 62 static void gtmr_write_ctl(struct gtmr_softc *, uint32_t); 63 static void gtmr_write_tval(struct gtmr_softc *, uint32_t); 64 static void gtmr_write_cval(struct gtmr_softc *, uint64_t); 65 66 static struct gtmr_softc gtmr_sc; 67 68 struct gtmr_percpu { 69 uint32_t pc_delta; 70 }; 71 72 static struct timecounter gtmr_timecounter = { 73 .tc_get_timecount = gtmr_get_timecount, 74 .tc_poll_pps = 0, 75 .tc_counter_mask = ~0u, 76 .tc_frequency = 0, /* set by cpu_initclocks() */ 77 .tc_name = NULL, /* set by attach */ 78 .tc_quality = 500, 79 .tc_priv = >mr_sc, 80 .tc_next = NULL, 81 }; 82 83 CFATTACH_DECL_NEW(armgtmr, 0, gtmr_match, gtmr_attach, NULL, NULL); 84 85 /* ARGSUSED */ 86 static int 87 gtmr_match(device_t parent, cfdata_t cf, void *aux) 88 { 89 struct mpcore_attach_args * const mpcaa = aux; 90 91 if (gtmr_sc.sc_dev != NULL) 92 return 0; 93 94 /* Generic Timer is always implemented in ARMv8-A */ 95 if (!cpu_gtmr_exists_p()) 96 return 0; 97 98 if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0) 99 return 0; 100 101 return 1; 102 } 103 104 static void 105 gtmr_attach(device_t parent, device_t self, void *aux) 106 { 107 struct mpcore_attach_args * const mpcaa = aux; 108 struct gtmr_softc *sc = >mr_sc; 109 prop_dictionary_t dict = device_properties(self); 110 prop_dictionary_t pdict = device_properties(device_parent(self)); 111 char freqbuf[sizeof("X.XXX SHz")]; 112 bool flag; 113 114 /* 115 * This runs at a fixed frequency of 1 to 50MHz. 116 */ 117 if (!prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq)) 118 sc->sc_freq = gtmr_cntfrq_read(); 119 120 if (!prop_dictionary_get_bool(dict, "physical", &sc->sc_physical)) 121 prop_dictionary_get_bool(pdict, "physical", &sc->sc_physical); 122 123 KASSERT(sc->sc_freq != 0); 124 125 humanize_number(freqbuf, sizeof(freqbuf), sc->sc_freq, "Hz", 1000); 126 127 aprint_naive("\n"); 128 aprint_normal(": Generic Timer (%s, %s)\n", freqbuf, 129 sc->sc_physical ? "physical" : "virtual"); 130 131 #if defined(__arm__) 132 if (prop_dictionary_get_bool(dict, "arm,cpu-registers-not-fw-configured", &flag) && flag) { 133 sc->sc_flags |= GTMR_FLAG_CPU_REGISTERS_NOT_FW_CONFIGURED; 134 aprint_debug_dev(self, "CPU registers not initialized by firmware\n"); 135 } 136 #endif 137 138 if (prop_dictionary_get_bool(dict, "sun50i-a64-unstable-timer", &flag) && flag) { 139 sc->sc_flags |= GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER; 140 aprint_debug_dev(self, "enabling Allwinner A64 timer workaround\n"); 141 } 142 143 device_set_private(self, sc); 144 sc->sc_dev = self; 145 146 #ifdef DIAGNOSTIC 147 sc->sc_percpu = percpu_alloc(sizeof(struct gtmr_percpu)); 148 #endif 149 150 evcnt_attach_dynamic(&sc->sc_ev_missing_ticks, EVCNT_TYPE_MISC, NULL, 151 device_xname(self), "missing interrupts"); 152 153 if (mpcaa->mpcaa_irq != -1) { 154 sc->sc_global_ih = intr_establish(mpcaa->mpcaa_irq, IPL_CLOCK, 155 IST_LEVEL | IST_MPSAFE, gtmr_intr, NULL); 156 if (sc->sc_global_ih == NULL) 157 panic("%s: unable to register timer interrupt", __func__); 158 aprint_normal_dev(self, "interrupting on irq %d\n", 159 mpcaa->mpcaa_irq); 160 } 161 162 const uint32_t cnt_frq = gtmr_cntfrq_read(); 163 if (cnt_frq == 0) { 164 aprint_verbose_dev(self, "cp15 CNT_FRQ not set\n"); 165 } else if (cnt_frq != sc->sc_freq) { 166 aprint_verbose_dev(self, 167 "cp15 CNT_FRQ (%u) differs from supplied frequency\n", 168 cnt_frq); 169 } 170 171 gtmr_timecounter.tc_name = device_xname(sc->sc_dev); 172 gtmr_timecounter.tc_frequency = sc->sc_freq; 173 gtmr_timecounter.tc_priv = sc; 174 175 tc_init(>mr_timecounter); 176 177 /* Disable the timer until we are ready */ 178 gtmr_write_ctl(sc, 0); 179 } 180 181 static uint64_t 182 gtmr_read_cntct(struct gtmr_softc *sc) 183 { 184 isb(); 185 186 if (ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) { 187 /* 188 * The Allwinner A64 SoC has an unstable architectural timer. 189 * To workaround this problem, ignore reads where the lower 190 * 10 bits are all 0s or 1s. 191 */ 192 uint64_t val; 193 u_int bits; 194 do { 195 val = sc->sc_physical ? gtmr_cntpct_read() : gtmr_cntvct_read(); 196 bits = val & __BITS(9,0); 197 } while (bits == 0 || bits == __BITS(9,0)); 198 return val; 199 } 200 201 return sc->sc_physical ? gtmr_cntpct_read() : gtmr_cntvct_read(); 202 } 203 204 static uint32_t 205 gtmr_read_ctl(struct gtmr_softc *sc) 206 { 207 isb(); 208 209 if (sc->sc_physical) 210 return gtmr_cntp_ctl_read(); 211 else 212 return gtmr_cntv_ctl_read(); 213 } 214 215 static void 216 gtmr_write_ctl(struct gtmr_softc *sc, uint32_t val) 217 { 218 if (sc->sc_physical) 219 gtmr_cntp_ctl_write(val); 220 else 221 gtmr_cntv_ctl_write(val); 222 223 isb(); 224 } 225 226 static void 227 gtmr_write_tval(struct gtmr_softc *sc, uint32_t val) 228 { 229 if (sc->sc_physical) 230 gtmr_cntp_tval_write(val); 231 else 232 gtmr_cntv_tval_write(val); 233 234 isb(); 235 } 236 237 static void 238 gtmr_write_cval(struct gtmr_softc *sc, uint64_t val) 239 { 240 if (sc->sc_physical) 241 gtmr_cntp_cval_write(val); 242 else 243 gtmr_cntv_cval_write(val); 244 245 isb(); 246 } 247 248 249 void 250 gtmr_init_cpu_clock(struct cpu_info *ci) 251 { 252 struct gtmr_softc * const sc = >mr_sc; 253 uint32_t cntk; 254 uint64_t ctl; 255 256 KASSERT(ci == curcpu()); 257 258 /* XXX hmm... called from cpu_hatch which hasn't lowered ipl yet */ 259 int s = splsched(); 260 261 #if defined(__arm__) 262 if ((sc->sc_flags & GTMR_FLAG_CPU_REGISTERS_NOT_FW_CONFIGURED) != 0) { 263 armreg_cnt_frq_write(sc->sc_freq); 264 } 265 #endif 266 267 /* 268 * Allow the virtual and physical counters to be accessed from 269 * usermode. (PL0) 270 */ 271 cntk = gtmr_cntk_ctl_read(); 272 cntk &= ~(CNTKCTL_PL0PTEN | CNTKCTL_PL0VTEN | CNTKCTL_EVNTEN); 273 if (sc->sc_physical) { 274 cntk |= CNTKCTL_PL0PCTEN; 275 cntk &= ~CNTKCTL_PL0VCTEN; 276 } else { 277 cntk |= CNTKCTL_PL0VCTEN; 278 cntk &= ~CNTKCTL_PL0PCTEN; 279 } 280 gtmr_cntk_ctl_write(cntk); 281 isb(); 282 283 /* 284 * enable timer and stop masking the timer. 285 */ 286 ctl = gtmr_read_ctl(sc); 287 ctl &= ~CNTCTL_IMASK; 288 ctl |= CNTCTL_ENABLE; 289 gtmr_write_ctl(sc, ctl); 290 291 /* 292 * Get now and update the compare timer. 293 */ 294 ci->ci_lastintr = gtmr_read_cntct(sc); 295 gtmr_write_tval(sc, sc->sc_autoinc); 296 297 splx(s); 298 299 KASSERT(gtmr_read_cntct(sc) != 0); 300 } 301 302 void 303 gtmr_cpu_initclocks(void) 304 { 305 struct gtmr_softc * const sc = >mr_sc; 306 307 KASSERT(sc->sc_dev != NULL); 308 KASSERT(sc->sc_freq != 0); 309 310 sc->sc_autoinc = sc->sc_freq / hz; 311 312 gtmr_init_cpu_clock(curcpu()); 313 } 314 315 void 316 gtmr_delay(unsigned int n) 317 { 318 struct gtmr_softc * const sc = >mr_sc; 319 320 KASSERT(sc != NULL); 321 322 uint32_t freq = sc->sc_freq ? sc->sc_freq : gtmr_cntfrq_read(); 323 KASSERT(freq != 0); 324 325 const unsigned int incr_per_us = howmany(freq, 1000000); 326 int64_t ticks = (int64_t)n * incr_per_us; 327 328 uint64_t last = gtmr_read_cntct(sc); 329 330 while (ticks > 0) { 331 SPINLOCK_BACKOFF_HOOK; 332 uint64_t curr = gtmr_read_cntct(sc); 333 if (curr >= last) 334 ticks -= (curr - last); 335 else 336 ticks -= (UINT64_MAX - curr + last); 337 last = curr; 338 } 339 } 340 341 /* 342 * gtmr_intr: 343 * 344 * Handle the hardclock interrupt. 345 */ 346 int 347 gtmr_intr(void *arg) 348 { 349 struct cpu_info * const ci = curcpu(); 350 struct clockframe * const cf = arg; 351 struct gtmr_softc * const sc = >mr_sc; 352 353 const uint32_t ctl = gtmr_read_ctl(sc); 354 if ((ctl & (CNTCTL_ENABLE|CNTCTL_ISTATUS)) != (CNTCTL_ENABLE|CNTCTL_ISTATUS)) { 355 aprint_debug_dev(ci->ci_dev, "spurious timer interrupt (ctl=%#x)\n", ctl); 356 return 0; 357 } 358 359 const uint64_t now = gtmr_read_cntct(sc); 360 uint64_t delta = now - ci->ci_lastintr; 361 362 #ifdef DIAGNOSTIC 363 struct gtmr_percpu *pc = NULL; 364 if (!ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) { 365 const uint64_t then = sc->sc_physical ? gtmr_cntp_cval_read() : gtmr_cntv_cval_read(); 366 pc = percpu_getref(sc->sc_percpu); 367 KASSERTMSG(then <= now, "%"PRId64, now - then); 368 KASSERTMSG(then + pc->pc_delta >= ci->ci_lastintr + sc->sc_autoinc, 369 "%"PRId64, then + pc->pc_delta - ci->ci_lastintr - sc->sc_autoinc); 370 } 371 #endif 372 373 if (!ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) { 374 KASSERTMSG(delta > sc->sc_autoinc / 100, 375 "%s: interrupting too quickly (delta=%"PRIu64") autoinc=%lu", 376 ci->ci_data.cpu_name, delta, sc->sc_autoinc); 377 } 378 379 /* 380 * If we got interrupted too soon (delta < sc->sc_autoinc) 381 * or we missed (or almost missed) a tick 382 * (delta >= 7 * sc->sc_autoinc / 4), don't try to adjust for jitter. 383 */ 384 if (delta >= sc->sc_autoinc && delta <= 7 * sc->sc_autoinc / 4) { 385 delta -= sc->sc_autoinc; 386 } else { 387 delta = 0; 388 } 389 390 isb(); 391 if (ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) { 392 gtmr_write_cval(sc, now + sc->sc_autoinc - delta); 393 } else { 394 gtmr_write_tval(sc, sc->sc_autoinc - delta); 395 } 396 397 ci->ci_lastintr = now; 398 399 #ifdef DIAGNOSTIC 400 if (!ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) { 401 KASSERT(delta == (uint32_t) delta); 402 pc->pc_delta = delta; 403 percpu_putref(sc->sc_percpu); 404 } 405 #endif 406 407 hardclock(cf); 408 409 sc->sc_ev_missing_ticks.ev_count += delta / sc->sc_autoinc; 410 411 return 1; 412 } 413 414 void 415 setstatclockrate(int newhz) 416 { 417 } 418 419 static u_int 420 gtmr_get_timecount(struct timecounter *tc) 421 { 422 struct gtmr_softc * const sc = tc->tc_priv; 423 424 return (u_int) gtmr_read_cntct(sc); 425 } 426
Indexes created Sun Sep 21 20:09:37 GMT 2025