1 /* $NetBSD: hd64461pcmcia.c,v 1.57 2025/08/06 11:11:34 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: hd64461pcmcia.c,v 1.57 2025/08/06 11:11:34 andvar Exp $"); 34 35 #include "opt_hd64461pcmcia.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/kmem.h> 41 #include <sys/kthread.h> 42 #include <sys/boot_flag.h> 43 #include <sys/bus.h> 44 45 #include <machine/intr.h> 46 47 #include <dev/pcmcia/pcmciareg.h> 48 #include <dev/pcmcia/pcmciavar.h> 49 #include <dev/pcmcia/pcmciachip.h> 50 51 #include <sh3/bscreg.h> 52 53 #include <hpcsh/dev/hd64461/hd64461reg.h> 54 #include <hpcsh/dev/hd64461/hd64461var.h> 55 #include <hpcsh/dev/hd64461/hd64461intcreg.h> 56 #include <hpcsh/dev/hd64461/hd64461gpioreg.h> 57 #include <hpcsh/dev/hd64461/hd64461pcmciavar.h> 58 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 59 60 #include <hpcsh/bus_util.h> /* for _BUS_SPACE_WRITE(), et cetera */ 61 62 #include "locators.h" 63 64 #ifdef HD64461PCMCIA_DEBUG 65 #define DPRINTF_ENABLE 66 #define DPRINTF_DEBUG hd64461pcmcia_debug 67 #endif 68 #include <machine/debug.h> 69 70 enum controller_channel { 71 CHANNEL_0 = 0, 72 CHANNEL_1 = 1, 73 CHANNEL_MAX = 2 74 }; 75 76 enum memory_window_mode { 77 MEMWIN_16M_MODE, 78 MEMWIN_32M_MODE 79 }; 80 81 enum memory_window_16 { 82 MEMWIN_16M_COMMON_0, 83 MEMWIN_16M_COMMON_1, 84 MEMWIN_16M_COMMON_2, 85 MEMWIN_16M_COMMON_3, 86 }; 87 #define MEMWIN_16M_MAX 4 88 89 enum memory_window_32 { 90 MEMWIN_32M_ATTR, 91 MEMWIN_32M_COMMON_0, 92 MEMWIN_32M_COMMON_1, 93 }; 94 #define MEMWIN_32M_MAX 3 95 96 enum hd64461pcmcia_event_type { 97 EVENT_NONE, 98 EVENT_INSERT, 99 EVENT_REMOVE, 100 }; 101 #define EVENT_QUEUE_MAX 5 102 103 struct hd64461pcmcia_softc; /* forward declaration */ 104 105 struct hd64461pcmcia_window_cookie { 106 bus_space_tag_t wc_tag; 107 bus_space_handle_t wc_handle; 108 int wc_size; 109 int wc_window; 110 }; 111 112 struct hd64461pcmcia_channel { 113 struct hd64461pcmcia_softc *ch_parent; 114 device_t ch_pcmcia; 115 enum controller_channel ch_channel; 116 117 /* memory space */ 118 enum memory_window_mode ch_memory_window_mode; 119 bus_space_tag_t ch_memt; 120 bus_space_handle_t ch_memh; 121 bus_addr_t ch_membase_addr; 122 bus_size_t ch_memsize; 123 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 124 125 /* I/O space */ 126 bus_space_tag_t ch_iot; 127 bus_addr_t ch_iobase; 128 bus_size_t ch_iosize; 129 130 /* card interrupt */ 131 int (*ch_ih_card_func)(void *); 132 void *ch_ih_card_arg; 133 int ch_attached; 134 }; 135 136 struct hd64461pcmcia_event { 137 int __queued; 138 enum hd64461pcmcia_event_type pe_type; 139 struct hd64461pcmcia_channel *pe_ch; 140 SIMPLEQ_ENTRY(hd64461pcmcia_event) pe_link; 141 }; 142 143 struct hd64461pcmcia_softc { 144 device_t sc_dev; 145 146 enum hd64461_module_id sc_module_id; 147 int sc_shutdown; 148 149 /* CSC event */ 150 lwp_t *sc_event_thread; 151 struct hd64461pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 152 SIMPLEQ_HEAD (, hd64461pcmcia_event) sc_event_head; 153 154 struct hd64461pcmcia_channel sc_ch[CHANNEL_MAX]; 155 }; 156 157 STATIC int hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 158 struct pcmcia_mem_handle *); 159 STATIC void hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 160 struct pcmcia_mem_handle *); 161 STATIC int hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 162 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 163 STATIC void hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 164 STATIC int hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 165 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 166 STATIC void hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t, 167 struct pcmcia_io_handle *); 168 STATIC int hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 169 bus_size_t, struct pcmcia_io_handle *, int *); 170 STATIC void hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 171 STATIC void hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 172 STATIC void hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 173 STATIC void hd64461pcmcia_chip_socket_settype(pcmcia_chipset_handle_t, int); 174 STATIC void *hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 175 struct pcmcia_function *, int, int (*)(void *), void *); 176 STATIC void hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 177 void *); 178 179 STATIC struct pcmcia_chip_functions hd64461pcmcia_functions = { 180 hd64461pcmcia_chip_mem_alloc, 181 hd64461pcmcia_chip_mem_free, 182 hd64461pcmcia_chip_mem_map, 183 hd64461pcmcia_chip_mem_unmap, 184 hd64461pcmcia_chip_io_alloc, 185 hd64461pcmcia_chip_io_free, 186 hd64461pcmcia_chip_io_map, 187 hd64461pcmcia_chip_io_unmap, 188 hd64461pcmcia_chip_intr_establish, 189 hd64461pcmcia_chip_intr_disestablish, 190 hd64461pcmcia_chip_socket_enable, 191 hd64461pcmcia_chip_socket_disable, 192 hd64461pcmcia_chip_socket_settype, 193 }; 194 195 STATIC int hd64461pcmcia_match(device_t, cfdata_t, void *); 196 STATIC void hd64461pcmcia_attach(device_t, device_t, void *); 197 STATIC int hd64461pcmcia_print(void *, const char *); 198 STATIC int hd64461pcmcia_submatch(device_t, cfdata_t, const int *, void *); 199 200 CFATTACH_DECL_NEW(hd64461pcmcia, sizeof(struct hd64461pcmcia_softc), 201 hd64461pcmcia_match, hd64461pcmcia_attach, NULL, NULL); 202 203 STATIC void hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *, 204 enum controller_channel); 205 /* hot plug */ 206 STATIC void hd64461pcmcia_event_thread(void *); 207 STATIC void queue_event(struct hd64461pcmcia_channel *, 208 enum hd64461pcmcia_event_type); 209 /* interrupt handler */ 210 STATIC int hd64461pcmcia_channel0_intr(void *); 211 STATIC int hd64461pcmcia_channel1_intr(void *); 212 /* card status */ 213 STATIC enum hd64461pcmcia_event_type detect_card(enum controller_channel); 214 STATIC void hd64461pcmcia_power_off(enum controller_channel); 215 STATIC void hd64461pcmcia_power_on(enum controller_channel); 216 /* memory window access ops */ 217 STATIC void hd64461pcmcia_memory_window_mode(enum controller_channel, 218 enum memory_window_mode)__attribute__((__unused__)); 219 STATIC void hd64461pcmcia_memory_window_16(enum controller_channel, 220 enum memory_window_16); 221 /* bus width */ 222 STATIC void hd64461_set_bus_width(enum controller_channel, int); 223 #ifdef HD64461PCMCIA_DEBUG 224 STATIC void hd64461pcmcia_info(struct hd64461pcmcia_softc *); 225 #endif 226 227 /* 228 * Workaround for SH-3 PCMCIA bug on area 6: 229 * 230 * According to TECH I vol. 14 (CQ Publishing, Tokyo, 2002) p. 184, 231 * byte-access to area 6 becomes word-access if preceding access is 232 * word-wise. Inserting a dummy byte-access works around the problem. 233 * Area 5 is not affected by this bug. 234 * 235 * Therefore, we insert a dummy byte-wise read to HD64461_PCC0_MEMBASE 236 * before any byte-access to area 6 (channel 0). 237 * 238 * Note that we used to use HD64461_PCC0_IOBASE for this purpose. But, 239 * read access to that register can modify device states, which breaks 240 * ep(4) at least. On the other hand, since HD64461_PCC0_MEMBASE is 241 * assigned to attribute memory, read access should be harmless. 242 */ 243 STATIC void fixup_sh3_pcmcia_area6(bus_space_tag_t); 244 #define _BUS_SPACE_ACCESS_HOOK() \ 245 do { \ 246 uint8_t dummy __unused = \ 247 *(volatile uint8_t *)HD64461_PCC0_MEMBASE; \ 248 } while (0) 249 _BUS_SPACE_READ(_sh3_pcmcia_bug, 1, 8) 250 _BUS_SPACE_READ_MULTI(_sh3_pcmcia_bug, 1, 8) 251 _BUS_SPACE_READ_REGION(_sh3_pcmcia_bug, 1, 8) 252 _BUS_SPACE_WRITE(_sh3_pcmcia_bug, 1, 8) 253 _BUS_SPACE_WRITE_MULTI(_sh3_pcmcia_bug, 1, 8) 254 _BUS_SPACE_WRITE_REGION(_sh3_pcmcia_bug, 1, 8) 255 _BUS_SPACE_SET_MULTI(_sh3_pcmcia_bug, 1, 8) 256 _BUS_SPACE_COPY_REGION(_sh3_pcmcia_bug, 1, 8) 257 #undef _BUS_SPACE_ACCESS_HOOK 258 259 #define DELAY_MS(x) delay((x) * 1000) 260 261 STATIC int 262 hd64461pcmcia_match(device_t parent, cfdata_t cf, void *aux) 263 { 264 struct hd64461_attach_args *ha = aux; 265 266 return (ha->ha_module_id == HD64461_MODULE_PCMCIA); 267 } 268 269 STATIC void 270 hd64461pcmcia_attach(device_t parent, device_t self, void *aux) 271 { 272 struct hd64461_attach_args *ha = aux; 273 struct hd64461pcmcia_softc *sc; 274 int error __diagused; 275 276 sc = device_private(self); 277 sc->sc_dev = self; 278 279 sc->sc_module_id = ha->ha_module_id; 280 281 aprint_naive("\n"); 282 aprint_normal("\n"); 283 284 #ifdef HD64461PCMCIA_DEBUG 285 hd64461pcmcia_info(sc); 286 #endif 287 /* Channel 0/1 common CSC event queue */ 288 SIMPLEQ_INIT (&sc->sc_event_head); 289 290 error = kthread_create(PRI_NONE, 0, NULL, 291 hd64461pcmcia_event_thread, sc, 292 &sc->sc_event_thread, 293 "%s", device_xname(self)); 294 KASSERT(error == 0); 295 296 config_pending_incr(self); 297 298 /* XXX: TODO */ 299 if (!pmf_device_register(self, NULL, NULL)) 300 aprint_error_dev(self, "unable to establish power handler\n"); 301 } 302 303 STATIC void 304 hd64461pcmcia_event_thread(void *arg) 305 { 306 struct hd64461pcmcia_softc *sc = arg; 307 struct hd64461pcmcia_event *pe; 308 int s; 309 310 #if !defined(HD64461PCMCIA_REORDER_ATTACH) 311 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 312 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 313 #else 314 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 315 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 316 #endif 317 config_pending_decr(sc->sc_dev); 318 319 while (!sc->sc_shutdown) { 320 tsleep(sc, PWAIT, "CSC wait", 0); 321 s = splhigh(); 322 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 323 splx(s); 324 switch (pe->pe_type) { 325 default: 326 printf("%s: unknown event.\n", __func__); 327 break; 328 case EVENT_INSERT: 329 DPRINTF("insert event.\n"); 330 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 331 break; 332 case EVENT_REMOVE: 333 DPRINTF("remove event.\n"); 334 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 335 DETACH_FORCE); 336 break; 337 } 338 s = splhigh(); 339 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe_link); 340 pe->__queued = 0; 341 } 342 splx(s); 343 } 344 345 sc->sc_event_thread = NULL; 346 kthread_exit(0); 347 /* NOTREACHED */ 348 } 349 350 STATIC int 351 hd64461pcmcia_print(void *arg, const char *pnp) 352 { 353 354 if (pnp) 355 aprint_normal("pcmcia at %s", pnp); 356 357 return (UNCONF); 358 } 359 360 STATIC int 361 hd64461pcmcia_submatch(device_t parent, cfdata_t cf, 362 const int *ldesc, void *aux) 363 { 364 struct pcmciabus_attach_args *paa = aux; 365 struct hd64461pcmcia_channel *ch = 366 (struct hd64461pcmcia_channel *)paa->pch; 367 368 if (ch->ch_channel == CHANNEL_0) { 369 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 370 PCMCIABUSCF_CONTROLLER_DEFAULT && 371 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 372 return 0; 373 } else { 374 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 375 PCMCIABUSCF_CONTROLLER_DEFAULT && 376 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 377 return 0; 378 } 379 paa->pct = (pcmcia_chipset_tag_t)&hd64461pcmcia_functions; 380 381 return (config_match(parent, cf, aux)); 382 } 383 384 STATIC void 385 hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *sc, 386 enum controller_channel channel) 387 { 388 device_t parent = sc->sc_dev; 389 struct hd64461pcmcia_channel *ch = &sc->sc_ch[channel]; 390 struct pcmciabus_attach_args paa; 391 bus_addr_t membase; 392 int i; 393 394 ch->ch_parent = sc; 395 ch->ch_channel = channel; 396 397 /* 398 * Continuous 16-MB Area Mode 399 */ 400 /* Attribute/Common memory extent */ 401 membase = (channel == CHANNEL_0) 402 ? HD64461_PCC0_MEMBASE : HD64461_PCC1_MEMBASE; 403 404 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 405 membase, 0x01000000); /* 16MB */ 406 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x01000000, 407 0x01000000, 0x01000000, 0, &ch->ch_membase_addr, 408 &ch->ch_memh); 409 if (channel == CHANNEL_0) 410 fixup_sh3_pcmcia_area6(ch->ch_memt); 411 412 /* Common memory space extent */ 413 ch->ch_memsize = 0x01000000; 414 for (i = 0; i < MEMWIN_16M_MAX; i++) { 415 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 416 membase + 0x01000000, 417 ch->ch_memsize); 418 if (channel == CHANNEL_0) 419 fixup_sh3_pcmcia_area6(ch->ch_cmemt[i]); 420 } 421 422 /* I/O port extent and interrupt staff */ 423 hd64461pcmcia_chip_socket_disable(ch); /* enable CSC interrupt only */ 424 425 if (channel == CHANNEL_0) { 426 ch->ch_iobase = 0; 427 ch->ch_iosize = HD64461_PCC0_IOSIZE; 428 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 429 HD64461_PCC0_IOBASE, 430 ch->ch_iosize); 431 fixup_sh3_pcmcia_area6(ch->ch_iot); 432 433 hd6446x_intr_establish(HD64461_INTC_PCC0, IST_LEVEL, IPL_TTY, 434 hd64461pcmcia_channel0_intr, ch); 435 } else { 436 hd64461_set_bus_width(CHANNEL_1, PCMCIA_WIDTH_IO16); 437 hd6446x_intr_establish(HD64461_INTC_PCC1, IST_EDGE, IPL_TTY, 438 hd64461pcmcia_channel1_intr, ch); 439 } 440 441 paa.paa_busname = "pcmcia"; 442 paa.pch = (pcmcia_chipset_handle_t)ch; 443 444 ch->ch_pcmcia = config_found(parent, &paa, hd64461pcmcia_print, 445 CFARGS(.submatch = hd64461pcmcia_submatch)); 446 447 if (ch->ch_pcmcia && (detect_card(ch->ch_channel) == EVENT_INSERT)) { 448 ch->ch_attached = 1; 449 pcmcia_card_attach(ch->ch_pcmcia); 450 } 451 } 452 453 STATIC int 454 hd64461pcmcia_channel0_intr(void *arg) 455 { 456 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 457 uint8_t r; 458 int ret = 0; 459 460 r = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 461 /* clear interrupt (edge source only) */ 462 hd64461_reg_write_1(HD64461_PCC0CSCR_REG8, 0); 463 464 if (r & HD64461_PCC0CSCR_P0IREQ) { 465 if (ch->ch_ih_card_func) { 466 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 467 } else 468 DPRINTF("spurious IREQ interrupt.\n"); 469 } 470 471 if (r & HD64461_PCC0CSCR_P0CDC) 472 queue_event(ch, detect_card(ch->ch_channel)); 473 474 return ret; 475 } 476 477 STATIC int 478 hd64461pcmcia_channel1_intr(void *arg) 479 { 480 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 481 uint8_t r; 482 int ret = 0; 483 484 r = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 485 /* clear interrupt */ 486 hd64461_reg_write_1(HD64461_PCC1CSCR_REG8, 0); 487 488 if (r & HD64461_PCC1CSCR_P1RC) { 489 if (ch->ch_ih_card_func) 490 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 491 else 492 DPRINTF("spurious READY interrupt.\n"); 493 } 494 495 if (r & HD64461_PCC1CSCR_P1CDC) 496 queue_event(ch, detect_card(ch->ch_channel)); 497 498 return ret; 499 } 500 501 STATIC void 502 queue_event(struct hd64461pcmcia_channel *ch, 503 enum hd64461pcmcia_event_type type) 504 { 505 struct hd64461pcmcia_event *pe, *pool; 506 struct hd64461pcmcia_softc *sc = ch->ch_parent; 507 int i; 508 int s = splhigh(); 509 510 if (type == EVENT_NONE) 511 goto out; 512 513 pe = 0; 514 pool = sc->sc_event_pool; 515 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 516 if (!pool[i].__queued) { 517 pe = &pool[i]; 518 break; 519 } 520 } 521 522 if (pe == 0) { 523 printf("%s: event FIFO overflow (max %d).\n", __func__, 524 EVENT_QUEUE_MAX); 525 goto out; 526 } 527 528 if ((ch->ch_attached && (type == EVENT_INSERT)) || 529 (!ch->ch_attached && (type == EVENT_REMOVE))) { 530 DPRINTF("spurious CSC interrupt.\n"); 531 goto out; 532 } 533 534 ch->ch_attached = (type == EVENT_INSERT); 535 pe->__queued = 1; 536 pe->pe_type = type; 537 pe->pe_ch = ch; 538 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 539 wakeup(sc); 540 out: 541 splx(s); 542 } 543 544 /* 545 * interface for pcmcia driver. 546 */ 547 STATIC void * 548 hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 549 struct pcmcia_function *pf, 550 int ipl, int (*ih_func)(void *), void *ih_arg) 551 { 552 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 553 int channel = ch->ch_channel; 554 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 555 int s = splhigh(); 556 uint8_t r; 557 558 ch->ch_ih_card_func = ih_func; 559 ch->ch_ih_card_arg = ih_arg; 560 561 /* enable card interrupt */ 562 r = hd64461_reg_read_1(cscier); 563 if (channel == CHANNEL_0) { 564 /* set level mode */ 565 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 566 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 567 hd6446x_intr_priority(HD64461_INTC_PCC0, ipl); 568 } else { 569 /* READY-pin LOW to HIGH changes generates interrupt */ 570 r |= HD64461_PCC1CSCIER_P1RE; 571 hd6446x_intr_priority(HD64461_INTC_PCC1, ipl); 572 } 573 hd64461_reg_write_1(cscier, r); 574 575 splx(s); 576 577 return (void *)ih_func; 578 } 579 580 STATIC void 581 hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 582 { 583 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 584 int channel = ch->ch_channel; 585 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 586 int s = splhigh(); 587 uint8_t r; 588 589 /* disable card interrupt */ 590 r = hd64461_reg_read_1(cscier); 591 if (channel == CHANNEL_0) { 592 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 593 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 594 hd6446x_intr_priority(HD64461_INTC_PCC0, IPL_TTY); 595 } else { 596 r &= ~HD64461_PCC1CSCIER_P1RE; 597 hd6446x_intr_priority(HD64461_INTC_PCC1, IPL_TTY); 598 } 599 hd64461_reg_write_1(cscier, r); 600 601 ch->ch_ih_card_func = 0; 602 603 splx(s); 604 } 605 606 STATIC int 607 hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 608 struct pcmcia_mem_handle *pcmhp) 609 { 610 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 611 612 pcmhp->memt = ch->ch_memt; 613 pcmhp->addr = ch->ch_membase_addr; 614 pcmhp->memh = ch->ch_memh; 615 pcmhp->size = size; 616 pcmhp->realsize = size; 617 618 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 619 620 return (0); 621 } 622 623 STATIC void 624 hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 625 struct pcmcia_mem_handle *pcmhp) 626 { 627 /* nothing to do */ 628 } 629 630 STATIC int 631 hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 632 bus_addr_t card_addr, 633 bus_size_t size, struct pcmcia_mem_handle *pcmhp, 634 bus_size_t *offsetp, int *windowp) 635 { 636 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 637 struct hd64461pcmcia_window_cookie *cookie; 638 bus_addr_t ofs; 639 640 cookie = kmem_zalloc(sizeof(struct hd64461pcmcia_window_cookie), 641 KM_SLEEP); 642 KASSERT(cookie != NULL); 643 644 /* Address */ 645 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 646 cookie->wc_tag = ch->ch_memt; 647 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 648 size, &cookie->wc_handle) != 0) 649 goto bad; 650 651 *offsetp = card_addr; 652 cookie->wc_window = -1; 653 } else { 654 int window = card_addr / ch->ch_memsize; 655 KASSERT(window < MEMWIN_16M_MAX); 656 657 cookie->wc_tag = ch->ch_cmemt[window]; 658 ofs = card_addr - window * ch->ch_memsize; 659 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 660 &cookie->wc_handle) != 0) 661 goto bad; 662 663 /* XXX bogus. check window per common memory access. */ 664 hd64461pcmcia_memory_window_16(ch->ch_channel, window); 665 *offsetp = ofs + 0x01000000; /* skip attribute area */ 666 cookie->wc_window = window; 667 } 668 cookie->wc_size = size; 669 *windowp = (int)cookie; 670 671 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 672 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, 673 size); 674 675 return (0); 676 bad: 677 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 678 kmem_free(cookie, sizeof(*cookie)); 679 680 return (1); 681 } 682 683 STATIC void 684 hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 685 { 686 struct hd64461pcmcia_window_cookie *cookie = (void *)window; 687 688 if (cookie->wc_window != -1) 689 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 690 cookie->wc_size); 691 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 692 kmem_free(cookie, sizeof(*cookie)); 693 } 694 695 STATIC int 696 hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 697 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 698 { 699 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 700 701 if (ch->ch_channel == CHANNEL_1) 702 return (1); 703 704 if (start) { 705 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 706 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 707 return (1); 708 } 709 DPRINTF("map %#lx+%#lx\n", start, size); 710 } else { 711 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 712 ch->ch_iobase + ch->ch_iosize - 1, 713 size, align, 0, 0, &pcihp->addr, 714 &pcihp->ioh)) { 715 DPRINTF("couldn't allocate %#lx\n", size); 716 return (1); 717 } 718 pcihp->flags = PCMCIA_IO_ALLOCATED; 719 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 720 } 721 722 pcihp->iot = ch->ch_iot; 723 pcihp->size = size; 724 725 return (0); 726 } 727 728 STATIC int 729 hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 730 bus_addr_t offset, 731 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 732 { 733 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 734 #ifdef HD64461PCMCIA_DEBUG 735 static const char *width_names[] = { "auto", "io8", "io16" }; 736 #endif 737 if (ch->ch_channel == CHANNEL_1) 738 return (1); 739 740 hd64461_set_bus_width(CHANNEL_0, width); 741 742 /* fake. drivers init that to -1 and check if it was changed. */ 743 *windowp = 0; 744 745 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 746 width_names[width]); 747 748 return (0); 749 } 750 751 STATIC void 752 hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 753 struct pcmcia_io_handle *pcihp) 754 { 755 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 756 757 if (ch->ch_channel == CHANNEL_1) 758 return; 759 760 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 761 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 762 else 763 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 764 765 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 766 } 767 768 STATIC void 769 hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 770 { 771 772 /* nothing to do */ 773 } 774 775 STATIC void 776 hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 777 { 778 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 779 int channel = ch->ch_channel; 780 bus_addr_t isr, gcr; 781 uint8_t r; 782 int i; 783 784 DPRINTF("enable channel %d\n", channel); 785 isr = HD64461_PCCISR(channel); 786 gcr = HD64461_PCCGCR(channel); 787 788 hd64461pcmcia_power_off(channel); 789 hd64461pcmcia_power_on(channel); 790 791 /* assert reset, set card type to memory */ 792 r = hd64461_reg_read_1(gcr); 793 r |= HD64461_PCCGCR_PCCR; 794 r &= ~HD64461_PCC0GCR_P0PCCT; 795 hd64461_reg_write_1(gcr, r); 796 797 /* 798 * hold RESET at least 10us. 799 */ 800 DELAY_MS(20); 801 802 /* clear the reset flag */ 803 r &= ~HD64461_PCCGCR_PCCR; 804 hd64461_reg_write_1(gcr, r); 805 DELAY_MS(2000); 806 807 /* wait for the chip to finish initializing */ 808 for (i = 0; i < 10000; i++) { 809 if ((hd64461_reg_read_1(isr) & HD64461_PCCISR_READY)) 810 goto reset_ok; 811 DELAY_MS(500); 812 813 if ((i > 5000) && (i % 100 == 99)) 814 printf("."); 815 } 816 printf("reset failed.\n"); 817 hd64461pcmcia_power_off(channel); 818 return; 819 820 reset_ok: 821 /* set Continuous 16-MB Area Mode */ 822 ch->ch_memory_window_mode = MEMWIN_16M_MODE; 823 hd64461pcmcia_memory_window_mode(channel, ch->ch_memory_window_mode); 824 825 /* 826 * set Common memory area. 827 */ 828 hd64461pcmcia_memory_window_16(channel, MEMWIN_16M_COMMON_0); 829 830 DPRINTF("OK.\n"); 831 } 832 833 STATIC void 834 hd64461pcmcia_chip_socket_settype(pcmcia_chipset_handle_t pch, int type) 835 { 836 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 837 int channel = ch->ch_channel; 838 bus_addr_t gcr; 839 uint8_t r; 840 841 DPRINTF("settype channel %d\n", channel); 842 gcr = HD64461_PCCGCR(channel); 843 844 /* set the card type */ 845 r = hd64461_reg_read_1(gcr); 846 if (channel == CHANNEL_0) { 847 if (type == PCMCIA_IFTYPE_IO) 848 r |= HD64461_PCC0GCR_P0PCCT; 849 else 850 r &= ~HD64461_PCC0GCR_P0PCCT; 851 } else { 852 /* reserved bit must be 0 */ 853 r &= ~HD64461_PCC1GCR_RESERVED; 854 } 855 hd64461_reg_write_1(gcr, r); 856 857 DPRINTF("OK.\n"); 858 } 859 860 STATIC void 861 hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 862 { 863 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 864 int channel = ch->ch_channel; 865 866 /* dont' disable CSC interrupt */ 867 hd64461_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 868 hd64461_reg_write_1(HD64461_PCCCSCR(channel), 0); 869 870 /* power down the socket */ 871 hd64461pcmcia_power_off(channel); 872 } 873 874 /* 875 * Card detect 876 */ 877 STATIC void 878 hd64461pcmcia_power_off(enum controller_channel channel) 879 { 880 uint8_t r; 881 uint16_t r16; 882 bus_addr_t scr, gcr; 883 884 gcr = HD64461_PCCGCR(channel); 885 scr = HD64461_PCCSCR(channel); 886 887 /* DRV (external buffer) high level */ 888 r = hd64461_reg_read_1(gcr); 889 r &= ~HD64461_PCCGCR_DRVE; 890 hd64461_reg_write_1(gcr, r); 891 892 /* stop power */ 893 r = hd64461_reg_read_1(scr); 894 r |= HD64461_PCCSCR_VCC1; /* VCC1 high */ 895 hd64461_reg_write_1(scr, r); 896 r = hd64461_reg_read_1(gcr); 897 r |= HD64461_PCCGCR_VCC0; /* VCC0 high */ 898 hd64461_reg_write_1(gcr, r); 899 /* 900 * wait 300ms until power fails (Tpf). Then, wait 100ms since 901 * we are changing Vcc (Toff). 902 */ 903 DELAY_MS(300 + 100); 904 905 /* stop clock */ 906 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 907 r16 |= (channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 908 HD64461_SYSSTBCR_SPC1ST); 909 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 910 } 911 912 STATIC void 913 hd64461pcmcia_power_on(enum controller_channel channel) 914 { 915 uint8_t r; 916 uint16_t r16; 917 bus_addr_t gcr, isr; 918 919 isr = HD64461_PCCISR(channel); 920 gcr = HD64461_PCCGCR(channel); 921 (void)HD64461_PCCSCR(channel); 922 923 /* 924 * XXX to access attribute memory, this is required. 925 */ 926 if (channel == CHANNEL_0) { 927 /* GPIO Port A XXX Jonanada690 specific? */ 928 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 929 r16 &= ~0xf; 930 r16 |= 0x5; 931 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 932 } 933 934 if (channel == CHANNEL_1) { 935 /* GPIO Port C, Port D -> PCC1 pin 936 * I assume SYSCR[1:0] == 0 937 */ 938 hd64461_reg_write_2(HD64461_GPCCR_REG16, 0xa800); 939 hd64461_reg_write_2(HD64461_GPDCR_REG16, 0xaa0a); 940 } 941 942 /* supply clock */ 943 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 944 r16 &= ~(channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 945 HD64461_SYSSTBCR_SPC1ST); 946 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 947 DELAY_MS(200); 948 949 /* detect voltage and supply VCC */ 950 r = hd64461_reg_read_1(isr); 951 952 switch (r & (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2)) { 953 case (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2): /* 5 V */ 954 DPRINTF("5V card\n"); 955 hd64461pcmcia_power(channel, V_5, 1); 956 break; 957 case HD64461_PCCISR_VS2: /* 3.3 / 5 V */ 958 /* FALLTHROUGH */ 959 case 0: /* x.x / 3.3 / 5 V */ 960 DPRINTF("3.3V card\n"); 961 hd64461pcmcia_power(channel, V_3_3, 1); 962 break; 963 case HD64461_PCCISR_VS1: /* x.x V */ 964 /* FALLTHROUGH */ 965 DPRINTF("x.x V card\n"); 966 hd64461pcmcia_power(channel, V_X_X, 1); 967 return; 968 default: 969 printf("\nunknown Voltage. don't attach.\n"); 970 return; 971 } 972 973 /* 974 * wait 100ms until power raise (Tpr) and 20ms to become 975 * stable (Tsu(Vcc)). 976 * 977 * some machines require some more time to be settled 978 * (300ms is added here). 979 */ 980 DELAY_MS(100 + 20 + 300); 981 982 /* DRV (external buffer) low level */ 983 r = hd64461_reg_read_1(gcr); 984 r |= HD64461_PCCGCR_DRVE; 985 hd64461_reg_write_1(gcr, r); 986 987 /* clear interrupt */ 988 hd64461_reg_write_1(channel == CHANNEL_0 ? HD64461_PCC0CSCR_REG8 : 989 HD64461_PCC1CSCR_REG8, 0); 990 } 991 992 STATIC enum hd64461pcmcia_event_type 993 detect_card(enum controller_channel channel) 994 { 995 uint8_t r; 996 997 r = hd64461_reg_read_1(HD64461_PCCISR(channel)) & 998 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 999 1000 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 1001 DPRINTF("remove\n"); 1002 return EVENT_REMOVE; 1003 } 1004 if (r == 0) { 1005 DPRINTF("insert\n"); 1006 return EVENT_INSERT; 1007 } 1008 DPRINTF("transition\n"); 1009 1010 return EVENT_NONE; 1011 } 1012 1013 /* 1014 * Memory window access ops. 1015 */ 1016 STATIC void 1017 hd64461pcmcia_memory_window_mode(enum controller_channel channel, 1018 enum memory_window_mode mode) 1019 { 1020 bus_addr_t a = HD64461_PCCGCR(channel); 1021 uint8_t r = hd64461_reg_read_1(a); 1022 1023 r &= ~HD64461_PCCGCR_MMOD; 1024 r |= (mode == MEMWIN_16M_MODE) ? HD64461_PCCGCR_MMOD_16M : 1025 HD64461_PCCGCR_MMOD_32M; 1026 hd64461_reg_write_1(a, r); 1027 } 1028 1029 STATIC void 1030 hd64461pcmcia_memory_window_16(enum controller_channel channel, 1031 enum memory_window_16 window) 1032 { 1033 bus_addr_t a = HD64461_PCCGCR(channel); 1034 uint8_t r; 1035 1036 r = hd64461_reg_read_1(a); 1037 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1038 1039 switch (window) { 1040 case MEMWIN_16M_COMMON_0: 1041 break; 1042 case MEMWIN_16M_COMMON_1: 1043 r |= HD64461_PCCGCR_PA24; 1044 break; 1045 case MEMWIN_16M_COMMON_2: 1046 r |= HD64461_PCCGCR_PA25; 1047 break; 1048 case MEMWIN_16M_COMMON_3: 1049 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1050 break; 1051 } 1052 1053 hd64461_reg_write_1(a, r); 1054 } 1055 1056 #if unused 1057 STATIC void 1058 memory_window_32(enum controller_channel channel, enum memory_window_32 window) 1059 { 1060 bus_addr_t a = HD64461_PCCGCR(channel); 1061 uint8_t r; 1062 1063 r = hd64461_reg_read_1(a); 1064 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1065 1066 switch (window) { 1067 case MEMWIN_32M_ATTR: 1068 break; 1069 case MEMWIN_32M_COMMON_0: 1070 r |= HD64461_PCCGCR_PREG; 1071 break; 1072 case MEMWIN_32M_COMMON_1: 1073 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1074 break; 1075 } 1076 1077 hd64461_reg_write_1(a, r); 1078 } 1079 #endif 1080 1081 STATIC void 1082 hd64461_set_bus_width(enum controller_channel channel, int width) 1083 { 1084 unsigned int area, buswidth; 1085 uint16_t bcr2; 1086 1087 if (channel == CHANNEL_0) 1088 area = BCR2_AREA6_SHIFT; 1089 else 1090 area = BCR2_AREA5_SHIFT; 1091 1092 if (width == PCMCIA_WIDTH_IO8) 1093 buswidth = BCR2_AREA_WIDTH_8; 1094 else 1095 buswidth = BCR2_AREA_WIDTH_16; 1096 1097 bcr2 = _reg_read_2(SH3_BCR2); 1098 1099 bcr2 &= ~(BCR2_AREA_WIDTH_MASK << area); 1100 bcr2 |= buswidth << area; 1101 1102 _reg_write_2(SH3_BCR2, bcr2); 1103 } 1104 1105 STATIC void 1106 fixup_sh3_pcmcia_area6(bus_space_tag_t t) 1107 { 1108 struct hpcsh_bus_space *hbs = (void *)t; 1109 1110 hbs->hbs_r_1 = _sh3_pcmcia_bug_read_1; 1111 hbs->hbs_rm_1 = _sh3_pcmcia_bug_read_multi_1; 1112 hbs->hbs_rr_1 = _sh3_pcmcia_bug_read_region_1; 1113 hbs->hbs_w_1 = _sh3_pcmcia_bug_write_1; 1114 hbs->hbs_wm_1 = _sh3_pcmcia_bug_write_multi_1; 1115 hbs->hbs_wr_1 = _sh3_pcmcia_bug_write_region_1; 1116 hbs->hbs_sm_1 = _sh3_pcmcia_bug_set_multi_1; 1117 hbs->hbs_c_1 = _sh3_pcmcia_bug_copy_region_1; 1118 } 1119 1120 #ifdef HD64461PCMCIA_DEBUG 1121 STATIC void 1122 hd64461pcmcia_info(struct hd64461pcmcia_softc *sc) 1123 { 1124 uint8_t r8; 1125 1126 dbg_banner_function(); 1127 /* 1128 * PCC0 1129 */ 1130 printf("[PCC0 memory and I/O card (SH3 Area 6)]\n"); 1131 printf("PCC0 Interface Status Register\n"); 1132 r8 = hd64461_reg_read_1(HD64461_PCC0ISR_REG8); 1133 1134 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0ISR_##m, #m) 1135 _(P0READY);_(P0MWP);_(P0VS2);_(P0VS1);_(P0CD2);_(P0CD1); 1136 _(P0BVD2);_(P0BVD1); 1137 #undef _ 1138 printf("\n"); 1139 1140 printf("PCC0 General Control Register\n"); 1141 r8 = hd64461_reg_read_1(HD64461_PCC0GCR_REG8); 1142 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0GCR_##m, #m) 1143 _(P0DRVE);_(P0PCCR);_(P0PCCT);_(P0VCC0);_(P0MMOD); 1144 _(P0PA25);_(P0PA24);_(P0REG); 1145 #undef _ 1146 printf("\n"); 1147 1148 printf("PCC0 Card Status Change Register\n"); 1149 r8 = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 1150 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCR_##m, #m) 1151 _(P0SCDI);_(P0IREQ);_(P0SC);_(P0CDC);_(P0RC);_(P0BW);_(P0BD); 1152 #undef _ 1153 printf("\n"); 1154 1155 printf("PCC0 Card Status Change Interrupt Enable Register\n"); 1156 r8 = hd64461_reg_read_1(HD64461_PCC0CSCIER_REG8); 1157 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCIER_##m, #m) 1158 _(P0CRE);_(P0SCE);_(P0CDE);_(P0RE);_(P0BWE);_(P0BDE); 1159 #undef _ 1160 printf("\ninterrupt type: "); 1161 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 1162 case HD64461_PCC0CSCIER_P0IREQE_NONE: 1163 printf("none\n"); 1164 break; 1165 case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 1166 printf("level\n"); 1167 break; 1168 case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 1169 printf("falling edge\n"); 1170 break; 1171 case HD64461_PCC0CSCIER_P0IREQE_REDGE: 1172 printf("rising edge\n"); 1173 break; 1174 } 1175 1176 printf("PCC0 Software Control Register\n"); 1177 r8 = hd64461_reg_read_1(HD64461_PCC0SCR_REG8); 1178 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0SCR_##m, #m) 1179 _(P0VCC1);_(P0SWP); 1180 #undef _ 1181 printf("\n"); 1182 1183 /* 1184 * PCC1 1185 */ 1186 printf("[PCC1 memory card only (SH3 Area 5)]\n"); 1187 printf("PCC1 Interface Status Register\n"); 1188 r8 = hd64461_reg_read_1(HD64461_PCC1ISR_REG8); 1189 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1ISR_##m, #m) 1190 _(P1READY);_(P1MWP);_(P1VS2);_(P1VS1);_(P1CD2);_(P1CD1); 1191 _(P1BVD2);_(P1BVD1); 1192 #undef _ 1193 printf("\n"); 1194 1195 printf("PCC1 General Contorol Register\n"); 1196 r8 = hd64461_reg_read_1(HD64461_PCC1GCR_REG8); 1197 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1GCR_##m, #m) 1198 _(P1DRVE);_(P1PCCR);_(P1VCC0);_(P1MMOD);_(P1PA25);_(P1PA24);_(P1REG); 1199 #undef _ 1200 printf("\n"); 1201 1202 printf("PCC1 Card Status Change Register\n"); 1203 r8 = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 1204 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCR_##m, #m) 1205 _(P1SCDI);_(P1CDC);_(P1RC);_(P1BW);_(P1BD); 1206 #undef _ 1207 printf("\n"); 1208 1209 printf("PCC1 Card Status Change Interrupt Enable Register\n"); 1210 r8 = hd64461_reg_read_1(HD64461_PCC1CSCIER_REG8); 1211 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCIER_##m, #m) 1212 _(P1CRE);_(P1CDE);_(P1RE);_(P1BWE);_(P1BDE); 1213 #undef _ 1214 printf("\n"); 1215 1216 printf("PCC1 Software Control Register\n"); 1217 r8 = hd64461_reg_read_1(HD64461_PCC1SCR_REG8); 1218 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1SCR_##m, #m) 1219 _(P1VCC1);_(P1SWP); 1220 #undef _ 1221 printf("\n"); 1222 1223 /* 1224 * General Control 1225 */ 1226 printf("[General Control]\n"); 1227 printf("PCC0 Output pins Control Register\n"); 1228 r8 = hd64461_reg_read_1(HD64461_PCCP0OCR_REG8); 1229 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP0OCR_##m, #m) 1230 _(P0DEPLUP);_(P0AEPLUP); 1231 #undef _ 1232 printf("\n"); 1233 1234 printf("PCC1 Output pins Control Register\n"); 1235 r8 = hd64461_reg_read_1(HD64461_PCCP1OCR_REG8); 1236 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP1OCR_##m, #m) 1237 _(P1RST8MA);_(P1RST4MA);_(P1RAS8MA);_(P1RAS4MA); 1238 #undef _ 1239 printf("\n"); 1240 1241 printf("PC Card General Control Register\n"); 1242 r8 = hd64461_reg_read_1(HD64461_PCCPGCR_REG8); 1243 #define _(m) dbg_bitmask_print(r8, HD64461_PCCPGCR_##m, #m) 1244 _(PSSDIR);_(PSSRDWR); 1245 #undef _ 1246 printf("\n"); 1247 1248 dbg_banner_line(); 1249 } 1250 #endif /* HD64461PCMCIA_DEBUG */ 1251
Indexes created Wed Oct 01 19:09:53 GMT 2025