| /src/sys/arch/arm/xscale/ |
| becc_intr.h | 77 uint32_t oldirqstate, hwpend; local in function:becc_splx
87 hwpend = becc_ipending & ~new;
88 if (hwpend != 0) {
90 intr_enabled |= hwpend;
|
| i80321_intr.h | 70 int oldirqstate, hwpend; local in function:i80321_splx
77 hwpend = (i80321_ipending & ICU_INT_HWMASK) & ~i80321_imask[new];
78 if (hwpend != 0) {
80 intr_enabled |= hwpend;
83 if (__predict_false(hwpend & INT_HPIMASK))
|
| ixp425_intr.h | 67 int oldirqstate, hwpend; local in function:ixp425_splx
74 hwpend = (ixp425_ipending & IXP425_INT_HWMASK) & ~ixp425_imask[ipl];
75 if (hwpend != 0) {
77 intr_enabled |= hwpend;
|
| becc_icu.c | 339 uint32_t oldirqstate, irq, ibit, hwpend; local in function:becc_intr_dispatch
344 hwpend = becc_icsr_read();
350 intr_enabled &= ~hwpend;
353 while (hwpend != 0) {
354 irq = ffs(hwpend) - 1;
357 hwpend &= ~ibit;
|
| i80321_icu.c | 355 int oldirqstate, irq, ibit, hwpend; local in function:i80321_intr_dispatch
363 hwpend = i80321_iintsrc_read();
369 intr_enabled &= ~hwpend;
376 while (hwpend != 0) {
379 if (__predict_false(hwpend & INT_HPIMASK))
383 irq = ffs(hwpend) - 1;
386 hwpend &= ~ibit;
451 hwpend |= ((i80321_ipending & ICU_INT_HWMASK) & ~imask);
|
| ixp425_intr.c | 389 int oldirqstate, irq, ibit, hwpend; local in function:ixp425_intr_dispatch
394 hwpend = ixp425_irq_read();
400 intr_enabled &= ~hwpend;
403 while (hwpend != 0) {
404 irq = ffs(hwpend) - 1;
407 hwpend &= ~ibit;
453 hwpend |= ((ixp425_ipending & IXP425_INT_HWMASK) & ~imask);
|
| /src/sys/arch/evbarm/ifpga/ |
| ifpga_intr.h | 70 int oldirqstate, hwpend; local in function:ifpga_splx
77 hwpend = (ifpga_ipending & IFPGA_INTR_HWMASK) & ~new;
78 if (hwpend != 0) {
79 intr_enabled |= hwpend;
|
| ifpga_intr.c | 301 int oldirqstate, pcpl, irq, ibit, hwpend; local in function:ifpga_intr_dispatch
306 hwpend = ifpga_iintsrc_read();
312 intr_enabled &= ~hwpend;
316 while ((ifpga_iintsrc_read() & hwpend) != 0)
319 while (hwpend != 0) {
320 irq = ffs(hwpend) - 1;
323 hwpend &= ~ibit;
348 hwpend |= (ifpga_ipending & IFPGA_INTR_HWMASK) & ~pcpl;
|
| /src/sys/arch/arm/footbridge/ |
| footbridge_irqhandler.c | 284 int oldirqstate, irq, ibit, hwpend; local in function:footbridge_intr_dispatch
289 hwpend = footbridge_intstatus();
295 intr_enabled &= ~hwpend;
298 while (hwpend != 0) {
300 irq = ffs(hwpend) - 1;
303 hwpend &= ~ibit;
336 hwpend |= (footbridge_ipending & ICU_INT_HWMASK) & ~imask;
|
| footbridge_intr.h | 103 int oldirqstate, hwpend; local in function:footbridge_splx
110 hwpend = footbridge_ipending & ICU_INT_HWMASK & ~footbridge_imask[ipl];
111 if (hwpend != 0) {
113 intr_enabled |= hwpend;
|
| /src/sys/arch/arm/ixp12x0/ |
| ixp12x0_intr.c | 383 uint32_t hwpend; local in function:ixp12x0_intr_dispatch
389 hwpend = ixp12x0_irq_read();
393 ixp12x0_set_intrmask(imask[ppl] | hwpend, pci_imask[ppl] | pci_hwpend);
395 hwpend &= ~imask[ppl];
398 while (hwpend) {
399 irq = ffs(hwpend) - 1;
410 hwpend &= ~ibit;
|
| /src/sys/arch/evbarm/iq80310/ |
| iq80310_intr.c | 419 int oldirqstate, pcpl, irq, ibit, hwpend, rv; local in function:iq80310_intr_dispatch
432 for (hwpend = iq80310_intstat_read(); hwpend != 0;) {
433 irq = ffs(hwpend) - 1;
440 hwpend &= ~ibit;
|
| /src/sys/arch/mips/cavium/ |
| octeon_intr.c | 487 uint64_t hwpend[2] = { 0, 0 }; local in function:octeon_iointr
492 hwpend[0] = mips3_ld(cpu->cpu_ip4_sum0)
494 hwpend[1] = sum1 & cpu->cpu_ip4_enable[1];
496 hwpend[0] = mips3_ld(cpu->cpu_ip3_sum0)
498 hwpend[1] = sum1 & cpu->cpu_ip3_enable[1];
500 hwpend[0] = mips3_ld(cpu->cpu_ip2_sum0)
502 hwpend[1] = sum1 & cpu->cpu_ip2_enable[1];
507 while (hwpend[bank] != 0) {
508 const int bit = ffs64(hwpend[bank]) - 1;
510 hwpend[bank] &= ~__BIT(bit)
[all...] |
