| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_r200.c | 162 u32 idx_value; local in function:r200_packet0_check
166 idx_value = radeon_get_ib_value(p, idx);
194 track->zb.offset = idx_value;
196 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
207 track->cb[0].offset = idx_value;
209 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
231 tmp = idx_value & ~(0x7 << 2);
235 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
278 track->textures[i].cube_info[face - 1].offset = idx_value;
279 ib[idx] = idx_value + ((u32)reloc->gpu_offset)
[all...] |
| radeon_r300.c | 670 u32 idx_value; local in function:r300_packet0_check
674 idx_value = radeon_get_ib_value(p, idx);
706 track->cb[i].offset = idx_value;
708 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
719 track->zb.offset = idx_value;
721 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
749 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */
750 ((idx_value & ~31) + (u32)reloc->gpu_offset);
759 tmp = idx_value + ((u32)reloc->gpu_offset);
769 track->vap_vf_cntl = idx_value;
[all...] |
| radeon_evergreen_cs.c | 1811 u32 idx_value; local in function:evergreen_packet3_check
1816 idx_value = radeon_get_ib_value(p, idx);
1849 (idx_value & 0xfffffff0) +
1895 idx_value +
1930 idx_value +
2041 if (idx_value != 1) {
2074 if (idx_value + size > track->indirect_draw_buffer_size) {
2076 idx_value, size, track->indirect_draw_buffer_size);
2108 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff);
2121 if (idx_value & 0x10)
3381 u32 idx_value = ib[idx]; local in function:evergreen_vm_packet3_check
[all...] |
| radeon_r600_cs.c | 1639 u32 idx_value; local in function:r600_packet3_check
1644 idx_value = radeon_get_ib_value(p, idx);
1677 (idx_value & 0xfffffff0) +
1718 idx_value +
1760 if (idx_value & 0x10) {
1775 } else if (idx_value & 0x100) {
1912 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
1928 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
1948 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
2028 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET
2385 u32 idx, idx_value; local in function:r600_dma_cs_parse
[all...] |
| radeon_r100.c | 1329 u32 idx_value; local in function:r100_packet3_load_vbpntr
1349 idx_value = radeon_get_ib_value(p, idx);
1352 track->arrays[i + 0].esize = idx_value >> 8;
1364 track->arrays[i + 1].esize = idx_value >> 24;
1375 idx_value = radeon_get_ib_value(p, idx);
1378 track->arrays[i + 0].esize = idx_value >> 8;
1581 u32 idx_value; local in function:r100_packet0_check
1586 idx_value = radeon_get_ib_value(p, idx);
1615 track->zb.offset = idx_value;
1617 ib[idx] = idx_value + ((u32)reloc->gpu_offset)
[all...] |
| radeon_si.c | 4491 u32 idx_value = ib[idx]; local in function:si_vm_packet3_cp_dma_check
4495 start_reg = idx_value << 2;
4542 u32 idx_value = ib[idx]; local in function:si_vm_packet3_gfx_check
4593 if ((idx_value & 0xf00) == 0) {
4600 if ((idx_value & 0xf00) == 0) {
4602 if (idx_value & 0x10000) {
4615 if (idx_value & 0x100) {
4622 if (idx_value & 0x2) {
4629 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
4660 u32 idx_value = ib[idx] local in function:si_vm_packet3_compute_check
[all...] |
