1 /* $NetBSD: intel_vdsc.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $ */ 2 3 // SPDX-License-Identifier: MIT 4 /* 5 * Copyright 2018 Intel Corporation 6 * 7 * Author: Gaurav K Singh <gaurav.k.singh (at) intel.com> 8 * Manasi Navare <manasi.d.navare (at) intel.com> 9 */ 10 11 #include <sys/cdefs.h> 12 __KERNEL_RCSID(0, "$NetBSD: intel_vdsc.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $"); 13 14 #include <drm/i915_drm.h> 15 16 #include "i915_drv.h" 17 #include "intel_display_types.h" 18 #include "intel_dsi.h" 19 #include "intel_vdsc.h" 20 21 enum ROW_INDEX_BPP { 22 ROW_INDEX_6BPP = 0, 23 ROW_INDEX_8BPP, 24 ROW_INDEX_10BPP, 25 ROW_INDEX_12BPP, 26 ROW_INDEX_15BPP, 27 MAX_ROW_INDEX 28 }; 29 30 enum COLUMN_INDEX_BPC { 31 COLUMN_INDEX_8BPC = 0, 32 COLUMN_INDEX_10BPC, 33 COLUMN_INDEX_12BPC, 34 COLUMN_INDEX_14BPC, 35 COLUMN_INDEX_16BPC, 36 MAX_COLUMN_INDEX 37 }; 38 39 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */ 40 static const u16 rc_buf_thresh[] = { 41 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, 42 7744, 7872, 8000, 8064 43 }; 44 45 struct rc_parameters { 46 u16 initial_xmit_delay; 47 u8 first_line_bpg_offset; 48 u16 initial_offset; 49 u8 flatness_min_qp; 50 u8 flatness_max_qp; 51 u8 rc_quant_incr_limit0; 52 u8 rc_quant_incr_limit1; 53 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; 54 }; 55 56 /* 57 * Selected Rate Control Related Parameter Recommended Values 58 * from DSC_v1.11 spec & C Model release: DSC_model_20161212 59 */ 60 static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { 61 { 62 /* 6BPP/8BPC */ 63 { 768, 15, 6144, 3, 13, 11, 11, { 64 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 }, 65 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 }, 66 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 }, 67 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 } 68 } 69 }, 70 /* 6BPP/10BPC */ 71 { 768, 15, 6144, 7, 17, 15, 15, { 72 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 }, 73 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 }, 74 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 }, 75 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 }, 76 { 17, 18, -12 } 77 } 78 }, 79 /* 6BPP/12BPC */ 80 { 768, 15, 6144, 11, 21, 19, 19, { 81 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 }, 82 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 }, 83 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 }, 84 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 }, 85 { 21, 22, -12 } 86 } 87 }, 88 /* 6BPP/14BPC */ 89 { 768, 15, 6144, 15, 25, 23, 27, { 90 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 }, 91 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 }, 92 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 }, 93 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 }, 94 { 25, 26, -12 } 95 } 96 }, 97 /* 6BPP/16BPC */ 98 { 768, 15, 6144, 19, 29, 27, 27, { 99 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 }, 100 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 }, 101 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 }, 102 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 }, 103 { 29, 30, -12 } 104 } 105 }, 106 }, 107 { 108 /* 8BPP/8BPC */ 109 { 512, 12, 6144, 3, 12, 11, 11, { 110 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, 111 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 112 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, 113 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } 114 } 115 }, 116 /* 8BPP/10BPC */ 117 { 512, 12, 6144, 7, 16, 15, 15, { 118 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, 119 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 120 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, 121 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } 122 } 123 }, 124 /* 8BPP/12BPC */ 125 { 512, 12, 6144, 11, 20, 19, 19, { 126 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, 127 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 128 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, 129 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, 130 { 21, 23, -12 } 131 } 132 }, 133 /* 8BPP/14BPC */ 134 { 512, 12, 6144, 15, 24, 23, 23, { 135 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, 136 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 137 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 }, 138 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, 139 { 24, 25, -12 } 140 } 141 }, 142 /* 8BPP/16BPC */ 143 { 512, 12, 6144, 19, 28, 27, 27, { 144 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 }, 145 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 146 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 }, 147 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 }, 148 { 28, 29, -12 } 149 } 150 }, 151 }, 152 { 153 /* 10BPP/8BPC */ 154 { 410, 15, 5632, 3, 12, 11, 11, { 155 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 }, 156 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 157 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 }, 158 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 } 159 } 160 }, 161 /* 10BPP/10BPC */ 162 { 410, 15, 5632, 7, 16, 15, 15, { 163 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 }, 164 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 165 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 }, 166 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 } 167 } 168 }, 169 /* 10BPP/12BPC */ 170 { 410, 15, 5632, 11, 20, 19, 19, { 171 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 }, 172 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 173 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 }, 174 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 }, 175 { 19, 20, -12 } 176 } 177 }, 178 /* 10BPP/14BPC */ 179 { 410, 15, 5632, 15, 24, 23, 23, { 180 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 }, 181 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 182 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 }, 183 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 }, 184 { 23, 24, -12 } 185 } 186 }, 187 /* 10BPP/16BPC */ 188 { 410, 15, 5632, 19, 28, 27, 27, { 189 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 }, 190 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 191 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 }, 192 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 }, 193 { 27, 28, -12 } 194 } 195 }, 196 }, 197 { 198 /* 12BPP/8BPC */ 199 { 341, 15, 2048, 3, 12, 11, 11, { 200 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, 201 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 202 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, 203 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } 204 } 205 }, 206 /* 12BPP/10BPC */ 207 { 341, 15, 2048, 7, 16, 15, 15, { 208 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, 209 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 210 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, 211 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } 212 } 213 }, 214 /* 12BPP/12BPC */ 215 { 341, 15, 2048, 11, 20, 19, 19, { 216 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, 217 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 218 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, 219 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, 220 { 21, 23, -12 } 221 } 222 }, 223 /* 12BPP/14BPC */ 224 { 341, 15, 2048, 15, 24, 23, 23, { 225 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 }, 226 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 227 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 }, 228 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 }, 229 { 22, 23, -12 } 230 } 231 }, 232 /* 12BPP/16BPC */ 233 { 341, 15, 2048, 19, 28, 27, 27, { 234 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 }, 235 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 236 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 }, 237 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 }, 238 { 26, 27, -12 } 239 } 240 }, 241 }, 242 { 243 /* 15BPP/8BPC */ 244 { 273, 15, 2048, 3, 12, 11, 11, { 245 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 }, 246 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 }, 247 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 }, 248 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 } 249 } 250 }, 251 /* 15BPP/10BPC */ 252 { 273, 15, 2048, 7, 16, 15, 15, { 253 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 }, 254 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 }, 255 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 }, 256 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 } 257 } 258 }, 259 /* 15BPP/12BPC */ 260 { 273, 15, 2048, 11, 20, 19, 19, { 261 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 }, 262 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 }, 263 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 }, 264 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 }, 265 { 16, 17, -12 } 266 } 267 }, 268 /* 15BPP/14BPC */ 269 { 273, 15, 2048, 15, 24, 23, 23, { 270 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 }, 271 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 }, 272 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 }, 273 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 }, 274 { 20, 21, -12 } 275 } 276 }, 277 /* 15BPP/16BPC */ 278 { 273, 15, 2048, 19, 28, 27, 27, { 279 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 }, 280 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 }, 281 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 }, 282 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 }, 283 { 24, 25, -12 } 284 } 285 } 286 } 287 288 }; 289 290 static int get_row_index_for_rc_params(u16 compressed_bpp) 291 { 292 switch (compressed_bpp) { 293 case 6: 294 return ROW_INDEX_6BPP; 295 case 8: 296 return ROW_INDEX_8BPP; 297 case 10: 298 return ROW_INDEX_10BPP; 299 case 12: 300 return ROW_INDEX_12BPP; 301 case 15: 302 return ROW_INDEX_15BPP; 303 default: 304 return -EINVAL; 305 } 306 } 307 308 static int get_column_index_for_rc_params(u8 bits_per_component) 309 { 310 switch (bits_per_component) { 311 case 8: 312 return COLUMN_INDEX_8BPC; 313 case 10: 314 return COLUMN_INDEX_10BPC; 315 case 12: 316 return COLUMN_INDEX_12BPC; 317 case 14: 318 return COLUMN_INDEX_14BPC; 319 case 16: 320 return COLUMN_INDEX_16BPC; 321 default: 322 return -EINVAL; 323 } 324 } 325 326 static const struct rc_parameters *get_rc_params(u16 compressed_bpp, 327 u8 bits_per_component) 328 { 329 int row_index, column_index; 330 331 row_index = get_row_index_for_rc_params(compressed_bpp); 332 if (row_index < 0) 333 return NULL; 334 335 column_index = get_column_index_for_rc_params(bits_per_component); 336 if (column_index < 0) 337 return NULL; 338 339 return &rc_parameters[row_index][column_index]; 340 } 341 342 bool intel_dsc_source_support(struct intel_encoder *encoder, 343 const struct intel_crtc_state *crtc_state) 344 { 345 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 346 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 347 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 348 enum pipe pipe = crtc->pipe; 349 350 if (!INTEL_INFO(i915)->display.has_dsc) 351 return false; 352 353 /* On TGL, DSC is supported on all Pipes */ 354 if (INTEL_GEN(i915) >= 12) 355 return true; 356 357 if (INTEL_GEN(i915) >= 10 && 358 (pipe != PIPE_A || 359 (cpu_transcoder == TRANSCODER_EDP || 360 cpu_transcoder == TRANSCODER_DSI_0 || 361 cpu_transcoder == TRANSCODER_DSI_1))) 362 return true; 363 364 return false; 365 } 366 367 static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state) 368 { 369 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 370 const struct drm_i915_private *i915 = to_i915(crtc->base.dev); 371 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 372 373 if (INTEL_GEN(i915) >= 12) 374 return true; 375 376 if (cpu_transcoder == TRANSCODER_EDP || 377 cpu_transcoder == TRANSCODER_DSI_0 || 378 cpu_transcoder == TRANSCODER_DSI_1) 379 return false; 380 381 /* There's no pipe A DSC engine on ICL */ 382 WARN_ON(crtc->pipe == PIPE_A); 383 384 return true; 385 } 386 387 int intel_dsc_compute_params(struct intel_encoder *encoder, 388 struct intel_crtc_state *pipe_config) 389 { 390 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; 391 u16 compressed_bpp = pipe_config->dsc.compressed_bpp; 392 const struct rc_parameters *rc_params; 393 u8 i = 0; 394 395 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; 396 vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay; 397 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, 398 pipe_config->dsc.slice_count); 399 400 /* Gen 11 does not support YCbCr */ 401 vdsc_cfg->simple_422 = false; 402 /* Gen 11 does not support VBR */ 403 vdsc_cfg->vbr_enable = false; 404 405 /* Gen 11 only supports integral values of bpp */ 406 vdsc_cfg->bits_per_pixel = compressed_bpp << 4; 407 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; 408 409 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { 410 /* 411 * six 0s are appended to the lsb of each threshold value 412 * internally in h/w. 413 * Only 8 bits are allowed for programming RcBufThreshold 414 */ 415 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; 416 } 417 418 /* 419 * For 6bpp, RC Buffer threshold 12 and 13 need a different value 420 * as per C Model 421 */ 422 if (compressed_bpp == 6) { 423 vdsc_cfg->rc_buf_thresh[12] = 0x7C; 424 vdsc_cfg->rc_buf_thresh[13] = 0x7D; 425 } 426 427 rc_params = get_rc_params(compressed_bpp, vdsc_cfg->bits_per_component); 428 if (!rc_params) 429 return -EINVAL; 430 431 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset; 432 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay; 433 vdsc_cfg->initial_offset = rc_params->initial_offset; 434 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp; 435 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp; 436 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0; 437 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1; 438 439 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 440 vdsc_cfg->rc_range_params[i].range_min_qp = 441 rc_params->rc_range_params[i].range_min_qp; 442 vdsc_cfg->rc_range_params[i].range_max_qp = 443 rc_params->rc_range_params[i].range_max_qp; 444 /* 445 * Range BPG Offset uses 2's complement and is only a 6 bits. So 446 * mask it to get only 6 bits. 447 */ 448 vdsc_cfg->rc_range_params[i].range_bpg_offset = 449 rc_params->rc_range_params[i].range_bpg_offset & 450 DSC_RANGE_BPG_OFFSET_MASK; 451 } 452 453 /* 454 * BitsPerComponent value determines mux_word_size: 455 * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits 456 * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to 457 * 48 bits 458 */ 459 if (vdsc_cfg->bits_per_component == 8 || 460 vdsc_cfg->bits_per_component == 10) 461 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; 462 else if (vdsc_cfg->bits_per_component == 12) 463 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; 464 465 /* RC_MODEL_SIZE is a constant across all configurations */ 466 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 467 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ 468 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / 469 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); 470 471 return 0; 472 } 473 474 enum intel_display_power_domain 475 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state) 476 { 477 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 478 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 479 enum pipe pipe = crtc->pipe; 480 481 /* 482 * VDSC/joining uses a separate power well, PW2, and requires 483 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases: 484 * 485 * - ICL eDP/DSI transcoder 486 * - TGL pipe A 487 * 488 * For any other pipe, VDSC/joining uses the power well associated with 489 * the pipe in use. Hence another reference on the pipe power domain 490 * will suffice. (Except no VDSC/joining on ICL pipe A.) 491 */ 492 if (INTEL_GEN(i915) >= 12 && pipe == PIPE_A) 493 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 494 else if (is_pipe_dsc(crtc_state)) 495 return POWER_DOMAIN_PIPE(pipe); 496 else 497 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 498 } 499 500 static void intel_dsc_pps_configure(struct intel_encoder *encoder, 501 const struct intel_crtc_state *crtc_state) 502 { 503 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 504 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 505 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 506 enum pipe pipe = crtc->pipe; 507 u32 pps_val = 0; 508 u32 rc_buf_thresh_dword[4]; 509 u32 rc_range_params_dword[8]; 510 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1; 511 int i = 0; 512 513 /* Populate PICTURE_PARAMETER_SET_0 registers */ 514 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << 515 DSC_VER_MIN_SHIFT | 516 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | 517 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; 518 if (vdsc_cfg->block_pred_enable) 519 pps_val |= DSC_BLOCK_PREDICTION; 520 if (vdsc_cfg->convert_rgb) 521 pps_val |= DSC_COLOR_SPACE_CONVERSION; 522 if (vdsc_cfg->simple_422) 523 pps_val |= DSC_422_ENABLE; 524 if (vdsc_cfg->vbr_enable) 525 pps_val |= DSC_VBR_ENABLE; 526 DRM_INFO("PPS0 = 0x%08x\n", pps_val); 527 if (!is_pipe_dsc(crtc_state)) { 528 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val); 529 /* 530 * If 2 VDSC instances are needed, configure PPS for second 531 * VDSC 532 */ 533 if (crtc_state->dsc.dsc_split) 534 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val); 535 } else { 536 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val); 537 if (crtc_state->dsc.dsc_split) 538 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), 539 pps_val); 540 } 541 542 /* Populate PICTURE_PARAMETER_SET_1 registers */ 543 pps_val = 0; 544 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); 545 DRM_INFO("PPS1 = 0x%08x\n", pps_val); 546 if (!is_pipe_dsc(crtc_state)) { 547 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val); 548 /* 549 * If 2 VDSC instances are needed, configure PPS for second 550 * VDSC 551 */ 552 if (crtc_state->dsc.dsc_split) 553 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val); 554 } else { 555 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val); 556 if (crtc_state->dsc.dsc_split) 557 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), 558 pps_val); 559 } 560 561 /* Populate PICTURE_PARAMETER_SET_2 registers */ 562 pps_val = 0; 563 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | 564 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); 565 DRM_INFO("PPS2 = 0x%08x\n", pps_val); 566 if (!is_pipe_dsc(crtc_state)) { 567 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val); 568 /* 569 * If 2 VDSC instances are needed, configure PPS for second 570 * VDSC 571 */ 572 if (crtc_state->dsc.dsc_split) 573 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val); 574 } else { 575 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val); 576 if (crtc_state->dsc.dsc_split) 577 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), 578 pps_val); 579 } 580 581 /* Populate PICTURE_PARAMETER_SET_3 registers */ 582 pps_val = 0; 583 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | 584 DSC_SLICE_WIDTH(vdsc_cfg->slice_width); 585 DRM_INFO("PPS3 = 0x%08x\n", pps_val); 586 if (!is_pipe_dsc(crtc_state)) { 587 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val); 588 /* 589 * If 2 VDSC instances are needed, configure PPS for second 590 * VDSC 591 */ 592 if (crtc_state->dsc.dsc_split) 593 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val); 594 } else { 595 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val); 596 if (crtc_state->dsc.dsc_split) 597 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), 598 pps_val); 599 } 600 601 /* Populate PICTURE_PARAMETER_SET_4 registers */ 602 pps_val = 0; 603 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | 604 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); 605 DRM_INFO("PPS4 = 0x%08x\n", pps_val); 606 if (!is_pipe_dsc(crtc_state)) { 607 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val); 608 /* 609 * If 2 VDSC instances are needed, configure PPS for second 610 * VDSC 611 */ 612 if (crtc_state->dsc.dsc_split) 613 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val); 614 } else { 615 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val); 616 if (crtc_state->dsc.dsc_split) 617 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe), 618 pps_val); 619 } 620 621 /* Populate PICTURE_PARAMETER_SET_5 registers */ 622 pps_val = 0; 623 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | 624 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); 625 DRM_INFO("PPS5 = 0x%08x\n", pps_val); 626 if (!is_pipe_dsc(crtc_state)) { 627 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val); 628 /* 629 * If 2 VDSC instances are needed, configure PPS for second 630 * VDSC 631 */ 632 if (crtc_state->dsc.dsc_split) 633 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val); 634 } else { 635 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val); 636 if (crtc_state->dsc.dsc_split) 637 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe), 638 pps_val); 639 } 640 641 /* Populate PICTURE_PARAMETER_SET_6 registers */ 642 pps_val = 0; 643 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | 644 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | 645 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | 646 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); 647 DRM_INFO("PPS6 = 0x%08x\n", pps_val); 648 if (!is_pipe_dsc(crtc_state)) { 649 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val); 650 /* 651 * If 2 VDSC instances are needed, configure PPS for second 652 * VDSC 653 */ 654 if (crtc_state->dsc.dsc_split) 655 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val); 656 } else { 657 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val); 658 if (crtc_state->dsc.dsc_split) 659 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe), 660 pps_val); 661 } 662 663 /* Populate PICTURE_PARAMETER_SET_7 registers */ 664 pps_val = 0; 665 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | 666 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); 667 DRM_INFO("PPS7 = 0x%08x\n", pps_val); 668 if (!is_pipe_dsc(crtc_state)) { 669 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val); 670 /* 671 * If 2 VDSC instances are needed, configure PPS for second 672 * VDSC 673 */ 674 if (crtc_state->dsc.dsc_split) 675 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val); 676 } else { 677 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val); 678 if (crtc_state->dsc.dsc_split) 679 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe), 680 pps_val); 681 } 682 683 /* Populate PICTURE_PARAMETER_SET_8 registers */ 684 pps_val = 0; 685 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | 686 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); 687 DRM_INFO("PPS8 = 0x%08x\n", pps_val); 688 if (!is_pipe_dsc(crtc_state)) { 689 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val); 690 /* 691 * If 2 VDSC instances are needed, configure PPS for second 692 * VDSC 693 */ 694 if (crtc_state->dsc.dsc_split) 695 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val); 696 } else { 697 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val); 698 if (crtc_state->dsc.dsc_split) 699 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe), 700 pps_val); 701 } 702 703 /* Populate PICTURE_PARAMETER_SET_9 registers */ 704 pps_val = 0; 705 pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) | 706 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); 707 DRM_INFO("PPS9 = 0x%08x\n", pps_val); 708 if (!is_pipe_dsc(crtc_state)) { 709 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val); 710 /* 711 * If 2 VDSC instances are needed, configure PPS for second 712 * VDSC 713 */ 714 if (crtc_state->dsc.dsc_split) 715 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val); 716 } else { 717 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val); 718 if (crtc_state->dsc.dsc_split) 719 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe), 720 pps_val); 721 } 722 723 /* Populate PICTURE_PARAMETER_SET_10 registers */ 724 pps_val = 0; 725 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | 726 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | 727 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | 728 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); 729 DRM_INFO("PPS10 = 0x%08x\n", pps_val); 730 if (!is_pipe_dsc(crtc_state)) { 731 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val); 732 /* 733 * If 2 VDSC instances are needed, configure PPS for second 734 * VDSC 735 */ 736 if (crtc_state->dsc.dsc_split) 737 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val); 738 } else { 739 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val); 740 if (crtc_state->dsc.dsc_split) 741 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe), 742 pps_val); 743 } 744 745 /* Populate Picture parameter set 16 */ 746 pps_val = 0; 747 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | 748 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / 749 vdsc_cfg->slice_width) | 750 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / 751 vdsc_cfg->slice_height); 752 DRM_INFO("PPS16 = 0x%08x\n", pps_val); 753 if (!is_pipe_dsc(crtc_state)) { 754 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val); 755 /* 756 * If 2 VDSC instances are needed, configure PPS for second 757 * VDSC 758 */ 759 if (crtc_state->dsc.dsc_split) 760 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val); 761 } else { 762 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val); 763 if (crtc_state->dsc.dsc_split) 764 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe), 765 pps_val); 766 } 767 768 /* Populate the RC_BUF_THRESH registers */ 769 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); 770 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { 771 rc_buf_thresh_dword[i / 4] |= 772 (u32)(vdsc_cfg->rc_buf_thresh[i] << 773 BITS_PER_BYTE * (i % 4)); 774 DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i, 775 rc_buf_thresh_dword[i / 4]); 776 } 777 if (!is_pipe_dsc(crtc_state)) { 778 I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]); 779 I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]); 780 I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]); 781 I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]); 782 if (crtc_state->dsc.dsc_split) { 783 I915_WRITE(DSCC_RC_BUF_THRESH_0, 784 rc_buf_thresh_dword[0]); 785 I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW, 786 rc_buf_thresh_dword[1]); 787 I915_WRITE(DSCC_RC_BUF_THRESH_1, 788 rc_buf_thresh_dword[2]); 789 I915_WRITE(DSCC_RC_BUF_THRESH_1_UDW, 790 rc_buf_thresh_dword[3]); 791 } 792 } else { 793 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0(pipe), 794 rc_buf_thresh_dword[0]); 795 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), 796 rc_buf_thresh_dword[1]); 797 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1(pipe), 798 rc_buf_thresh_dword[2]); 799 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), 800 rc_buf_thresh_dword[3]); 801 if (crtc_state->dsc.dsc_split) { 802 I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe), 803 rc_buf_thresh_dword[0]); 804 I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), 805 rc_buf_thresh_dword[1]); 806 I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1(pipe), 807 rc_buf_thresh_dword[2]); 808 I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe), 809 rc_buf_thresh_dword[3]); 810 } 811 } 812 813 /* Populate the RC_RANGE_PARAMETERS registers */ 814 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); 815 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 816 rc_range_params_dword[i / 2] |= 817 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << 818 RC_BPG_OFFSET_SHIFT) | 819 (vdsc_cfg->rc_range_params[i].range_max_qp << 820 RC_MAX_QP_SHIFT) | 821 (vdsc_cfg->rc_range_params[i].range_min_qp << 822 RC_MIN_QP_SHIFT)) << 16 * (i % 2)); 823 DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i, 824 rc_range_params_dword[i / 2]); 825 } 826 if (!is_pipe_dsc(crtc_state)) { 827 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0, 828 rc_range_params_dword[0]); 829 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW, 830 rc_range_params_dword[1]); 831 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1, 832 rc_range_params_dword[2]); 833 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1_UDW, 834 rc_range_params_dword[3]); 835 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2, 836 rc_range_params_dword[4]); 837 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2_UDW, 838 rc_range_params_dword[5]); 839 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3, 840 rc_range_params_dword[6]); 841 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW, 842 rc_range_params_dword[7]); 843 if (crtc_state->dsc.dsc_split) { 844 I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0, 845 rc_range_params_dword[0]); 846 I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW, 847 rc_range_params_dword[1]); 848 I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1, 849 rc_range_params_dword[2]); 850 I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1_UDW, 851 rc_range_params_dword[3]); 852 I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2, 853 rc_range_params_dword[4]); 854 I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2_UDW, 855 rc_range_params_dword[5]); 856 I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3, 857 rc_range_params_dword[6]); 858 I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3_UDW, 859 rc_range_params_dword[7]); 860 } 861 } else { 862 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), 863 rc_range_params_dword[0]); 864 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe), 865 rc_range_params_dword[1]); 866 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), 867 rc_range_params_dword[2]); 868 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe), 869 rc_range_params_dword[3]); 870 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), 871 rc_range_params_dword[4]); 872 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe), 873 rc_range_params_dword[5]); 874 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), 875 rc_range_params_dword[6]); 876 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), 877 rc_range_params_dword[7]); 878 if (crtc_state->dsc.dsc_split) { 879 I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), 880 rc_range_params_dword[0]); 881 I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), 882 rc_range_params_dword[1]); 883 I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe), 884 rc_range_params_dword[2]); 885 I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe), 886 rc_range_params_dword[3]); 887 I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe), 888 rc_range_params_dword[4]); 889 I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe), 890 rc_range_params_dword[5]); 891 I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe), 892 rc_range_params_dword[6]); 893 I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe), 894 rc_range_params_dword[7]); 895 } 896 } 897 } 898 899 void intel_dsc_get_config(struct intel_encoder *encoder, 900 struct intel_crtc_state *crtc_state) 901 { 902 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 903 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 904 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 905 enum pipe pipe = crtc->pipe; 906 enum intel_display_power_domain power_domain; 907 intel_wakeref_t wakeref; 908 u32 dss_ctl1, dss_ctl2, val; 909 910 if (!intel_dsc_source_support(encoder, crtc_state)) 911 return; 912 913 power_domain = intel_dsc_power_domain(crtc_state); 914 915 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 916 if (!wakeref) 917 return; 918 919 if (!is_pipe_dsc(crtc_state)) { 920 dss_ctl1 = I915_READ(DSS_CTL1); 921 dss_ctl2 = I915_READ(DSS_CTL2); 922 } else { 923 dss_ctl1 = I915_READ(ICL_PIPE_DSS_CTL1(pipe)); 924 dss_ctl2 = I915_READ(ICL_PIPE_DSS_CTL2(pipe)); 925 } 926 927 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; 928 if (!crtc_state->dsc.compression_enable) 929 goto out; 930 931 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && 932 (dss_ctl1 & JOINER_ENABLE); 933 934 /* FIXME: add more state readout as needed */ 935 936 /* PPS1 */ 937 if (!is_pipe_dsc(crtc_state)) 938 val = I915_READ(DSCA_PICTURE_PARAMETER_SET_1); 939 else 940 val = I915_READ(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); 941 vdsc_cfg->bits_per_pixel = val; 942 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; 943 out: 944 intel_display_power_put(dev_priv, power_domain, wakeref); 945 } 946 947 static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, 948 const struct intel_crtc_state *crtc_state) 949 { 950 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 951 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 952 struct mipi_dsi_device *dsi; 953 struct drm_dsc_picture_parameter_set pps; 954 enum port port; 955 956 drm_dsc_pps_payload_pack(&pps, vdsc_cfg); 957 958 for_each_dsi_port(port, intel_dsi->ports) { 959 dsi = intel_dsi->dsi_hosts[port]->device; 960 961 mipi_dsi_picture_parameter_set(dsi, &pps); 962 mipi_dsi_compression_mode(dsi, true); 963 } 964 } 965 966 static void intel_dsc_dp_pps_write(struct intel_encoder *encoder, 967 const struct intel_crtc_state *crtc_state) 968 { 969 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 970 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 971 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 972 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp; 973 974 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ 975 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header); 976 977 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */ 978 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg); 979 980 intel_dig_port->write_infoframe(encoder, crtc_state, 981 DP_SDP_PPS, &dp_dsc_pps_sdp, 982 sizeof(dp_dsc_pps_sdp)); 983 } 984 985 void intel_dsc_enable(struct intel_encoder *encoder, 986 const struct intel_crtc_state *crtc_state) 987 { 988 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 989 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 990 enum pipe pipe = crtc->pipe; 991 i915_reg_t dss_ctl1_reg, dss_ctl2_reg; 992 u32 dss_ctl1_val = 0; 993 u32 dss_ctl2_val = 0; 994 995 if (!crtc_state->dsc.compression_enable) 996 return; 997 998 /* Enable Power wells for VDSC/joining */ 999 intel_display_power_get(dev_priv, 1000 intel_dsc_power_domain(crtc_state)); 1001 1002 intel_dsc_pps_configure(encoder, crtc_state); 1003 1004 if (encoder->type == INTEL_OUTPUT_DSI) 1005 intel_dsc_dsi_pps_write(encoder, crtc_state); 1006 else 1007 intel_dsc_dp_pps_write(encoder, crtc_state); 1008 1009 if (!is_pipe_dsc(crtc_state)) { 1010 dss_ctl1_reg = DSS_CTL1; 1011 dss_ctl2_reg = DSS_CTL2; 1012 } else { 1013 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe); 1014 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe); 1015 } 1016 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; 1017 if (crtc_state->dsc.dsc_split) { 1018 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; 1019 dss_ctl1_val |= JOINER_ENABLE; 1020 } 1021 I915_WRITE(dss_ctl1_reg, dss_ctl1_val); 1022 I915_WRITE(dss_ctl2_reg, dss_ctl2_val); 1023 } 1024 1025 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) 1026 { 1027 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1028 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1029 enum pipe pipe = crtc->pipe; 1030 i915_reg_t dss_ctl1_reg, dss_ctl2_reg; 1031 u32 dss_ctl1_val = 0, dss_ctl2_val = 0; 1032 1033 if (!old_crtc_state->dsc.compression_enable) 1034 return; 1035 1036 if (!is_pipe_dsc(old_crtc_state)) { 1037 dss_ctl1_reg = DSS_CTL1; 1038 dss_ctl2_reg = DSS_CTL2; 1039 } else { 1040 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe); 1041 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe); 1042 } 1043 dss_ctl1_val = I915_READ(dss_ctl1_reg); 1044 if (dss_ctl1_val & JOINER_ENABLE) 1045 dss_ctl1_val &= ~JOINER_ENABLE; 1046 I915_WRITE(dss_ctl1_reg, dss_ctl1_val); 1047 1048 dss_ctl2_val = I915_READ(dss_ctl2_reg); 1049 if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE || 1050 dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE) 1051 dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE | 1052 RIGHT_BRANCH_VDSC_ENABLE); 1053 I915_WRITE(dss_ctl2_reg, dss_ctl2_val); 1054 1055 /* Disable Power wells for VDSC/joining */ 1056 intel_display_power_put_unchecked(dev_priv, 1057 intel_dsc_power_domain(old_crtc_state)); 1058 } 1059
Indexes created Sat Sep 20 22:09:52 GMT 2025