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      1 /* $NetBSD: gicv3_its.h,v 1.10 2025/01/28 21:48:03 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2018 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Jared McNeill <jmcneill (at) invisible.ca>.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #ifndef _ARM_CORTEX_GICV3_ITS_H
     33 #define _ARM_CORTEX_GICV3_ITS_H
     34 
     35 #include <dev/pci/pcivar.h>
     36 
     37 #include <arm/pci/pci_msi_machdep.h>
     38 #include <arm/cortex/gic_reg.h>
     39 #include <arm/cortex/gicv3.h>
     40 
     41 struct gicv3_its_device {
     42 	uint32_t		dev_id;
     43 	u_int			dev_size;
     44 	struct gicv3_dma	dev_itt;
     45 
     46 	LIST_ENTRY(gicv3_its_device) dev_list;
     47 };
     48 
     49 struct gicv3_its_page_table {
     50 	uint32_t		pt_index;
     51 	struct gicv3_dma	pt_dma;
     52 	LIST_ENTRY(gicv3_its_page_table) pt_list;
     53 };
     54 
     55 struct gicv3_its_table {
     56 	void			*tab_l1;
     57 	uint32_t		tab_page_size;
     58 	uint64_t		tab_l1_entry_size;
     59 	uint64_t		tab_l1_num_ids;
     60 	uint64_t		tab_l2_entry_size;
     61 	uint64_t		tab_l2_num_ids;
     62 	bool			tab_indirect;
     63 	bool			tab_shareable;
     64 
     65 	LIST_HEAD(, gicv3_its_page_table) tab_pt;
     66 };
     67 
     68 struct gicv3_its {
     69 	bus_space_tag_t		its_bst;
     70 	bus_space_handle_t	its_bsh;
     71 	bus_dma_tag_t		its_dmat;
     72 	uint32_t		its_id;
     73 	uint64_t		its_base;
     74 	uint64_t		*its_rdbase;
     75 	bool			*its_cpuonline;
     76 
     77 	struct gicv3_softc	*its_gic;
     78 	struct gicv3_lpi_callback its_cb;
     79 
     80 	struct pic_softc	*its_pic;
     81 	struct pci_attach_args	**its_pa;
     82 	struct cpu_info		**its_targets;
     83 	uint32_t		*its_devid;
     84 
     85 	LIST_HEAD(, gicv3_its_device) its_devices;
     86 
     87 	struct gicv3_dma	its_cmd;		/* Command queue */
     88 	struct gicv3_dma	its_tab[8];		/* ITS tables */
     89 
     90 	struct gicv3_its_table	its_tab_device;
     91 
     92 	bool			its_cmd_flush;
     93 
     94 	struct arm_pci_msi	its_msi;
     95 
     96 	kmutex_t		*its_lock;
     97 };
     98 
     99 int	gicv3_its_init(struct gicv3_softc *, bus_space_handle_t, uint64_t, uint32_t);
    100 
    101 #endif /* !_ARM_CORTEX_GICV3_ITS_H */
    102