amdgpu_navi10_ppt.c | 1018 uint32_t level_count = 0, freq = 0; local in function:navi10_get_clock_by_type_with_latency 1026 ret = smu_get_dpm_level_count(smu, clk_type, &level_count); 1030 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS); 1031 clocks->num_levels = level_count; 1033 for (i = 0; i < level_count; i++) { 1424 uint32_t level_count = 0; local in function:navi10_get_profiling_clk_mask 1434 ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count); 1437 *sclk_mask = level_count - 1; 1441 ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count); [all...] |