| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_r300.c | 533 uint32_t link_width_cntl, mask; local in function:rv370_set_pcie_lanes
568 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
570 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
574 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
578 link_width_cntl |= mask;
579 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
580 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
584 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
585 while (link_width_cntl == 0xffffffff)
586 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL)
592 u32 link_width_cntl; local in function:rv370_get_pcie_lanes
[all...] |
| radeon_rv770.c | 2032 u32 link_width_cntl, lanes, speed_cntl, tmp; local in function:rv770_pcie_gen2_enable
2055 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
2056 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
2057 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2058 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
2059 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
2060 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
2061 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
2063 link_width_cntl |= lanes | LC_RECONFIG_NOW |
2065 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
[all...] |
| radeon_r600.c | 4459 u32 link_width_cntl, mask; local in function:r600_set_pcie_lanes
4501 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4502 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;
4503 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;
4504 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |
4507 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4512 u32 link_width_cntl; local in function:r600_get_pcie_lanes
4526 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4528 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4549 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp local in function:r600_pcie_gen2_enable
[all...] |
| radeon_evergreen.c | 5339 u32 link_width_cntl, speed_cntl; local in function:evergreen_pcie_gen2_enable
5369 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
5370 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
5371 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
5390 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
5393 link_width_cntl |= LC_UPCONFIGURE_DIS;
5395 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
5396 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_si.c | 1299 u32 link_width_cntl; local in function:si_get_pcie_lanes
1304 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1306 switch ((link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT) {
1324 u32 link_width_cntl, mask; local in function:si_set_pcie_lanes
1353 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1354 link_width_cntl &= ~LC_LINK_WIDTH_MASK;
1355 link_width_cntl |= mask << LC_LINK_WIDTH_SHIFT;
1356 link_width_cntl |= (LC_RECONFIG_NOW |
1359 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
|
