1 /* $NetBSD: if_iwmreg.h,v 1.14 2023/09/01 11:23:39 andvar Exp $ */ 2 /* OpenBSD: if_iwmreg.h,v 1.19 2016/09/20 11:46:09 stsp Exp */ 3 4 /*- 5 * Based on BSD-licensed source modules in the Linux iwlwifi driver, 6 * which were used as the reference documentation for this implementation. 7 * 8 *********************************************************************** 9 * 10 * This file is provided under a dual BSD/GPLv2 license. When using or 11 * redistributing this file, you may do so under either license. 12 * 13 * GPL LICENSE SUMMARY 14 * 15 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. 16 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 17 * Copyright(c) 2016 Intel Deutschland GmbH 18 * 19 * This program is free software; you can redistribute it and/or modify 20 * it under the terms of version 2 of the GNU General Public License as 21 * published by the Free Software Foundation. 22 * 23 * This program is distributed in the hope that it will be useful, but 24 * WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 26 * General Public License for more details. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 31 * USA 32 * 33 * The full GNU General Public License is included in this distribution 34 * in the file called COPYING. 35 * 36 * Contact Information: 37 * Intel Linux Wireless <linuxwifi (at) intel.com> 38 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 39 * 40 * BSD LICENSE 41 * 42 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 43 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 44 * Copyright(c) 2016 Intel Deutschland GmbH 45 * All rights reserved. 46 * 47 * Redistribution and use in source and binary forms, with or without 48 * modification, are permitted provided that the following conditions 49 * are met: 50 * 51 * * Redistributions of source code must retain the above copyright 52 * notice, this list of conditions and the following disclaimer. 53 * * Redistributions in binary form must reproduce the above copyright 54 * notice, this list of conditions and the following disclaimer in 55 * the documentation and/or other materials provided with the 56 * distribution. 57 * * Neither the name Intel Corporation nor the names of its 58 * contributors may be used to endorse or promote products derived 59 * from this software without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 62 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 63 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 64 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 65 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 66 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 67 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 68 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 69 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 70 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 71 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 72 */ 73 74 /* 75 * CSR (control and status registers) 76 * 77 * CSR registers are mapped directly into PCI bus space, and are accessible 78 * whenever platform supplies power to device, even when device is in 79 * low power states due to driver-invoked device resets 80 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 81 * 82 * Use iwl_write32() and iwl_read32() family to access these registers; 83 * these provide simple PCI bus access, without waking up the MAC. 84 * Do not use iwl_write_direct32() family for these registers; 85 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 86 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 87 * the CSR registers. 88 * 89 * NOTE: Device does need to be awake in order to read this memory 90 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 91 */ 92 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 93 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 94 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 95 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 96 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 97 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 98 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 99 #define IWM_CSR_GP_CNTRL (0x024) 100 101 /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 102 #define IWM_CSR_INT_PERIODIC_REG (0x005) 103 104 /* 105 * Hardware revision info 106 * Bit fields: 107 * 31-16: Reserved 108 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 109 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 110 * 1-0: "Dash" (-) value, as in A-1, etc. 111 */ 112 #define IWM_CSR_HW_REV (0x028) 113 114 /* 115 * EEPROM and OTP (one-time-programmable) memory reads 116 * 117 * NOTE: Device must be awake, initialized via apm_ops.init(), 118 * in order to read. 119 */ 120 #define IWM_CSR_EEPROM_REG (0x02c) 121 #define IWM_CSR_EEPROM_GP (0x030) 122 #define IWM_CSR_OTP_GP_REG (0x034) 123 124 #define IWM_CSR_GIO_REG (0x03C) 125 #define IWM_CSR_GP_UCODE_REG (0x048) 126 #define IWM_CSR_GP_DRIVER_REG (0x050) 127 128 /* 129 * UCODE-DRIVER GP (general purpose) mailbox registers. 130 * SET/CLR registers set/clear bit(s) if "1" is written. 131 */ 132 #define IWM_CSR_UCODE_DRV_GP1 (0x054) 133 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 134 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 135 #define IWM_CSR_UCODE_DRV_GP2 (0x060) 136 137 #define IWM_CSR_MBOX_SET_REG (0x088) 138 #define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20 139 140 #define IWM_CSR_LED_REG (0x094) 141 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 142 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 143 144 145 /* GIO Chicken Bits (PCI Express bus link power management) */ 146 #define IWM_CSR_GIO_CHICKEN_BITS (0x100) 147 148 /* Analog phase-lock-loop configuration */ 149 #define IWM_CSR_ANA_PLL_CFG (0x20c) 150 151 /* 152 * CSR Hardware Revision Workaround Register. Indicates hardware rev; 153 * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 154 * See also IWM_CSR_HW_REV register. 155 * Bit fields: 156 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 157 * 1-0: "Dash" (-) value, as in C-1, etc. 158 */ 159 #define IWM_CSR_HW_REV_WA_REG (0x22C) 160 161 #define IWM_CSR_DBG_HPET_MEM_REG (0x240) 162 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 163 164 /* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 165 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 166 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 167 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 168 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 169 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 170 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 171 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 172 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 173 174 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 175 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 176 #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 177 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 178 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 179 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 180 181 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 182 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 183 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 184 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 185 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 186 #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 187 #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 188 189 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 190 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 191 192 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 193 * acknowledged (reset) by host writing "1" to flagged bits. */ 194 #define IWM_CSR_INT_BIT_FH_RX (1U << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 195 #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 196 #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 197 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 198 #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 199 #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 200 #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 201 #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 202 #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 203 #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 204 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 205 206 #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 207 IWM_CSR_INT_BIT_HW_ERR | \ 208 IWM_CSR_INT_BIT_FH_TX | \ 209 IWM_CSR_INT_BIT_SW_ERR | \ 210 IWM_CSR_INT_BIT_RF_KILL | \ 211 IWM_CSR_INT_BIT_SW_RX | \ 212 IWM_CSR_INT_BIT_WAKEUP | \ 213 IWM_CSR_INT_BIT_ALIVE | \ 214 IWM_CSR_INT_BIT_RX_PERIODIC) 215 216 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 217 #define IWM_CSR_FH_INT_BIT_ERR (1U << 31) /* Error */ 218 #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 219 #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 220 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 221 #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 222 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 223 224 #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 225 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 226 IWM_CSR_FH_INT_BIT_RX_CHNL0) 227 228 #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 229 IWM_CSR_FH_INT_BIT_TX_CHNL0) 230 231 /* GPIO */ 232 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 233 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 234 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 235 236 /* RESET */ 237 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 238 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 239 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 240 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 241 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 242 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 243 244 /* 245 * GP (general purpose) CONTROL REGISTER 246 * Bit fields: 247 * 27: HW_RF_KILL_SW 248 * Indicates state of (platform's) hardware RF-Kill switch 249 * 26-24: POWER_SAVE_TYPE 250 * Indicates current power-saving mode: 251 * 000 -- No power saving 252 * 001 -- MAC power-down 253 * 010 -- PHY (radio) power-down 254 * 011 -- Error 255 * 9-6: SYS_CONFIG 256 * Indicates current system configuration, reflecting pins on chip 257 * as forced high/low by device circuit board. 258 * 4: GOING_TO_SLEEP 259 * Indicates MAC is entering a power-saving sleep power-down. 260 * Not a good time to access device-internal resources. 261 * 3: MAC_ACCESS_REQ 262 * Host sets this to request and maintain MAC wakeup, to allow host 263 * access to device-internal resources. Host must wait for 264 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 265 * device registers. 266 * 2: INIT_DONE 267 * Host sets this to put device into fully operational D0 power mode. 268 * Host resets this after SW_RESET to put device into low power mode. 269 * 0: MAC_CLOCK_READY 270 * Indicates MAC (ucode processor, etc.) is powered up and can run. 271 * Internal resources are accessible. 272 * NOTE: This does not indicate that the processor is actually running. 273 * NOTE: This does not indicate that device has completed 274 * init or post-power-down restore of internal SRAM memory. 275 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 276 * SRAM is restored and uCode is in normal operation mode. 277 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 278 * do not need to save/restore it. 279 * NOTE: After device reset, this bit remains "0" until host sets 280 * INIT_DONE 281 */ 282 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 283 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 284 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 285 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 286 287 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 288 289 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 290 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 291 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 292 293 294 /* HW REV */ 295 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 296 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 297 298 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 299 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 300 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 301 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 302 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 303 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 304 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 305 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 306 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 307 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 308 #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 309 #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 310 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 311 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 312 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 313 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 314 #define IWM_CSR_HW_REV_TYPE_7265D (0x0000210) 315 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 316 317 /* EEPROM REG */ 318 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 319 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 320 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 321 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 322 323 /* EEPROM GP */ 324 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 325 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 326 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 327 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 328 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 329 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 330 331 /* One-time-programmable memory general purpose reg */ 332 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 333 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 334 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 335 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 336 337 /* GP REG */ 338 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 339 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 340 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 341 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 342 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 343 344 345 /* CSR GIO */ 346 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 347 348 /* 349 * UCODE-DRIVER GP (general purpose) mailbox register 1 350 * Host driver and uCode write and/or read this register to communicate with 351 * each other. 352 * Bit fields: 353 * 4: UCODE_DISABLE 354 * Host sets this to request permanent halt of uCode, same as 355 * sending CARD_STATE command with "halt" bit set. 356 * 3: CT_KILL_EXIT 357 * Host sets this to request exit from CT_KILL state, i.e. host thinks 358 * device temperature is low enough to continue normal operation. 359 * 2: CMD_BLOCKED 360 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 361 * to release uCode to clear all Tx and command queues, enter 362 * unassociated mode, and power down. 363 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 364 * 1: SW_BIT_RFKILL 365 * Host sets this when issuing CARD_STATE command to request 366 * device sleep. 367 * 0: MAC_SLEEP 368 * uCode sets this when preparing a power-saving power-down. 369 * uCode resets this when power-up is complete and SRAM is sane. 370 * NOTE: device saves internal SRAM data to host when powering down, 371 * and must restore this data after powering back up. 372 * MAC_SLEEP is the best indication that restore is complete. 373 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 374 * do not need to save/restore it. 375 */ 376 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 377 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 378 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 379 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 380 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 381 382 /* GP Driver */ 383 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 384 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 385 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 386 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 387 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 388 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 389 390 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 391 392 /* GIO Chicken Bits (PCI Express bus link power management) */ 393 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 394 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 395 396 /* LED */ 397 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 398 #define IWM_CSR_LED_REG_TURN_ON (0x60) 399 #define IWM_CSR_LED_REG_TURN_OFF (0x20) 400 401 /* ANA_PLL */ 402 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 403 404 /* HPET MEM debug */ 405 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 406 407 /* DRAM INT TABLE */ 408 #define IWM_CSR_DRAM_INT_TBL_ENABLE (1U << 31) 409 #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 410 #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 411 412 /* SECURE boot registers */ 413 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 414 enum iwm_secure_boot_config_reg { 415 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, 416 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, 417 }; 418 419 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 420 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 421 enum iwm_secure_boot_status_reg { 422 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, 423 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, 424 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, 425 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, 426 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, 427 }; 428 429 #define IWM_FH_UCODE_LOAD_STATUS 0x1af0 430 #define IWM_CSR_UCODE_LOAD_STATUS_ADDR 0x1e70 431 enum iwm_secure_load_status_reg { 432 IWM_LMPM_CPU_UCODE_LOADING_STARTED = 0x00000001, 433 IWM_LMPM_CPU_HDRS_LOADING_COMPLETED = 0x00000003, 434 IWM_LMPM_CPU_UCODE_LOADING_COMPLETED = 0x00000007, 435 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8, 436 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00, 437 }; 438 #define IWM_FH_MEM_TB_MAX_LENGTH 0x20000 439 440 #define IWM_LMPM_SECURE_INSPECTOR_CODE_ADDR 0x1e38 441 #define IWM_LMPM_SECURE_INSPECTOR_DATA_ADDR 0x1e3c 442 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78 443 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c 444 445 #define IWM_LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE 0x400000 446 #define IWM_LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE 0x402000 447 #define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000 448 #define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400 449 450 #define IWM_CSR_SECURE_TIME_OUT (100) 451 452 /* extended range in FW SRAM */ 453 #define IWM_FW_MEM_EXTENDED_START 0x40000 454 #define IWM_FW_MEM_EXTENDED_END 0x57FFF 455 456 /* FW chicken bits */ 457 #define IWM_LMPM_CHICK 0xa01ff8 458 #define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01 459 460 #define IWM_FH_TCSR_0_REG0 (0x1D00) 461 462 /* 463 * HBUS (Host-side Bus) 464 * 465 * HBUS registers are mapped directly into PCI bus space, but are used 466 * to indirectly access device's internal memory or registers that 467 * may be powered-down. 468 * 469 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 470 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 471 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 472 * internal resources. 473 * 474 * Do not use iwl_write32()/iwl_read32() family to access these registers; 475 * these provide only simple PCI bus access, without waking up the MAC. 476 */ 477 #define IWM_HBUS_BASE (0x400) 478 479 /* 480 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 481 * structures, error log, event log, verifying uCode load). 482 * First write to address register, then read from or write to data register 483 * to complete the job. Once the address register is set up, accesses to 484 * data registers auto-increment the address by one dword. 485 * Bit usage for address registers (read or write): 486 * 0-31: memory address within device 487 */ 488 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 489 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 490 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 491 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 492 493 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 494 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 495 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 496 497 /* 498 * Registers for accessing device's internal peripheral registers 499 * (e.g. SCD, BSM, etc.). First write to address register, 500 * then read from or write to data register to complete the job. 501 * Bit usage for address registers (read or write): 502 * 0-15: register address (offset) within device 503 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 504 */ 505 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 506 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 507 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 508 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 509 510 /* enable the ID buf for read */ 511 #define IWM_WFPM_PS_CTL_CLR 0xa0300c 512 #define IWM_WFMP_MAC_ADDR_0 0xa03080 513 #define IWM_WFMP_MAC_ADDR_1 0xa03084 514 #define IWM_LMPM_PMG_EN 0xa01cec 515 #define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 516 #define IWM_RFIC_REG_RD 0xad0470 517 #define IWM_WFPM_CTRL_REG 0xa03030 518 #define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 519 #define IWM_ENABLE_WFPM 0x80000000 520 521 #define IWM_AUX_MISC_REG 0xa200b0 522 #define IWM_HW_STEP_LOCATION_BITS 24 523 524 #define IWM_AUX_MISC_MASTER1_EN 0xa20818 525 #define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 526 #define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 527 #define IWM_RSA_ENABLE 0xa24b08 528 #define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0 529 #define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78 530 #define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000 531 #define IWM_SB_CFG_BASE_OVERRIDE 0xa20000 532 #define IWM_SB_MODIFY_CFG_FLAG 0xa03088 533 #define IWM_SB_CPU_1_STATUS 0xa01e30 534 #define IWM_SB_CPU_2_STATUS 0Xa01e34 535 536 /* Used to enable DBGM */ 537 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 538 539 /* 540 * Per-Tx-queue write pointer (index, really!) 541 * Indicates index to next TFD that driver will fill (1 past latest filled). 542 * Bit usage: 543 * 0-7: queue write index 544 * 11-8: queue selector 545 */ 546 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 547 548 /********************************************************** 549 * CSR values 550 **********************************************************/ 551 /* 552 * host interrupt timeout value 553 * used with setting interrupt coalescing timer 554 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 555 * 556 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 557 */ 558 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 559 #define IWM_HOST_INT_TIMEOUT_DEF (0x40) 560 #define IWM_HOST_INT_TIMEOUT_MIN (0x0) 561 #define IWM_HOST_INT_OPER_MODE (1U << 31) 562 563 /***************************************************************************** 564 * 7000/3000 series SHR DTS addresses * 565 *****************************************************************************/ 566 567 /* Diode Results Register Structure: */ 568 enum iwm_dtd_diode_reg { 569 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 570 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 571 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 572 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 573 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 574 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 575 /* Those are the masks INSIDE the flags bit-field: */ 576 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 577 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 578 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 579 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 580 }; 581 582 /** 583 * enum iwm_ucode_tlv_flag - ucode API flags 584 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 585 * was a separate TLV but moved here to save space. 586 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 587 * treats good CRC threshold as a boolean 588 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 589 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 590 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 591 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 592 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 593 * offload profile config command. 594 * @IWM_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 595 * @IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 596 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 597 * (rather than two) IPv6 addresses 598 * @IWM_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 599 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 600 * from the probe request template. 601 * @IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 602 * connection when going back to D0 603 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 604 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 605 * @IWM_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 606 * @IWM_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 607 * @IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 608 * containing CAM (Continuous Active Mode) indication. 609 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a 610 * single bound interface). 611 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 612 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 613 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 614 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 615 * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients 616 * 617 */ 618 enum iwm_ucode_tlv_flag { 619 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0), 620 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 621 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2), 622 IWM_UCODE_TLV_FLAGS_P2P = (1 << 3), 623 IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 624 IWM_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 625 IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT = (1 << 6), 626 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 627 IWM_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 628 IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 629 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 630 IWM_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 631 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 632 IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 633 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 634 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 635 IWM_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 636 IWM_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 637 IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 638 IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21), 639 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM = (1 << 22), 640 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM = (1 << 23), 641 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24), 642 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25), 643 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26), 644 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29), 645 IWM_UCODE_TLV_FLAGS_GO_UAPSD = (1 << 30), 646 IWM_UCODE_TLV_FLAGS_LTE_COEX = (1U << 31), 647 }; 648 #define IWM_UCODE_TLV_FLAG_BITS \ 649 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERGY\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFFL_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 650 651 /** 652 * enum iwm_ucode_tlv_api - ucode api 653 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 654 * longer than the passive one, which is essential for fragmented scan. 655 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 656 * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header 657 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 658 * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority 659 * instead of 3. 660 * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size 661 * (command version 3) that supports per-chain limits 662 * 663 * @IWM_NUM_UCODE_TLV_API: number of bits used 664 */ 665 enum iwm_ucode_tlv_api { 666 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = 8, 667 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = 9, 668 IWM_UCODE_TLV_API_WIDE_CMD_HDR = 14, 669 IWM_UCODE_TLV_API_LQ_SS_PARAMS = 18, 670 IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY = 24, 671 IWM_UCODE_TLV_API_TX_POWER_CHAIN = 27, 672 673 IWM_NUM_UCODE_TLV_API = 32 674 }; 675 676 #define IWM_UCODE_TLV_API_BITS \ 677 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN" 678 679 /** 680 * enum iwm_ucode_tlv_capa - ucode capabilities 681 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 682 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 683 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 684 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 685 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 686 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 687 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 688 * tx power value into TPC Report action frame and Link Measurement Report 689 * action frame 690 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 691 * channel in DS parameter set element in probe requests. 692 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 693 * probe requests. 694 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 695 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 696 * which also implies support for the scheduler configuration command 697 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 698 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 699 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 700 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 701 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 702 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 703 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 704 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 705 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 706 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 707 * sources for the MCC. This TLV bit is a future replacement to 708 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 709 * is supported. 710 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 711 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 712 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 713 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 714 * 0=no support) 715 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 716 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 717 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 718 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 719 * antenna the beacon should be transmitted 720 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 721 * from AP and will send it upon d0i3 exit. 722 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 723 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 724 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 725 * thresholds reporting 726 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 727 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 728 * regular image. 729 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 730 * memory addresses from the firmware. 731 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 732 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 733 * 0=no support) 734 * 735 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used 736 */ 737 enum iwm_ucode_tlv_capa { 738 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0, 739 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1, 740 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2, 741 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3, 742 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5, 743 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6, 744 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8, 745 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9, 746 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10, 747 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11, 748 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12, 749 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13, 750 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17, 751 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18, 752 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19, 753 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20, 754 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21, 755 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22, 756 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26, 757 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28, 758 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29, 759 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30, 760 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31, 761 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34, 762 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35, 763 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64, 764 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65, 765 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67, 766 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68, 767 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71, 768 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72, 769 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73, 770 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74, 771 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75, 772 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76, 773 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77, 774 IWM_UCODE_TLV_CAPA_LMAC_UPLOAD = 79, 775 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80, 776 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81, 777 778 IWM_NUM_UCODE_TLV_CAPA = 128 779 }; 780 781 /* The default calibrate table size if not specified by firmware file */ 782 #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 783 #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 784 #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 785 786 /* The default max probe length if not specified by the firmware file */ 787 #define IWM_DEFAULT_MAX_PROBE_LENGTH 200 788 789 /* 790 * enumeration of ucode section. 791 * This enumeration is used directly for older firmware (before 16.0). 792 * For new firmware, there can be up to 4 sections (see below) but the 793 * first one packaged into the firmware file is the DATA section and 794 * some debugging code accesses that. 795 */ 796 enum iwm_ucode_sec { 797 IWM_UCODE_SECTION_DATA, 798 IWM_UCODE_SECTION_INST, 799 }; 800 /* 801 * For 16.0 uCode and above, there is no differentiation between sections, 802 * just an offset to the HW address. 803 */ 804 #define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 805 #define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB 806 807 /* uCode version contains 4 values: Major/Minor/API/Serial */ 808 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 809 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 810 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 811 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 812 813 /* 814 * Calibration control struct. 815 * Sent as part of the phy configuration command. 816 * @flow_trigger: bitmap for which calibrations to perform according to 817 * flow triggers. 818 * @event_trigger: bitmap for which calibrations to perform according to 819 * event triggers. 820 */ 821 struct iwm_tlv_calib_ctrl { 822 uint32_t flow_trigger; 823 uint32_t event_trigger; 824 } __packed; 825 826 enum iwm_fw_phy_cfg { 827 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0, 828 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS, 829 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2, 830 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS, 831 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4, 832 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS, 833 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16, 834 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS, 835 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20, 836 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS, 837 }; 838 839 #define IWM_UCODE_MAX_CS 1 840 841 /** 842 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 843 * @cipher: a cipher suite selector 844 * @flags: cipher scheme flags (currently reserved for a future use) 845 * @hdr_len: a size of MPDU security header 846 * @pn_len: a size of PN 847 * @pn_off: an offset of pn from the beginning of the security header 848 * @key_idx_off: an offset of key index byte in the security header 849 * @key_idx_mask: a bit mask of key_idx bits 850 * @key_idx_shift: bit shift needed to get key_idx 851 * @mic_len: mic length in bytes 852 * @hw_cipher: a HW cipher index used in host commands 853 */ 854 struct iwm_fw_cipher_scheme { 855 uint32_t cipher; 856 uint8_t flags; 857 uint8_t hdr_len; 858 uint8_t pn_len; 859 uint8_t pn_off; 860 uint8_t key_idx_off; 861 uint8_t key_idx_mask; 862 uint8_t key_idx_shift; 863 uint8_t mic_len; 864 uint8_t hw_cipher; 865 } __packed; 866 867 /** 868 * struct iwm_fw_cscheme_list - a cipher scheme list 869 * @size: a number of entries 870 * @cs: cipher scheme entries 871 */ 872 struct iwm_fw_cscheme_list { 873 uint8_t size; 874 struct iwm_fw_cipher_scheme cs[]; 875 } __packed; 876 877 /* v1/v2 uCode file layout */ 878 struct iwm_ucode_header { 879 uint32_t ver; /* major/minor/API/serial */ 880 union { 881 struct { 882 uint32_t inst_size; /* bytes of runtime code */ 883 uint32_t data_size; /* bytes of runtime data */ 884 uint32_t init_size; /* bytes of init code */ 885 uint32_t init_data_size; /* bytes of init data */ 886 uint32_t boot_size; /* bytes of bootstrap code */ 887 uint8_t data[0]; /* in same order as sizes */ 888 } v1; 889 struct { 890 uint32_t build; /* build number */ 891 uint32_t inst_size; /* bytes of runtime code */ 892 uint32_t data_size; /* bytes of runtime data */ 893 uint32_t init_size; /* bytes of init code */ 894 uint32_t init_data_size; /* bytes of init data */ 895 uint32_t boot_size; /* bytes of bootstrap code */ 896 uint8_t data[0]; /* in same order as sizes */ 897 } v2; 898 } u; 899 }; 900 901 /* 902 * new TLV uCode file layout 903 * 904 * The new TLV file format contains TLVs, that each specify 905 * some piece of data. 906 */ 907 908 enum iwm_ucode_tlv_type { 909 IWM_UCODE_TLV_INVALID = 0, /* unused */ 910 IWM_UCODE_TLV_INST = 1, 911 IWM_UCODE_TLV_DATA = 2, 912 IWM_UCODE_TLV_INIT = 3, 913 IWM_UCODE_TLV_INIT_DATA = 4, 914 IWM_UCODE_TLV_BOOT = 5, 915 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */ 916 IWM_UCODE_TLV_PAN = 7, 917 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8, 918 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, 919 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10, 920 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11, 921 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12, 922 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13, 923 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14, 924 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, 925 IWM_UCODE_TLV_WOWLAN_INST = 16, 926 IWM_UCODE_TLV_WOWLAN_DATA = 17, 927 IWM_UCODE_TLV_FLAGS = 18, 928 IWM_UCODE_TLV_SEC_RT = 19, 929 IWM_UCODE_TLV_SEC_INIT = 20, 930 IWM_UCODE_TLV_SEC_WOWLAN = 21, 931 IWM_UCODE_TLV_DEF_CALIB = 22, 932 IWM_UCODE_TLV_PHY_SKU = 23, 933 IWM_UCODE_TLV_SECURE_SEC_RT = 24, 934 IWM_UCODE_TLV_SECURE_SEC_INIT = 25, 935 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26, 936 IWM_UCODE_TLV_NUM_OF_CPU = 27, 937 IWM_UCODE_TLV_CSCHEME = 28, 938 939 /* 940 * Following two are not in our base tag, but allow 941 * handling ucode version 9. 942 */ 943 IWM_UCODE_TLV_API_CHANGES_SET = 29, 944 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30, 945 946 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31, 947 IWM_UCODE_TLV_PAGING = 32, 948 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34, 949 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35, 950 IWM_UCODE_TLV_FW_VERSION = 36, 951 IWM_UCODE_TLV_FW_DBG_DEST = 38, 952 IWM_UCODE_TLV_FW_DBG_CONF = 39, 953 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40, 954 IWM_UCODE_TLV_FW_UNDOCUMENTED1 = 48, /* undocumented TLV */ 955 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50, 956 IWM_UCODE_TLV_FW_MEM_SEG = 51, 957 }; 958 959 struct iwm_ucode_tlv { 960 uint32_t type; /* see above */ 961 uint32_t length; /* not including type/length fields */ 962 uint8_t data[0]; 963 }; 964 965 struct iwm_ucode_api { 966 uint32_t api_index; 967 uint32_t api_flags; 968 } __packed; 969 970 struct iwm_ucode_capa { 971 uint32_t api_index; 972 uint32_t api_capa; 973 } __packed; 974 975 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749 976 977 struct iwm_tlv_ucode_header { 978 /* 979 * The TLV style ucode header is distinguished from 980 * the v1/v2 style header by first four bytes being 981 * zero, as such is an invalid combination of 982 * major/minor/API/serial versions. 983 */ 984 uint32_t zero; 985 uint32_t magic; 986 uint8_t human_readable[64]; 987 uint32_t ver; /* major/minor/API/serial */ 988 uint32_t build; 989 uint64_t ignore; 990 /* 991 * The data contained herein has a TLV layout, 992 * see above for the TLV header and types. 993 * Note that each TLV is padded to a length 994 * that is a multiple of 4 for alignment. 995 */ 996 uint8_t data[0]; 997 }; 998 999 /* 1000 * Registers in this file are internal, not PCI bus memory mapped. 1001 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 1002 */ 1003 #define IWM_PRPH_BASE (0x00000) 1004 #define IWM_PRPH_END (0xFFFFF) 1005 1006 /* APMG (power management) constants */ 1007 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 1008 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 1009 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 1010 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 1011 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 1012 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 1013 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 1014 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 1015 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 1016 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 1017 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 1018 1019 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 1020 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 1021 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 1022 1023 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 1024 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 1025 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 1026 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 1027 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 1028 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 1029 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 1030 1031 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 1032 1033 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 1034 1035 /* Device system time */ 1036 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 1037 1038 /* Device NMI register */ 1039 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30 1040 #define IWM_DEVICE_SET_NMI_VAL_HW 0x01 1041 #define IWM_DEVICE_SET_NMI_VAL_DRV 0x80 1042 #define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24 1043 #define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000 1044 1045 /* 1046 * Device reset for family 8000 1047 * write to bit 24 in order to reset the CPU 1048 */ 1049 #define IWM_RELEASE_CPU_RESET 0x300c 1050 #define IWM_RELEASE_CPU_RESET_BIT 0x1000000 1051 1052 1053 /***************************************************************************** 1054 * 7000/3000 series SHR DTS addresses * 1055 *****************************************************************************/ 1056 1057 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 1058 #define IWM_DTSC_CFG_MODE (0x00a10604) 1059 #define IWM_DTSC_VREF_AVG (0x00a10648) 1060 #define IWM_DTSC_VREF5_AVG (0x00a1064c) 1061 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 1062 #define IWM_DTSC_PTAT_AVG (0x00a10650) 1063 1064 1065 /** 1066 * Tx Scheduler 1067 * 1068 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 1069 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 1070 * host DRAM. It steers each frame's Tx command (which contains the frame 1071 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 1072 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 1073 * but one DMA channel may take input from several queues. 1074 * 1075 * Tx DMA FIFOs have dedicated purposes. 1076 * 1077 * For 5000 series and up, they are used differently 1078 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 1079 * 1080 * 0 -- EDCA BK (background) frames, lowest priority 1081 * 1 -- EDCA BE (best effort) frames, normal priority 1082 * 2 -- EDCA VI (video) frames, higher priority 1083 * 3 -- EDCA VO (voice) and management frames, highest priority 1084 * 4 -- unused 1085 * 5 -- unused 1086 * 6 -- unused 1087 * 7 -- Commands 1088 * 1089 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 1090 * In addition, driver can map the remaining queues to Tx DMA/FIFO 1091 * channels 0-3 to support 11n aggregation via EDCA DMA channels. 1092 * 1093 * The driver sets up each queue to work in one of two modes: 1094 * 1095 * 1) Scheduler-Ack, in which the scheduler automatically supports a 1096 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 1097 * contains TFDs for a unique combination of Recipient Address (RA) 1098 * and Traffic Identifier (TID), that is, traffic of a given 1099 * Quality-Of-Service (QOS) priority, destined for a single station. 1100 * 1101 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 1102 * each frame within the BA window, including whether it's been transmitted, 1103 * and whether it's been acknowledged by the receiving station. The device 1104 * automatically processes block-acks received from the receiving STA, 1105 * and reschedules un-acked frames to be retransmitted (successful 1106 * Tx completion may end up being out-of-order). 1107 * 1108 * The driver must maintain the queue's Byte Count table in host DRAM 1109 * for this mode. 1110 * This mode does not support fragmentation. 1111 * 1112 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 1113 * The device may automatically retry Tx, but will retry only one frame 1114 * at a time, until receiving ACK from receiving station, or reaching 1115 * retry limit and giving up. 1116 * 1117 * The command queue (#4/#9) must use this mode! 1118 * This mode does not require use of the Byte Count table in host DRAM. 1119 * 1120 * Driver controls scheduler operation via 3 means: 1121 * 1) Scheduler registers 1122 * 2) Shared scheduler data base in internal SRAM 1123 * 3) Shared data in host DRAM 1124 * 1125 * Initialization: 1126 * 1127 * When loading, driver should allocate memory for: 1128 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 1129 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 1130 * (1024 bytes for each queue). 1131 * 1132 * After receiving "Alive" response from uCode, driver must initialize 1133 * the scheduler (especially for queue #4/#9, the command queue, otherwise 1134 * the driver can't issue commands!): 1135 */ 1136 #define IWM_SCD_MEM_LOWER_BOUND (0x0000) 1137 1138 /** 1139 * Max Tx window size is the max number of contiguous TFDs that the scheduler 1140 * can keep track of at one time when creating block-ack chains of frames. 1141 * Note that "64" matches the number of ack bits in a block-ack packet. 1142 */ 1143 #define IWM_SCD_WIN_SIZE 64 1144 #define IWM_SCD_FRAME_LIMIT 64 1145 1146 #define IWM_SCD_TXFIFO_POS_TID (0) 1147 #define IWM_SCD_TXFIFO_POS_RA (4) 1148 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 1149 1150 /* agn SCD */ 1151 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 1152 #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 1153 #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 1154 #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 1155 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 1156 1157 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 1158 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 1159 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 1160 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 1161 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 1162 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 1163 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1164 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1165 #define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0) 1166 #define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18) 1167 1168 /* Context Data */ 1169 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 1170 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1171 1172 /* Tx status */ 1173 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1174 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1175 1176 /* Translation Data */ 1177 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1178 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 1179 1180 #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 1181 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 1182 1183 #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 1184 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 1185 1186 #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 1187 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 1188 1189 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 1190 1191 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 1192 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 1193 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 1194 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 1195 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 1196 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 1197 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 1198 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 1199 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 1200 #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8) 1201 #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254) 1202 1203 static __inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 1204 { 1205 if (chnl < 20) 1206 return IWM_SCD_BASE + 0x18 + chnl * 4; 1207 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1208 } 1209 1210 static __inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1211 { 1212 if (chnl < 20) 1213 return IWM_SCD_BASE + 0x68 + chnl * 4; 1214 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4; 1215 } 1216 1217 static __inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1218 { 1219 if (chnl < 20) 1220 return IWM_SCD_BASE + 0x10c + chnl * 4; 1221 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4; 1222 } 1223 1224 /*********************** END TX SCHEDULER *************************************/ 1225 1226 /* Oscillator clock */ 1227 #define IWM_OSC_CLK (0xa04068) 1228 #define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1229 1230 /****************************/ 1231 /* Flow Handler Definitions */ 1232 /****************************/ 1233 1234 /** 1235 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1236 * Addresses are offsets from device's PCI hardware base address. 1237 */ 1238 #define IWM_FH_MEM_LOWER_BOUND (0x1000) 1239 #define IWM_FH_MEM_UPPER_BOUND (0x2000) 1240 1241 /** 1242 * Keep-Warm (KW) buffer base address. 1243 * 1244 * Driver must allocate a 4KByte buffer that is for keeping the 1245 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1246 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1247 * from going into a power-savings mode that would cause higher DRAM latency, 1248 * and possible data over/under-runs, before all Tx/Rx is complete. 1249 * 1250 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1251 * of the buffer, which must be 4K aligned. Once this is set up, the device 1252 * automatically invokes keep-warm accesses when normal accesses might not 1253 * be sufficient to maintain fast DRAM response. 1254 * 1255 * Bit fields: 1256 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1257 */ 1258 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1259 1260 1261 /** 1262 * TFD Circular Buffers Base (CBBC) addresses 1263 * 1264 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1265 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1266 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1267 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1268 * aligned (address bits 0-7 must be 0). 1269 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1270 * for them are in different places. 1271 * 1272 * Bit fields in each pointer register: 1273 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1274 */ 1275 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1276 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1277 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1278 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1279 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1280 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1281 1282 /* Find TFD CB base pointer for given queue */ 1283 static __inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1284 { 1285 if (chnl < 16) 1286 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1287 if (chnl < 20) 1288 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1289 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1290 } 1291 1292 1293 /** 1294 * Rx SRAM Control and Status Registers (RSCSR) 1295 * 1296 * These registers provide handshake between driver and device for the Rx queue 1297 * (this queue handles *all* command responses, notifications, Rx data, etc. 1298 * sent from uCode to host driver). Unlike Tx, there is only one Rx 1299 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1300 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1301 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1302 * mapping between RBDs and RBs. 1303 * 1304 * Driver must allocate host DRAM memory for the following, and set the 1305 * physical address of each into device registers: 1306 * 1307 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1308 * entries (although any power of 2, up to 4096, is selectable by driver). 1309 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1310 * (typically 4K, although 8K or 16K are also selectable by driver). 1311 * Driver sets up RB size and number of RBDs in the CB via Rx config 1312 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1313 * 1314 * Bit fields within one RBD: 1315 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1316 * 1317 * Driver sets physical address [35:8] of base of RBD circular buffer 1318 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1319 * 1320 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1321 * (RBs) have been filled, via a "write pointer", actually the index of 1322 * the RB's corresponding RBD within the circular buffer. Driver sets 1323 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1324 * 1325 * Bit fields in lower dword of Rx status buffer (upper dword not used 1326 * by driver: 1327 * 31-12: Not used by driver 1328 * 11- 0: Index of last filled Rx buffer descriptor 1329 * (device writes, driver reads this value) 1330 * 1331 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1332 * enter pointers to these RBs into contiguous RBD circular buffer entries, 1333 * and update the device's "write" index register, 1334 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1335 * 1336 * This "write" index corresponds to the *next* RBD that the driver will make 1337 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1338 * the circular buffer. This value should initially be 0 (before preparing any 1339 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1340 * wrap back to 0 at the end of the circular buffer (but don't wrap before 1341 * "read" index has advanced past 1! See below). 1342 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1343 * 1344 * As the device fills RBs (referenced from contiguous RBDs within the circular 1345 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1346 * to tell the driver the index of the latest filled RBD. The driver must 1347 * read this "read" index from DRAM after receiving an Rx interrupt from device 1348 * 1349 * The driver must also internally keep track of a third index, which is the 1350 * next RBD to process. When receiving an Rx interrupt, driver should process 1351 * all filled but unprocessed RBs up to, but not including, the RB 1352 * corresponding to the "read" index. For example, if "read" index becomes "1", 1353 * driver may process the RB pointed to by RBD 0. Depending on volume of 1354 * traffic, there may be many RBs to process. 1355 * 1356 * If read index == write index, device thinks there is no room to put new data. 1357 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1358 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1359 * and "read" indexes; that is, make sure that there are no more than 254 1360 * buffers waiting to be filled. 1361 */ 1362 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1363 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1364 #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1365 1366 /** 1367 * Physical base address of 8-byte Rx Status buffer. 1368 * Bit fields: 1369 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1370 */ 1371 #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1372 1373 /** 1374 * Physical base address of Rx Buffer Descriptor Circular Buffer. 1375 * Bit fields: 1376 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1377 */ 1378 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1379 1380 /** 1381 * Rx write pointer (index, really!). 1382 * Bit fields: 1383 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1384 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1385 */ 1386 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1387 #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1388 1389 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1390 #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1391 1392 /** 1393 * Rx Config/Status Registers (RCSR) 1394 * Rx Config Reg for channel 0 (only channel used) 1395 * 1396 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1397 * normal operation (see bit fields). 1398 * 1399 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1400 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1401 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1402 * 1403 * Bit fields: 1404 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1405 * '10' operate normally 1406 * 29-24: reserved 1407 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1408 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1409 * 19-18: reserved 1410 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1411 * '10' 12K, '11' 16K. 1412 * 15-14: reserved 1413 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1414 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1415 * typical value 0x10 (about 1/2 msec) 1416 * 3- 0: reserved 1417 */ 1418 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1419 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1420 #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1421 1422 #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1423 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1424 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1425 1426 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1427 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1428 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1429 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1430 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1431 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1432 1433 #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1434 #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1435 #define IWM_RX_RB_TIMEOUT (0x11) 1436 1437 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1438 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1439 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1440 1441 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1442 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1443 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1444 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1445 1446 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1447 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1448 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1449 1450 /** 1451 * Rx Shared Status Registers (RSSR) 1452 * 1453 * After stopping Rx DMA channel (writing 0 to 1454 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1455 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1456 * 1457 * Bit fields: 1458 * 24: 1 = Channel 0 is idle 1459 * 1460 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1461 * contain default values that should not be altered by the driver. 1462 */ 1463 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1464 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1465 1466 #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1467 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1468 #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1469 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1470 1471 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1472 1473 #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1474 1475 /* TFDB Area - TFDs buffer table */ 1476 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1477 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1478 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1479 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1480 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1481 1482 /** 1483 * Transmit DMA Channel Control/Status Registers (TCSR) 1484 * 1485 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1486 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1487 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1488 * 1489 * To use a Tx DMA channel, driver must initialize its 1490 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1491 * 1492 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1493 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1494 * 1495 * All other bits should be 0. 1496 * 1497 * Bit fields: 1498 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1499 * '10' operate normally 1500 * 29- 4: Reserved, set to "0" 1501 * 3: Enable internal DMA requests (1, normal operation), disable (0) 1502 * 2- 0: Reserved, set to "0" 1503 */ 1504 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1505 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1506 1507 /* Find Control/Status reg for given Tx DMA/FIFO channel */ 1508 #define IWM_FH_TCSR_CHNL_NUM (8) 1509 1510 /* TCSR: tx_config register values */ 1511 #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1512 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1513 #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1514 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1515 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1516 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1517 1518 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1519 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1520 1521 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1522 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1523 1524 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1525 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1526 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1527 1528 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1529 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1530 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1531 1532 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1533 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1534 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1535 1536 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1537 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1538 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1539 1540 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1541 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1542 1543 /** 1544 * Tx Shared Status Registers (TSSR) 1545 * 1546 * After stopping Tx DMA channel (writing 0 to 1547 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1548 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1549 * (channel's buffers empty | no pending requests). 1550 * 1551 * Bit fields: 1552 * 31-24: 1 = Channel buffers empty (channel 7:0) 1553 * 23-16: 1 = No pending requests (channel 7:0) 1554 */ 1555 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1556 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1557 1558 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1559 1560 /** 1561 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1562 * 31: Indicates an address error when accessed to internal memory 1563 * uCode/driver must write "1" in order to clear this flag 1564 * 30: Indicates that Host did not send the expected number of dwords to FH 1565 * uCode/driver must write "1" in order to clear this flag 1566 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1567 * command was received from the scheduler while the TRB was already full 1568 * with previous command 1569 * uCode/driver must write "1" in order to clear this flag 1570 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1571 * bit is set, it indicates that the FH has received a full indication 1572 * from the RTC TxFIFO and the current value of the TxCredit counter was 1573 * not equal to zero. This mean that the credit mechanism was not 1574 * synchronized to the TxFIFO status 1575 * uCode/driver must write "1" in order to clear this flag 1576 */ 1577 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1578 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1579 1580 #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1581 1582 /* Tx service channels */ 1583 #define IWM_FH_SRVC_CHNL (9) 1584 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1585 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1586 #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1587 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1588 1589 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1590 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1591 (_chan) * 4) 1592 1593 /* Instruct FH to increment the retry count of a packet when 1594 * it is brought from the memory to TX-FIFO 1595 */ 1596 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1597 1598 #define IWM_RX_QUEUE_SIZE 256 1599 #define IWM_RX_QUEUE_MASK 255 1600 #define IWM_RX_QUEUE_SIZE_LOG 8 1601 1602 /* 1603 * RX related structures and functions 1604 */ 1605 #define IWM_RX_FREE_BUFFERS 64 1606 #define IWM_RX_LOW_WATERMARK 8 1607 1608 /** 1609 * struct iwm_rb_status - reseve buffer status 1610 * host memory mapped FH registers 1611 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1612 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1613 * @finished_rb_num [0:11] - Indicates the index of the current RB 1614 * in which the last frame was written to 1615 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1616 * which was transferred 1617 */ 1618 struct iwm_rb_status { 1619 uint16_t closed_rb_num; 1620 uint16_t closed_fr_num; 1621 uint16_t finished_rb_num; 1622 uint16_t finished_fr_nam; 1623 uint32_t unused; 1624 } __packed; 1625 1626 1627 #define IWM_TFD_QUEUE_SIZE_MAX (256) 1628 #define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1629 #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1630 IWM_TFD_QUEUE_SIZE_BC_DUP) 1631 #define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1632 #define IWM_NUM_OF_TBS 20 1633 1634 static __inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1635 { 1636 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1637 } 1638 /** 1639 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1640 * 1641 * This structure contains dma address and length of transmission address 1642 * 1643 * @lo: low [31:0] portion of the dma address of TX buffer 1644 * every even is unaligned on 16 bit boundary 1645 * @hi_n_len 0-3 [35:32] portion of dma 1646 * 4-15 length of the tx buffer 1647 */ 1648 struct iwm_tfd_tb { 1649 uint32_t lo; 1650 uint16_t hi_n_len; 1651 } __packed; 1652 1653 /** 1654 * struct iwm_tfd 1655 * 1656 * Transmit Frame Descriptor (TFD) 1657 * 1658 * @ __reserved1[3] reserved 1659 * @ num_tbs 0-4 number of active tbs 1660 * 5 reserved 1661 * 6-7 padding (not used) 1662 * @ tbs[20] transmit frame buffer descriptors 1663 * @ __pad padding 1664 * 1665 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1666 * Both driver and device share these circular buffers, each of which must be 1667 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1668 * 1669 * Driver must indicate the physical address of the base of each 1670 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1671 * 1672 * Each TFD contains pointer/size information for up to 20 data buffers 1673 * in host DRAM. These buffers collectively contain the (one) frame described 1674 * by the TFD. Each buffer must be a single contiguous block of memory within 1675 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1676 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1677 * Tx frame, up to 8 KBytes in size. 1678 * 1679 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1680 */ 1681 struct iwm_tfd { 1682 uint8_t __reserved1[3]; 1683 uint8_t num_tbs; 1684 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1685 uint32_t __pad; 1686 } __packed; 1687 1688 /* Keep Warm Size */ 1689 #define IWM_KW_SIZE 0x1000 /* 4k */ 1690 1691 /* Fixed (non-configurable) rx data from phy */ 1692 1693 /** 1694 * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1695 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1696 * @tfd_offset 0-12 - tx command byte count 1697 * 12-16 - station index 1698 */ 1699 struct iwm_agn_scd_bc_tbl { 1700 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1701 } __packed; 1702 1703 /* Maximum number of Tx queues. */ 1704 #define IWM_MAX_QUEUES 31 1705 1706 /* Tx queue numbers */ 1707 enum { 1708 IWM_OFFCHANNEL_QUEUE = 8, 1709 IWM_CMD_QUEUE = 9, 1710 IWM_AUX_QUEUE = 15, 1711 }; 1712 1713 enum iwm_mvm_tx_fifo { 1714 IWM_TX_FIFO_BK = 0, 1715 IWM_TX_FIFO_BE, 1716 IWM_TX_FIFO_VI, 1717 IWM_TX_FIFO_VO, 1718 IWM_TX_FIFO_MCAST = 5, 1719 IWM_TX_FIFO_CMD = 7, 1720 }; 1721 1722 #define IWM_STATION_COUNT 16 1723 1724 /* commands */ 1725 enum { 1726 IWM_ALIVE = 0x1, 1727 IWM_REPLY_ERROR = 0x2, 1728 1729 IWM_INIT_COMPLETE_NOTIF = 0x4, 1730 1731 /* PHY context commands */ 1732 IWM_PHY_CONTEXT_CMD = 0x8, 1733 IWM_DBG_CFG = 0x9, 1734 1735 /* UMAC scan commands */ 1736 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5, 1737 IWM_SCAN_CFG_CMD = 0xc, 1738 IWM_SCAN_REQ_UMAC = 0xd, 1739 IWM_SCAN_ABORT_UMAC = 0xe, 1740 IWM_SCAN_COMPLETE_UMAC = 0xf, 1741 1742 /* station table */ 1743 IWM_ADD_STA_KEY = 0x17, 1744 IWM_ADD_STA = 0x18, 1745 IWM_REMOVE_STA = 0x19, 1746 1747 /* TX */ 1748 IWM_TX_CMD = 0x1c, 1749 IWM_TXPATH_FLUSH = 0x1e, 1750 IWM_MGMT_MCAST_KEY = 0x1f, 1751 1752 /* scheduler config */ 1753 IWM_SCD_QUEUE_CFG = 0x1d, 1754 1755 /* global key */ 1756 IWM_WEP_KEY = 0x20, 1757 1758 /* MAC and Binding commands */ 1759 IWM_MAC_CONTEXT_CMD = 0x28, 1760 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */ 1761 IWM_TIME_EVENT_NOTIFICATION = 0x2a, 1762 IWM_BINDING_CONTEXT_CMD = 0x2b, 1763 IWM_TIME_QUOTA_CMD = 0x2c, 1764 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d, 1765 1766 IWM_LQ_CMD = 0x4e, 1767 1768 /* paging block to FW cpu2 */ 1769 IWM_FW_PAGING_BLOCK_CMD = 0x4f, 1770 1771 /* Calibration */ 1772 IWM_TEMPERATURE_NOTIFICATION = 0x62, 1773 IWM_CALIBRATION_CFG_CMD = 0x65, 1774 IWM_CALIBRATION_RES_NOTIFICATION = 0x66, 1775 IWM_CALIBRATION_COMPLETE_NOTIFICATION = 0x67, 1776 IWM_RADIO_VERSION_NOTIFICATION = 0x68, 1777 1778 /* Scan offload */ 1779 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51, 1780 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52, 1781 IWM_HOT_SPOT_CMD = 0x53, 1782 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d, 1783 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e, 1784 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f, 1785 IWM_MATCH_FOUND_NOTIFICATION = 0xd9, 1786 IWM_SCAN_ITERATION_COMPLETE = 0xe7, 1787 1788 /* Phy */ 1789 IWM_PHY_CONFIGURATION_CMD = 0x6a, 1790 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b, 1791 IWM_PHY_DB_CMD = 0x6c, 1792 1793 /* Power - legacy power table command */ 1794 IWM_POWER_TABLE_CMD = 0x77, 1795 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78, 1796 1797 /* Thermal Throttling*/ 1798 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e, 1799 1800 /* Scanning */ 1801 IWM_SCAN_REQUEST_CMD = 0x80, 1802 IWM_SCAN_ABORT_CMD = 0x81, 1803 IWM_SCAN_START_NOTIFICATION = 0x82, 1804 IWM_SCAN_RESULTS_NOTIFICATION = 0x83, 1805 IWM_SCAN_COMPLETE_NOTIFICATION = 0x84, 1806 1807 /* NVM */ 1808 IWM_NVM_ACCESS_CMD = 0x88, 1809 1810 IWM_SET_CALIB_DEFAULT_CMD = 0x8e, 1811 1812 IWM_BEACON_NOTIFICATION = 0x90, 1813 IWM_BEACON_TEMPLATE_CMD = 0x91, 1814 IWM_TX_ANT_CONFIGURATION_CMD = 0x98, 1815 IWM_BT_CONFIG = 0x9b, 1816 IWM_STATISTICS_NOTIFICATION = 0x9d, 1817 IWM_REDUCE_TX_POWER_CMD = 0x9f, 1818 1819 /* RF-KILL commands and notifications */ 1820 IWM_CARD_STATE_CMD = 0xa0, 1821 IWM_CARD_STATE_NOTIFICATION = 0xa1, 1822 1823 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2, 1824 1825 IWM_MFUART_LOAD_NOTIFICATION = 0xb1, 1826 1827 /* Power - new power table command */ 1828 IWM_MAC_PM_POWER_TABLE = 0xa9, 1829 1830 IWM_REPLY_RX_PHY_CMD = 0xc0, 1831 IWM_REPLY_RX_MPDU_CMD = 0xc1, 1832 IWM_BA_NOTIF = 0xc5, 1833 1834 /* Location Aware Regulatory */ 1835 IWM_MCC_UPDATE_CMD = 0xc8, 1836 IWM_MCC_CHUB_UPDATE_CMD = 0xc9, 1837 1838 /* BT Coex */ 1839 IWM_BT_COEX_PRIO_TABLE = 0xcc, 1840 IWM_BT_COEX_PROT_ENV = 0xcd, 1841 IWM_BT_PROFILE_NOTIFICATION = 0xce, 1842 IWM_BT_COEX_CI = 0x5d, 1843 1844 IWM_REPLY_SF_CFG_CMD = 0xd1, 1845 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2, 1846 1847 /* DTS measurements */ 1848 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc, 1849 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd, 1850 1851 IWM_REPLY_DEBUG_CMD = 0xf0, 1852 IWM_DEBUG_LOG_MSG = 0xf7, 1853 1854 IWM_MCAST_FILTER_CMD = 0xd0, 1855 1856 /* D3 commands/notifications */ 1857 IWM_D3_CONFIG_CMD = 0xd3, 1858 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4, 1859 IWM_OFFLOADS_QUERY_CMD = 0xd5, 1860 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6, 1861 1862 /* for WoWLAN in particular */ 1863 IWM_WOWLAN_PATTERNS = 0xe0, 1864 IWM_WOWLAN_CONFIGURATION = 0xe1, 1865 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2, 1866 IWM_WOWLAN_TKIP_PARAM = 0xe3, 1867 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4, 1868 IWM_WOWLAN_GET_STATUSES = 0xe5, 1869 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6, 1870 1871 /* and for NetDetect */ 1872 IWM_NET_DETECT_CONFIG_CMD = 0x54, 1873 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56, 1874 IWM_NET_DETECT_PROFILES_CMD = 0x57, 1875 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58, 1876 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, 1877 1878 IWM_REPLY_MAX = 0xff, 1879 }; 1880 1881 enum iwm_phy_ops_subcmd_ids { 1882 IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE = 0x0, 1883 IWM_CTDP_CONFIG_CMD = 0x03, 1884 IWM_TEMP_REPORTING_THRESHOLDS_CMD = 0x04, 1885 IWM_CT_KILL_NOTIFICATION = 0xFE, 1886 IWM_DTS_MEASUREMENT_NOTIF_WIDE = 0xFF, 1887 }; 1888 1889 /* command groups */ 1890 enum { 1891 IWM_LEGACY_GROUP = 0x0, 1892 IWM_LONG_GROUP = 0x1, 1893 IWM_SYSTEM_GROUP = 0x2, 1894 IWM_MAC_CONF_GROUP = 0x3, 1895 IWM_PHY_OPS_GROUP = 0x4, 1896 IWM_DATA_PATH_GROUP = 0x5, 1897 IWM_PROT_OFFLOAD_GROUP = 0xb, 1898 }; 1899 1900 /** 1901 * struct iwm_cmd_response - generic response struct for most commands 1902 * @status: status of the command asked, changes for each one 1903 */ 1904 struct iwm_cmd_response { 1905 uint32_t status; 1906 }; 1907 1908 /* 1909 * struct iwm_tx_ant_cfg_cmd 1910 * @valid: valid antenna configuration 1911 */ 1912 struct iwm_tx_ant_cfg_cmd { 1913 uint32_t valid; 1914 } __packed; 1915 1916 /** 1917 * struct iwm_reduce_tx_power_cmd - TX power reduction command 1918 * IWM_REDUCE_TX_POWER_CMD = 0x9f 1919 * @flags: (reserved for future implementation) 1920 * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1921 * @pwr_restriction: TX power restriction in dBms. 1922 */ 1923 struct iwm_reduce_tx_power_cmd { 1924 uint8_t flags; 1925 uint8_t mac_context_id; 1926 uint16_t pwr_restriction; 1927 } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 1928 1929 /* 1930 * Calibration control struct. 1931 * Sent as part of the phy configuration command. 1932 * @flow_trigger: bitmap for which calibrations to perform according to 1933 * flow triggers. 1934 * @event_trigger: bitmap for which calibrations to perform according to 1935 * event triggers. 1936 */ 1937 struct iwm_calib_ctrl { 1938 uint32_t flow_trigger; 1939 uint32_t event_trigger; 1940 } __packed; 1941 1942 /* This enum defines the bitmap of various calibrations to enable in both 1943 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 1944 */ 1945 enum iwm_calib_cfg { 1946 IWM_CALIB_CFG_XTAL_IDX = (1 << 0), 1947 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1), 1948 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2), 1949 IWM_CALIB_CFG_PAPD_IDX = (1 << 3), 1950 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4), 1951 IWM_CALIB_CFG_DC_IDX = (1 << 5), 1952 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6), 1953 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7), 1954 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8), 1955 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9), 1956 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10), 1957 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11), 1958 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12), 1959 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13), 1960 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14), 1961 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15), 1962 IWM_CALIB_CFG_DAC_IDX = (1 << 16), 1963 IWM_CALIB_CFG_ABS_IDX = (1 << 17), 1964 IWM_CALIB_CFG_AGC_IDX = (1 << 18), 1965 }; 1966 1967 /* 1968 * Phy configuration command. 1969 */ 1970 struct iwm_phy_cfg_cmd { 1971 uint32_t phy_cfg; 1972 struct iwm_calib_ctrl calib_control; 1973 } __packed; 1974 1975 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 1976 #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 1977 #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 1978 #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 1979 #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 1980 #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 1981 #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 1982 #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 1983 #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 1984 #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 1985 1986 /* 1987 * PHY db 1988 */ 1989 1990 enum iwm_phy_db_section_type { 1991 IWM_PHY_DB_CFG = 1, 1992 IWM_PHY_DB_CALIB_NCH, 1993 IWM_PHY_DB_UNUSED, 1994 IWM_PHY_DB_CALIB_CHG_PAPD, 1995 IWM_PHY_DB_CALIB_CHG_TXP, 1996 IWM_PHY_DB_MAX 1997 }; 1998 1999 /* 2000 * phy db - configure operational ucode 2001 */ 2002 struct iwm_phy_db_cmd { 2003 uint16_t type; 2004 uint16_t length; 2005 uint8_t data[]; 2006 } __packed; 2007 2008 /* for parsing of tx power channel group data that comes from the firmware*/ 2009 struct iwm_phy_db_chg_txp { 2010 uint32_t space; 2011 uint16_t max_channel_idx; 2012 } __packed; 2013 2014 /* 2015 * phy db - Receive phy db chunk after calibrations 2016 */ 2017 struct iwm_calib_res_notif_phy_db { 2018 uint16_t type; 2019 uint16_t length; 2020 uint8_t data[]; 2021 } __packed; 2022 2023 /* 7k family NVM HW-Section offset (in words) definitions */ 2024 #define IWM_HW_ADDR 0x15 2025 /* 7k family NVM SW-Section offset (in words) definitions */ 2026 #define IWM_NVM_SW_SECTION 0x1C0 2027 #define IWM_NVM_VERSION 0 2028 #define IWM_RADIO_CFG 1 2029 #define IWM_SKU 2 2030 #define IWM_N_HW_ADDRS 3 2031 #define IWM_NVM_CHANNELS 0x1E0 - IWM_NVM_SW_SECTION 2032 /* 7k family NVM calibration section offset (in words) definitions */ 2033 #define IWM_NVM_CALIB_SECTION 0x2B8 2034 #define IWM_XTAL_CALIB (0x316 - IWM_NVM_CALIB_SECTION) 2035 2036 /* 8k family NVM HW-Section offset (in words) definitions */ 2037 #define IWM_HW_ADDR0_WFPM_8000 0x12 2038 #define IWM_HW_ADDR1_WFPM_8000 0x16 2039 #define IWM_HW_ADDR0_PCIE_8000 0x8A 2040 #define IWM_HW_ADDR1_PCIE_8000 0x8E 2041 #define IWM_MAC_ADDRESS_OVERRIDE_8000 1 2042 2043 /* 8k family NVM SW-Section offset (in words) definitions */ 2044 #define IWM_NVM_SW_SECTION_8000 0x1C0 2045 #define IWM_NVM_VERSION_8000 0 2046 #define IWM_RADIO_CFG_8000 0 2047 #define IWM_SKU_8000 2 2048 #define IWM_N_HW_ADDRS_8000 3 2049 2050 /* 8k family NVM REGULATORY -Section offset (in words) definitions */ 2051 #define IWM_NVM_CHANNELS_8000 0 2052 #define IWM_NVM_LAR_OFFSET_8000_OLD 0x4C7 2053 #define IWM_NVM_LAR_OFFSET_8000 0x507 2054 #define IWM_NVM_LAR_ENABLED_8000 0x7 2055 2056 /* 8k family NVM calibration section offset (in words) definitions */ 2057 #define IWM_NVM_CALIB_SECTION_8000 0x2B8 2058 #define IWM_XTAL_CALIB_8000 (0x316 - IWM_NVM_CALIB_SECTION_8000) 2059 2060 /* SKU Capabilities (actual values from NVM definition) */ 2061 #define IWM_NVM_SKU_CAP_BAND_24GHZ (1 << 0) 2062 #define IWM_NVM_SKU_CAP_BAND_52GHZ (1 << 1) 2063 #define IWM_NVM_SKU_CAP_11N_ENABLE (1 << 2) 2064 #define IWM_NVM_SKU_CAP_11AC_ENABLE (1 << 3) 2065 #define IWM_NVM_SKU_CAP_MIMO_DISABLE (1 << 5) 2066 2067 /* radio config bits (actual values from NVM definition) */ 2068 #define IWM_NVM_RF_CFG_DASH_MSK(x) (x & 0x3) /* bits 0-1 */ 2069 #define IWM_NVM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */ 2070 #define IWM_NVM_RF_CFG_TYPE_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */ 2071 #define IWM_NVM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */ 2072 #define IWM_NVM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */ 2073 #define IWM_NVM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */ 2074 2075 #define IWM_NVM_RF_CFG_PNUM_MSK_8000(x) (x & 0xF) 2076 #define IWM_NVM_RF_CFG_DASH_MSK_8000(x) ((x >> 4) & 0xF) 2077 #define IWM_NVM_RF_CFG_STEP_MSK_8000(x) ((x >> 8) & 0xF) 2078 #define IWM_NVM_RF_CFG_TYPE_MSK_8000(x) ((x >> 12) & 0xFFF) 2079 #define IWM_NVM_RF_CFG_TX_ANT_MSK_8000(x) ((x >> 24) & 0xF) 2080 #define IWM_NVM_RF_CFG_RX_ANT_MSK_8000(x) ((x >> 28) & 0xF) 2081 2082 #define DEFAULT_MAX_TX_POWER 16 2083 2084 /* 2085 * channel flags in NVM 2086 * @IWM_NVM_CHANNEL_VALID: channel is usable for this SKU/geo 2087 * @IWM_NVM_CHANNEL_IBSS: usable as an IBSS channel 2088 * @IWM_NVM_CHANNEL_ACTIVE: active scanning allowed 2089 * @IWM_NVM_CHANNEL_RADAR: radar detection required 2090 * @IWM_NVM_CHANNEL_DFS: dynamic freq selection candidate 2091 * @IWM_NVM_CHANNEL_WIDE: 20 MHz channel okay (?) 2092 * @IWM_NVM_CHANNEL_40MHZ: 40 MHz channel okay (?) 2093 * @IWM_NVM_CHANNEL_80MHZ: 80 MHz channel okay (?) 2094 * @IWM_NVM_CHANNEL_160MHZ: 160 MHz channel okay (?) 2095 */ 2096 #define IWM_NVM_CHANNEL_VALID (1 << 0) 2097 #define IWM_NVM_CHANNEL_IBSS (1 << 1) 2098 #define IWM_NVM_CHANNEL_ACTIVE (1 << 3) 2099 #define IWM_NVM_CHANNEL_RADAR (1 << 4) 2100 #define IWM_NVM_CHANNEL_DFS (1 << 7) 2101 #define IWM_NVM_CHANNEL_WIDE (1 << 8) 2102 #define IWM_NVM_CHANNEL_40MHZ (1 << 9) 2103 #define IWM_NVM_CHANNEL_80MHZ (1 << 10) 2104 #define IWM_NVM_CHANNEL_160MHZ (1 << 11) 2105 2106 /* Target of the IWM_NVM_ACCESS_CMD */ 2107 enum { 2108 IWM_NVM_ACCESS_TARGET_CACHE = 0, 2109 IWM_NVM_ACCESS_TARGET_OTP = 1, 2110 IWM_NVM_ACCESS_TARGET_EEPROM = 2, 2111 }; 2112 2113 /* Section types for IWM_NVM_ACCESS_CMD */ 2114 enum { 2115 IWM_NVM_SECTION_TYPE_HW = 0, 2116 IWM_NVM_SECTION_TYPE_SW, 2117 IWM_NVM_SECTION_TYPE_PAPD, 2118 IWM_NVM_SECTION_TYPE_REGULATORY, 2119 IWM_NVM_SECTION_TYPE_CALIBRATION, 2120 IWM_NVM_SECTION_TYPE_PRODUCTION, 2121 IWM_NVM_SECTION_TYPE_POST_FCS_CALIB, 2122 /* 7, 8, 9 unknown */ 2123 IWM_NVM_SECTION_TYPE_HW_8000 = 10, 2124 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE, 2125 IWM_NVM_SECTION_TYPE_PHY_SKU, 2126 IWM_NVM_NUM_OF_SECTIONS, 2127 }; 2128 2129 /** 2130 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 2131 * @op_code: 0 - read, 1 - write 2132 * @target: IWM_NVM_ACCESS_TARGET_* 2133 * @type: IWM_NVM_SECTION_TYPE_* 2134 * @offset: offset in bytes into the section 2135 * @length: in bytes, to read/write 2136 * @data: if write operation, the data to write. On read its empty 2137 */ 2138 struct iwm_nvm_access_cmd { 2139 uint8_t op_code; 2140 uint8_t target; 2141 uint16_t type; 2142 uint16_t offset; 2143 uint16_t length; 2144 uint8_t data[]; 2145 } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 2146 2147 #define IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */ 2148 2149 /* 2150 * struct iwm_fw_paging_cmd - paging layout 2151 * 2152 * (IWM_FW_PAGING_BLOCK_CMD = 0x4f) 2153 * 2154 * Send to FW the paging layout in the driver. 2155 * 2156 * @flags: various flags for the command 2157 * @block_size: the block size in powers of 2 2158 * @block_num: number of blocks specified in the command. 2159 * @device_phy_addr: virtual addresses from device side 2160 * 32 bit address for API version 1, 64 bit address for API version 2. 2161 */ 2162 struct iwm_fw_paging_cmd { 2163 uint32_t flags; 2164 uint32_t block_size; 2165 uint32_t block_num; 2166 union { 2167 uint32_t addr32[IWM_NUM_OF_FW_PAGING_BLOCKS]; 2168 uint64_t addr64[IWM_NUM_OF_FW_PAGING_BLOCKS]; 2169 } device_phy_addr; 2170 } __packed; /* FW_PAGING_BLOCK_CMD_API_S_VER_2 */ 2171 2172 /* 2173 * Fw items ID's 2174 * 2175 * @IWM_FW_ITEM_ID_PAGING: Address of the pages that the FW will upload 2176 * download 2177 */ 2178 enum iwm_fw_item_id { 2179 IWM_FW_ITEM_ID_PAGING = 3, 2180 }; 2181 2182 /* 2183 * struct iwm_fw_get_item_cmd - get an item from the fw 2184 */ 2185 struct iwm_fw_get_item_cmd { 2186 uint32_t item_id; 2187 } __packed; /* FW_GET_ITEM_CMD_API_S_VER_1 */ 2188 2189 /** 2190 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 2191 * @offset: offset in bytes into the section 2192 * @length: in bytes, either how much was written or read 2193 * @type: IWM_NVM_SECTION_TYPE_* 2194 * @status: 0 for success, fail otherwise 2195 * @data: if read operation, the data returned. Empty on write. 2196 */ 2197 struct iwm_nvm_access_resp { 2198 uint16_t offset; 2199 uint16_t length; 2200 uint16_t type; 2201 uint16_t status; 2202 uint8_t data[]; 2203 } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 2204 2205 /* IWM_ALIVE 0x1 */ 2206 2207 /* alive response is_valid values */ 2208 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 2209 #define IWM_ALIVE_RESP_RFKILL (1 << 1) 2210 2211 /* alive response ver_type values */ 2212 enum { 2213 IWM_FW_TYPE_HW = 0, 2214 IWM_FW_TYPE_PROT = 1, 2215 IWM_FW_TYPE_AP = 2, 2216 IWM_FW_TYPE_WOWLAN = 3, 2217 IWM_FW_TYPE_TIMING = 4, 2218 IWM_FW_TYPE_WIPAN = 5 2219 }; 2220 2221 /* alive response ver_subtype values */ 2222 enum { 2223 IWM_FW_SUBTYPE_FULL_FEATURE = 0, 2224 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */ 2225 IWM_FW_SUBTYPE_REDUCED = 2, 2226 IWM_FW_SUBTYPE_ALIVE_ONLY = 3, 2227 IWM_FW_SUBTYPE_WOWLAN = 4, 2228 IWM_FW_SUBTYPE_AP_SUBTYPE = 5, 2229 IWM_FW_SUBTYPE_WIPAN = 6, 2230 IWM_FW_SUBTYPE_INITIALIZE = 9 2231 }; 2232 2233 #define IWM_ALIVE_STATUS_ERR 0xDEAD 2234 #define IWM_ALIVE_STATUS_OK 0xCAFE 2235 2236 #define IWM_ALIVE_FLG_RFKILL (1 << 0) 2237 2238 struct iwm_alive_resp_v1 { 2239 uint16_t status; 2240 uint16_t flags; 2241 uint8_t ucode_minor; 2242 uint8_t ucode_major; 2243 uint16_t id; 2244 uint8_t api_minor; 2245 uint8_t api_major; 2246 uint8_t ver_subtype; 2247 uint8_t ver_type; 2248 uint8_t mac; 2249 uint8_t opt; 2250 uint16_t reserved2; 2251 uint32_t timestamp; 2252 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2253 uint32_t log_event_table_ptr; /* SRAM address for event log */ 2254 uint32_t cpu_register_ptr; 2255 uint32_t dbgm_config_ptr; 2256 uint32_t alive_counter_ptr; 2257 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2258 } __packed; /* IWM_ALIVE_RES_API_S_VER_1 */ 2259 2260 struct iwm_alive_resp_v2 { 2261 uint16_t status; 2262 uint16_t flags; 2263 uint8_t ucode_minor; 2264 uint8_t ucode_major; 2265 uint16_t id; 2266 uint8_t api_minor; 2267 uint8_t api_major; 2268 uint8_t ver_subtype; 2269 uint8_t ver_type; 2270 uint8_t mac; 2271 uint8_t opt; 2272 uint16_t reserved2; 2273 uint32_t timestamp; 2274 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2275 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2276 uint32_t cpu_register_ptr; 2277 uint32_t dbgm_config_ptr; 2278 uint32_t alive_counter_ptr; 2279 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2280 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2281 uint32_t st_fwrd_size; 2282 uint8_t umac_minor; /* UMAC version: minor */ 2283 uint8_t umac_major; /* UMAC version: major */ 2284 uint16_t umac_id; /* UMAC version: id */ 2285 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2286 uint32_t dbg_print_buff_addr; 2287 } __packed; /* ALIVE_RES_API_S_VER_2 */ 2288 2289 struct iwm_alive_resp_v3 { 2290 uint16_t status; 2291 uint16_t flags; 2292 uint32_t ucode_minor; 2293 uint32_t ucode_major; 2294 uint8_t ver_subtype; 2295 uint8_t ver_type; 2296 uint8_t mac; 2297 uint8_t opt; 2298 uint32_t timestamp; 2299 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2300 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2301 uint32_t cpu_register_ptr; 2302 uint32_t dbgm_config_ptr; 2303 uint32_t alive_counter_ptr; 2304 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2305 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2306 uint32_t st_fwrd_size; 2307 uint32_t umac_minor; /* UMAC version: minor */ 2308 uint32_t umac_major; /* UMAC version: major */ 2309 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2310 uint32_t dbg_print_buff_addr; 2311 } __packed; /* ALIVE_RES_API_S_VER_3 */ 2312 2313 /* Error response/notification */ 2314 enum { 2315 IWM_FW_ERR_UNKNOWN_CMD = 0x0, 2316 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1, 2317 IWM_FW_ERR_SERVICE = 0x2, 2318 IWM_FW_ERR_ARC_MEMORY = 0x3, 2319 IWM_FW_ERR_ARC_CODE = 0x4, 2320 IWM_FW_ERR_WATCH_DOG = 0x5, 2321 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10, 2322 IWM_FW_ERR_WEP_KEY_SIZE = 0x11, 2323 IWM_FW_ERR_OBSOLETE_FUNC = 0x12, 2324 IWM_FW_ERR_UNEXPECTED = 0xFE, 2325 IWM_FW_ERR_FATAL = 0xFF 2326 }; 2327 2328 /** 2329 * struct iwm_error_resp - FW error indication 2330 * ( IWM_REPLY_ERROR = 0x2 ) 2331 * @error_type: one of IWM_FW_ERR_* 2332 * @cmd_id: the command ID for which the error occured 2333 * @bad_cmd_seq_num: sequence number of the erroneous command 2334 * @error_service: which service created the error, applicable only if 2335 * error_type = 2, otherwise 0 2336 * @timestamp: TSF in usecs. 2337 */ 2338 struct iwm_error_resp { 2339 uint32_t error_type; 2340 uint8_t cmd_id; 2341 uint8_t reserved1; 2342 uint16_t bad_cmd_seq_num; 2343 uint32_t error_service; 2344 uint64_t timestamp; 2345 } __packed; 2346 2347 2348 /* Common PHY, MAC and Bindings definitions */ 2349 2350 #define IWM_MAX_MACS_IN_BINDING (3) 2351 #define IWM_MAX_BINDINGS (4) 2352 #define IWM_AUX_BINDING_INDEX (3) 2353 #define IWM_MAX_PHYS (4) 2354 2355 /* Used to extract ID and color from the context dword */ 2356 #define IWM_FW_CTXT_ID_POS (0) 2357 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 2358 #define IWM_FW_CTXT_COLOR_POS (8) 2359 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 2360 #define IWM_FW_CTXT_INVALID (0xffffffff) 2361 2362 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 2363 (_color << IWM_FW_CTXT_COLOR_POS)) 2364 2365 /* Possible actions on PHYs, MACs and Bindings */ 2366 enum { 2367 IWM_FW_CTXT_ACTION_STUB = 0, 2368 IWM_FW_CTXT_ACTION_ADD, 2369 IWM_FW_CTXT_ACTION_MODIFY, 2370 IWM_FW_CTXT_ACTION_REMOVE, 2371 IWM_FW_CTXT_ACTION_NUM 2372 }; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2373 2374 /* Time Events */ 2375 2376 /* Time Event types, according to MAC type */ 2377 enum iwm_time_event_type { 2378 /* BSS Station Events */ 2379 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC, 2380 IWM_TE_BSS_STA_ASSOC, 2381 IWM_TE_BSS_EAP_DHCP_PROT, 2382 IWM_TE_BSS_QUIET_PERIOD, 2383 2384 /* P2P Device Events */ 2385 IWM_TE_P2P_DEVICE_DISCOVERABLE, 2386 IWM_TE_P2P_DEVICE_LISTEN, 2387 IWM_TE_P2P_DEVICE_ACTION_SCAN, 2388 IWM_TE_P2P_DEVICE_FULL_SCAN, 2389 2390 /* P2P Client Events */ 2391 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC, 2392 IWM_TE_P2P_CLIENT_ASSOC, 2393 IWM_TE_P2P_CLIENT_QUIET_PERIOD, 2394 2395 /* P2P GO Events */ 2396 IWM_TE_P2P_GO_ASSOC_PROT, 2397 IWM_TE_P2P_GO_REPETITIVE_NOA, 2398 IWM_TE_P2P_GO_CT_WINDOW, 2399 2400 /* WiDi Sync Events */ 2401 IWM_TE_WIDI_TX_SYNC, 2402 2403 IWM_TE_MAX 2404 }; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 2405 2406 2407 2408 /* Time event - defines for command API v1 */ 2409 2410 /* 2411 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 2412 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2413 * the first fragment is scheduled. 2414 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 2415 * the first 2 fragments are scheduled. 2416 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2417 * number of fragments are valid. 2418 * 2419 * Other than the constant defined above, specifying a fragmentation value 'x' 2420 * means that the event can be fragmented but only the first 'x' will be 2421 * scheduled. 2422 */ 2423 enum { 2424 IWM_TE_V1_FRAG_NONE = 0, 2425 IWM_TE_V1_FRAG_SINGLE = 1, 2426 IWM_TE_V1_FRAG_DUAL = 2, 2427 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff 2428 }; 2429 2430 /* If a Time Event can be fragmented, this is the max number of fragments */ 2431 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 2432 /* Repeat the time event endlessly (until removed) */ 2433 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 2434 /* If a Time Event has bounded repetitions, this is the maximal value */ 2435 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 2436 2437 /* Time Event dependencies: none, on another TE, or in a specific time */ 2438 enum { 2439 IWM_TE_V1_INDEPENDENT = 0, 2440 IWM_TE_V1_DEP_OTHER = (1 << 0), 2441 IWM_TE_V1_DEP_TSF = (1 << 1), 2442 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2), 2443 }; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 2444 2445 /* 2446 * @IWM_TE_V1_NOTIF_NONE: no notifications 2447 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 2448 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 2449 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 2450 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 2451 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2452 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2453 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 2454 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 2455 * 2456 * Supported Time event notifications configuration. 2457 * A notification (both event and fragment) includes a status indicating weather 2458 * the FW was able to schedule the event or not. For fragment start/end 2459 * notification the status is always success. There is no start/end fragment 2460 * notification for monolithic events. 2461 */ 2462 enum { 2463 IWM_TE_V1_NOTIF_NONE = 0, 2464 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0), 2465 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1), 2466 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2467 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2468 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4), 2469 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5), 2470 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2471 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2472 }; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2473 2474 2475 /** 2476 * struct iwm_time_event_cmd_api_v1 - configuring Time Events 2477 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 (see also 2478 * with version 2. determined by IWM_UCODE_TLV_FLAGS) 2479 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2480 * @id_and_color: ID and color of the relevant MAC 2481 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2482 * @id: this field has two meanings, depending on the action: 2483 * If the action is ADD, then it means the type of event to add. 2484 * For all other actions it is the unique event ID assigned when the 2485 * event was added by the FW. 2486 * @apply_time: When to start the Time Event (in GP2) 2487 * @max_delay: maximum delay to event's start (apply time), in TU 2488 * @depends_on: the unique ID of the event we depend on (if any) 2489 * @interval: interval between repetitions, in TU 2490 * @interval_reciprocal: 2^32 / interval 2491 * @duration: duration of event in TU 2492 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2493 * @dep_policy: one of IWM_TE_V1_INDEPENDENT, IWM_TE_V1_DEP_OTHER, IWM_TE_V1_DEP_TSF 2494 * and IWM_TE_V1_EVENT_SOCIOPATHIC 2495 * @is_present: 0 or 1, are we present or absent during the Time Event 2496 * @max_frags: maximal number of fragments the Time Event can be divided to 2497 * @notify: notifications using IWM_TE_V1_NOTIF_* (whom to notify when) 2498 */ 2499 struct iwm_time_event_cmd_v1 { 2500 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2501 uint32_t id_and_color; 2502 uint32_t action; 2503 uint32_t id; 2504 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 */ 2505 uint32_t apply_time; 2506 uint32_t max_delay; 2507 uint32_t dep_policy; 2508 uint32_t depends_on; 2509 uint32_t is_present; 2510 uint32_t max_frags; 2511 uint32_t interval; 2512 uint32_t interval_reciprocal; 2513 uint32_t duration; 2514 uint32_t repeat; 2515 uint32_t notify; 2516 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_1 */ 2517 2518 2519 /* Time event - defines for command API v2 */ 2520 2521 /** 2522 * DOC: Time Events - what is it? 2523 * 2524 * Time Events are a fw feature that allows the driver to control the presence 2525 * of the device on the channel. Since the fw supports multiple channels 2526 * concurrently, the fw may choose to jump to another channel at any time. 2527 * In order to make sure that the fw is on a specific channel at a certain time 2528 * and for a certain duration, the driver needs to issue a time event. 2529 * 2530 * The simplest example is for BSS association. The driver issues a time event, 2531 * waits for it to start, and only then tells mac80211 that we can start the 2532 * association. This way, we make sure that the association will be done 2533 * smoothly and won't be interrupted by channel switch decided within the fw. 2534 */ 2535 2536 /** 2537 * DOC: The flow against the fw 2538 * 2539 * When the driver needs to make sure we are in a certain channel, at a certain 2540 * time and for a certain duration, it sends a Time Event. The flow against the 2541 * fw goes like this: 2542 * 1) Driver sends a TIME_EVENT_CMD to the fw 2543 * 2) Driver gets the response for that command. This response contains the 2544 * Unique ID (UID) of the event. 2545 * 3) The fw sends notification when the event starts. 2546 * 2547 * Of course the API provides various options that allow to cover parameters 2548 * of the flow. 2549 * What is the duration of the event? 2550 * What is the start time of the event? 2551 * Is there an end-time for the event? 2552 * How much can the event be delayed? 2553 * Can the event be split? 2554 * If yes what is the maximal number of chunks? 2555 * etc... 2556 */ 2557 2558 /* 2559 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2560 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2561 * the first fragment is scheduled. 2562 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2563 * the first 2 fragments are scheduled. 2564 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2565 * number of fragments are valid. 2566 * 2567 * Other than the constant defined above, specifying a fragmentation value 'x' 2568 * means that the event can be fragmented but only the first 'x' will be 2569 * scheduled. 2570 */ 2571 enum { 2572 IWM_TE_V2_FRAG_NONE = 0, 2573 IWM_TE_V2_FRAG_SINGLE = 1, 2574 IWM_TE_V2_FRAG_DUAL = 2, 2575 IWM_TE_V2_FRAG_MAX = 0xfe, 2576 IWM_TE_V2_FRAG_ENDLESS = 0xff 2577 }; 2578 2579 /* Repeat the time event endlessly (until removed) */ 2580 #define IWM_TE_V2_REPEAT_ENDLESS 0xff 2581 /* If a Time Event has bounded repetitions, this is the maximal value */ 2582 #define IWM_TE_V2_REPEAT_MAX 0xfe 2583 2584 #define IWM_TE_V2_PLACEMENT_POS 12 2585 #define IWM_TE_V2_ABSENCE_POS 15 2586 2587 /* Time event policy values (for time event cmd api v2) 2588 * A notification (both event and fragment) includes a status indicating weather 2589 * the FW was able to schedule the event or not. For fragment start/end 2590 * notification the status is always success. There is no start/end fragment 2591 * notification for monolithic events. 2592 * 2593 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unnoticeable 2594 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2595 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2596 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2597 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2598 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2599 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2600 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2601 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2602 * @IWM_TE_V2_DEP_OTHER: depends on another time event 2603 * @IWM_TE_V2_DEP_TSF: depends on a specific time 2604 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2605 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2606 */ 2607 enum { 2608 IWM_TE_V2_DEFAULT_POLICY = 0x0, 2609 2610 /* notifications (event start/stop, fragment start/stop) */ 2611 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0), 2612 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1), 2613 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2614 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2615 2616 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4), 2617 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5), 2618 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2619 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2620 IWM_T2_V2_START_IMMEDIATELY = (1 << 11), 2621 2622 IWM_TE_V2_NOTIF_MSK = 0xff, 2623 2624 /* placement characteristics */ 2625 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS), 2626 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)), 2627 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)), 2628 2629 /* are we present or absent during the Time Event. */ 2630 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS), 2631 }; 2632 2633 /** 2634 * struct iwm_time_event_cmd_api_v2 - configuring Time Events 2635 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2636 * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2637 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2638 * @id_and_color: ID and color of the relevant MAC 2639 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2640 * @id: this field has two meanings, depending on the action: 2641 * If the action is ADD, then it means the type of event to add. 2642 * For all other actions it is the unique event ID assigned when the 2643 * event was added by the FW. 2644 * @apply_time: When to start the Time Event (in GP2) 2645 * @max_delay: maximum delay to event's start (apply time), in TU 2646 * @depends_on: the unique ID of the event we depend on (if any) 2647 * @interval: interval between repetitions, in TU 2648 * @duration: duration of event in TU 2649 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2650 * @max_frags: maximal number of fragments the Time Event can be divided to 2651 * @policy: defines whether uCode shall notify the host or other uCode modules 2652 * on event and/or fragment start and/or end 2653 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2654 * IWM_TE_EVENT_SOCIOPATHIC 2655 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2656 */ 2657 struct iwm_time_event_cmd_v2 { 2658 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2659 uint32_t id_and_color; 2660 uint32_t action; 2661 uint32_t id; 2662 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2663 uint32_t apply_time; 2664 uint32_t max_delay; 2665 uint32_t depends_on; 2666 uint32_t interval; 2667 uint32_t duration; 2668 uint8_t repeat; 2669 uint8_t max_frags; 2670 uint16_t policy; 2671 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2672 2673 /** 2674 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2675 * @status: bit 0 indicates success, all others specify errors 2676 * @id: the Time Event type 2677 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2678 * @id_and_color: ID and color of the relevant MAC 2679 */ 2680 struct iwm_time_event_resp { 2681 uint32_t status; 2682 uint32_t id; 2683 uint32_t unique_id; 2684 uint32_t id_and_color; 2685 } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2686 2687 /** 2688 * struct iwm_time_event_notif - notifications of time event start/stop 2689 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2690 * @timestamp: action timestamp in GP2 2691 * @session_id: session's unique id 2692 * @unique_id: unique id of the Time Event itself 2693 * @id_and_color: ID and color of the relevant MAC 2694 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2695 * @status: true if scheduled, false otherwise (not executed) 2696 */ 2697 struct iwm_time_event_notif { 2698 uint32_t timestamp; 2699 uint32_t session_id; 2700 uint32_t unique_id; 2701 uint32_t id_and_color; 2702 uint32_t action; 2703 uint32_t status; 2704 } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2705 2706 2707 /* Bindings and Time Quota */ 2708 2709 /** 2710 * struct iwm_binding_cmd - configuring bindings 2711 * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2712 * @id_and_color: ID and color of the relevant Binding 2713 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2714 * @macs: array of MAC id and colors which belong to the binding 2715 * @phy: PHY id and color which belongs to the binding 2716 */ 2717 struct iwm_binding_cmd { 2718 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2719 uint32_t id_and_color; 2720 uint32_t action; 2721 /* IWM_BINDING_DATA_API_S_VER_1 */ 2722 uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2723 uint32_t phy; 2724 } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2725 2726 /* The maximal number of fragments in the FW's schedule session */ 2727 #define IWM_MAX_QUOTA 128 2728 2729 /** 2730 * struct iwm_time_quota_data - configuration of time quota per binding 2731 * @id_and_color: ID and color of the relevant Binding 2732 * @quota: absolute time quota in TU. The scheduler will try to divide the 2733 * remainig quota (after Time Events) according to this quota. 2734 * @max_duration: max uninterrupted context duration in TU 2735 */ 2736 struct iwm_time_quota_data { 2737 uint32_t id_and_color; 2738 uint32_t quota; 2739 uint32_t max_duration; 2740 } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 2741 2742 /** 2743 * struct iwm_time_quota_cmd - configuration of time quota between bindings 2744 * ( IWM_TIME_QUOTA_CMD = 0x2c ) 2745 * @quotas: allocations per binding 2746 */ 2747 struct iwm_time_quota_cmd { 2748 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 2749 } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2750 2751 2752 /* PHY context */ 2753 2754 /* Supported bands */ 2755 #define IWM_PHY_BAND_5 (0) 2756 #define IWM_PHY_BAND_24 (1) 2757 2758 /* Supported channel width, vary if there is VHT support */ 2759 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 2760 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 2761 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 2762 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 2763 2764 /* 2765 * Control channel position: 2766 * For legacy set bit means upper channel, otherwise lower. 2767 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2768 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2769 * center_freq 2770 * | 2771 * 40Mhz |_______|_______| 2772 * 80Mhz |_______|_______|_______|_______| 2773 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2774 * code 011 010 001 000 | 100 101 110 111 2775 */ 2776 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2777 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2778 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2779 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2780 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2781 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2782 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2783 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2784 2785 /* 2786 * @band: IWM_PHY_BAND_* 2787 * @channel: channel number 2788 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2789 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2790 */ 2791 struct iwm_fw_channel_info { 2792 uint8_t band; 2793 uint8_t channel; 2794 uint8_t width; 2795 uint8_t ctrl_pos; 2796 } __packed; 2797 2798 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 2799 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 2800 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 2801 #define IWM_PHY_RX_CHAIN_VALID_POS (1) 2802 #define IWM_PHY_RX_CHAIN_VALID_MSK \ 2803 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 2804 #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 2805 #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 2806 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 2807 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2808 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 2809 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 2810 #define IWM_PHY_RX_CHAIN_CNT_POS (10) 2811 #define IWM_PHY_RX_CHAIN_CNT_MSK \ 2812 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 2813 #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 2814 #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 2815 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 2816 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 2817 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 2818 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 2819 2820 /* TODO: fix the value, make it depend on firmware at runtime? */ 2821 #define IWM_NUM_PHY_CTX 3 2822 2823 /* TODO: complete missing documentation */ 2824 /** 2825 * struct iwm_phy_context_cmd - config of the PHY context 2826 * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 2827 * @id_and_color: ID and color of the relevant Binding 2828 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2829 * @apply_time: 0 means immediate apply and context switch. 2830 * other value means apply new params after X usecs 2831 * @tx_param_color: ??? 2832 * @channel_info: 2833 * @txchain_info: ??? 2834 * @rxchain_info: ??? 2835 * @acquisition_data: ??? 2836 * @dsp_cfg_flags: set to 0 2837 */ 2838 struct iwm_phy_context_cmd { 2839 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2840 uint32_t id_and_color; 2841 uint32_t action; 2842 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 2843 uint32_t apply_time; 2844 uint32_t tx_param_color; 2845 struct iwm_fw_channel_info ci; 2846 uint32_t txchain_info; 2847 uint32_t rxchain_info; 2848 uint32_t acquisition_data; 2849 uint32_t dsp_cfg_flags; 2850 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 2851 2852 #define IWM_RX_INFO_PHY_CNT 8 2853 #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 2854 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 2855 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 2856 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 2857 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0 2858 #define IWM_RX_INFO_ENERGY_ANT_B_POS 8 2859 #define IWM_RX_INFO_ENERGY_ANT_C_POS 16 2860 2861 #define IWM_RX_INFO_AGC_IDX 1 2862 #define IWM_RX_INFO_RSSI_AB_IDX 2 2863 #define IWM_OFDM_AGC_A_MSK 0x0000007f 2864 #define IWM_OFDM_AGC_A_POS 0 2865 #define IWM_OFDM_AGC_B_MSK 0x00003f80 2866 #define IWM_OFDM_AGC_B_POS 7 2867 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 2868 #define IWM_OFDM_AGC_CODE_POS 20 2869 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 2870 #define IWM_OFDM_RSSI_A_POS 0 2871 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 2872 #define IWM_OFDM_RSSI_ALLBAND_A_POS 8 2873 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 2874 #define IWM_OFDM_RSSI_B_POS 16 2875 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 2876 #define IWM_OFDM_RSSI_ALLBAND_B_POS 24 2877 2878 /** 2879 * struct iwm_rx_phy_info - phy info 2880 * (IWM_REPLY_RX_PHY_CMD = 0xc0) 2881 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 2882 * @cfg_phy_cnt: configurable DSP phy data byte count 2883 * @stat_id: configurable DSP phy data set ID 2884 * @reserved1: 2885 * @system_timestamp: GP2 at on air rise 2886 * @timestamp: TSF at on air rise 2887 * @beacon_time_stamp: beacon at on-air rise 2888 * @phy_flags: general phy flags: band, modulation, ... 2889 * @channel: channel number 2890 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 2891 * @rate_n_flags: IWM_RATE_MCS_* 2892 * @byte_count: frame's byte-count 2893 * @frame_time: frame's time on the air, based on byte count and frame rate 2894 * calculation 2895 * @mac_active_msk: what MACs were active when the frame was received 2896 * 2897 * Before each Rx, the device sends this data. It contains PHY information 2898 * about the reception of the packet. 2899 */ 2900 struct iwm_rx_phy_info { 2901 uint8_t non_cfg_phy_cnt; 2902 uint8_t cfg_phy_cnt; 2903 uint8_t stat_id; 2904 uint8_t reserved1; 2905 uint32_t system_timestamp; 2906 uint64_t timestamp; 2907 uint32_t beacon_time_stamp; 2908 uint16_t phy_flags; 2909 #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 2910 uint16_t channel; 2911 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 2912 uint32_t rate_n_flags; 2913 uint32_t byte_count; 2914 uint16_t mac_active_msk; 2915 uint16_t frame_time; 2916 } __packed; 2917 2918 struct iwm_rx_mpdu_res_start { 2919 uint16_t byte_count; 2920 uint16_t reserved; 2921 } __packed; 2922 2923 /** 2924 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags 2925 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 2926 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 2927 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 2928 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 2929 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 2930 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 2931 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 2932 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 2933 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 2934 */ 2935 enum iwm_rx_phy_flags { 2936 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0), 2937 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1), 2938 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2), 2939 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3), 2940 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 2941 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 2942 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7), 2943 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8), 2944 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9), 2945 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10), 2946 }; 2947 2948 /** 2949 * enum iwm_mvm_rx_status - written by fw for each Rx packet 2950 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 2951 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 2952 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 2953 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 2954 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 2955 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 2956 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 2957 * in the driver. 2958 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 2959 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 2960 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 2961 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 2962 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 2963 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 2964 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 2965 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 2966 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 2967 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 2968 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 2969 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 2970 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 2971 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 2972 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 2973 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 2974 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 2975 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 2976 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 2977 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 2978 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 2979 */ 2980 enum iwm_mvm_rx_status { 2981 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0), 2982 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1), 2983 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2), 2984 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3), 2985 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4), 2986 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5), 2987 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6), 2988 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7), 2989 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7), 2990 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 2991 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 2992 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 2993 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 2994 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 2995 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 2996 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 2997 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 2998 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11), 2999 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12), 3000 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13), 3001 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14), 3002 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15), 3003 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000), 3004 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000), 3005 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29), 3006 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), 3007 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), 3008 }; 3009 3010 /** 3011 * struct iwm_radio_version_notif - information on the radio version 3012 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 3013 * @radio_flavor: 3014 * @radio_step: 3015 * @radio_dash: 3016 */ 3017 struct iwm_radio_version_notif { 3018 uint32_t radio_flavor; 3019 uint32_t radio_step; 3020 uint32_t radio_dash; 3021 } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 3022 3023 enum iwm_card_state_flags { 3024 IWM_CARD_ENABLED = 0x00, 3025 IWM_HW_CARD_DISABLED = 0x01, 3026 IWM_SW_CARD_DISABLED = 0x02, 3027 IWM_CT_KILL_CARD_DISABLED = 0x04, 3028 IWM_HALT_CARD_DISABLED = 0x08, 3029 IWM_CARD_DISABLED_MSK = 0x0f, 3030 IWM_CARD_IS_RX_ON = 0x10, 3031 }; 3032 3033 /** 3034 * struct iwm_radio_version_notif - information on the radio version 3035 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 3036 * @flags: %iwm_card_state_flags 3037 */ 3038 struct iwm_card_state_notif { 3039 uint32_t flags; 3040 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 3041 3042 /** 3043 * struct iwm_missed_beacons_notif - information on missed beacons 3044 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 3045 * @mac_id: interface ID 3046 * @consec_missed_beacons_since_last_rx: number of consecutive missed 3047 * beacons since last RX. 3048 * @consec_missed_beacons: number of consecutive missed beacons 3049 * @num_expected_beacons: 3050 * @num_recvd_beacons: 3051 */ 3052 struct iwm_missed_beacons_notif { 3053 uint32_t mac_id; 3054 uint32_t consec_missed_beacons_since_last_rx; 3055 uint32_t consec_missed_beacons; 3056 uint32_t num_expected_beacons; 3057 uint32_t num_recvd_beacons; 3058 } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 3059 3060 /** 3061 * struct iwm_mfuart_load_notif - mfuart image version & status 3062 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 ) 3063 * @installed_ver: installed image version 3064 * @external_ver: external image version 3065 * @status: MFUART loading status 3066 * @duration: MFUART loading time 3067 */ 3068 struct iwm_mfuart_load_notif { 3069 uint32_t installed_ver; 3070 uint32_t external_ver; 3071 uint32_t status; 3072 uint32_t duration; 3073 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 3074 3075 /** 3076 * struct iwm_set_calib_default_cmd - set default value for calibration. 3077 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 3078 * @calib_index: the calibration to set value for 3079 * @length: of data 3080 * @data: the value to set for the calibration result 3081 */ 3082 struct iwm_set_calib_default_cmd { 3083 uint16_t calib_index; 3084 uint16_t length; 3085 uint8_t data[0]; 3086 } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 3087 3088 #define IWM_MAX_PORT_ID_NUM 2 3089 #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 3090 3091 /** 3092 * struct iwm_mcast_filter_cmd - configure multicast filter. 3093 * @filter_own: Set 1 to filter out multicast packets sent by station itself 3094 * @port_id: Multicast MAC addresses array specifier. This is a strange way 3095 * to identify network interface adopted in host-device IF. 3096 * It is used by FW as index in array of addresses. This array has 3097 * IWM_MAX_PORT_ID_NUM members. 3098 * @count: Number of MAC addresses in the array 3099 * @pass_all: Set 1 to pass all multicast packets. 3100 * @bssid: current association BSSID. 3101 * @addr_list: Place holder for array of MAC addresses. 3102 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 3103 */ 3104 struct iwm_mcast_filter_cmd { 3105 uint8_t filter_own; 3106 uint8_t port_id; 3107 uint8_t count; 3108 uint8_t pass_all; 3109 uint8_t bssid[6]; 3110 uint8_t reserved[2]; 3111 uint8_t addr_list[0]; 3112 } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 3113 3114 struct iwm_statistics_dbg { 3115 uint32_t burst_check; 3116 uint32_t burst_count; 3117 uint32_t wait_for_silence_timeout_cnt; 3118 uint32_t reserved[3]; 3119 } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 3120 3121 struct iwm_statistics_div { 3122 uint32_t tx_on_a; 3123 uint32_t tx_on_b; 3124 uint32_t exec_time; 3125 uint32_t probe_time; 3126 uint32_t rssi_ant; 3127 uint32_t reserved2; 3128 } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 3129 3130 struct iwm_statistics_general_common { 3131 uint32_t temperature; /* radio temperature */ 3132 uint32_t temperature_m; /* radio voltage */ 3133 struct iwm_statistics_dbg dbg; 3134 uint32_t sleep_time; 3135 uint32_t slots_out; 3136 uint32_t slots_idle; 3137 uint32_t ttl_timestamp; 3138 struct iwm_statistics_div div; 3139 uint32_t rx_enable_counter; 3140 /* 3141 * num_of_sos_states: 3142 * count the number of times we have to re-tune 3143 * in order to get out of bad PHY status 3144 */ 3145 uint32_t num_of_sos_states; 3146 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3147 3148 struct iwm_statistics_rx_non_phy { 3149 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 3150 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 3151 uint32_t non_bssid_frames; /* number of frames with BSSID that 3152 * doesn't belong to the STA BSSID */ 3153 uint32_t filtered_frames; /* count frames that were dumped in the 3154 * filtering process */ 3155 uint32_t non_channel_beacons; /* beacons with our bss id but not on 3156 * our serving channel */ 3157 uint32_t channel_beacons; /* beacons with our bss id and in our 3158 * serving channel */ 3159 uint32_t num_missed_bcon; /* number of missed beacons */ 3160 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 3161 * ADC was in saturation */ 3162 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 3163 * for INA */ 3164 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 3165 uint32_t interference_data_flag; /* flag for interference data 3166 * availability. 1 when data is 3167 * available. */ 3168 uint32_t channel_load; /* counts RX Enable time in uSec */ 3169 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 3170 * and CCK) counter */ 3171 uint32_t beacon_rssi_a; 3172 uint32_t beacon_rssi_b; 3173 uint32_t beacon_rssi_c; 3174 uint32_t beacon_energy_a; 3175 uint32_t beacon_energy_b; 3176 uint32_t beacon_energy_c; 3177 uint32_t num_bt_kills; 3178 uint32_t mac_id; 3179 uint32_t directed_data_mpdu; 3180 } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 3181 3182 struct iwm_statistics_rx_phy { 3183 uint32_t ina_cnt; 3184 uint32_t fina_cnt; 3185 uint32_t plcp_err; 3186 uint32_t crc32_err; 3187 uint32_t overrun_err; 3188 uint32_t early_overrun_err; 3189 uint32_t crc32_good; 3190 uint32_t false_alarm_cnt; 3191 uint32_t fina_sync_err_cnt; 3192 uint32_t sfd_timeout; 3193 uint32_t fina_timeout; 3194 uint32_t unresponded_rts; 3195 uint32_t rxe_frame_limit_overrun; 3196 uint32_t sent_ack_cnt; 3197 uint32_t sent_cts_cnt; 3198 uint32_t sent_ba_rsp_cnt; 3199 uint32_t dsp_self_kill; 3200 uint32_t mh_format_err; 3201 uint32_t re_acq_main_rssi_sum; 3202 uint32_t reserved; 3203 } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 3204 3205 struct iwm_statistics_rx_ht_phy { 3206 uint32_t plcp_err; 3207 uint32_t overrun_err; 3208 uint32_t early_overrun_err; 3209 uint32_t crc32_good; 3210 uint32_t crc32_err; 3211 uint32_t mh_format_err; 3212 uint32_t agg_crc32_good; 3213 uint32_t agg_mpdu_cnt; 3214 uint32_t agg_cnt; 3215 uint32_t unsupport_mcs; 3216 } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 3217 3218 #define IWM_MAX_CHAINS 3 3219 3220 struct iwm_statistics_tx_non_phy_agg { 3221 uint32_t ba_timeout; 3222 uint32_t ba_reschedule_frames; 3223 uint32_t scd_query_agg_frame_cnt; 3224 uint32_t scd_query_no_agg; 3225 uint32_t scd_query_agg; 3226 uint32_t scd_query_mismatch; 3227 uint32_t frame_not_ready; 3228 uint32_t underrun; 3229 uint32_t bt_prio_kill; 3230 uint32_t rx_ba_rsp_cnt; 3231 int8_t txpower[IWM_MAX_CHAINS]; 3232 int8_t reserved; 3233 uint32_t reserved2; 3234 } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 3235 3236 struct iwm_statistics_tx_channel_width { 3237 uint32_t ext_cca_narrow_ch20[1]; 3238 uint32_t ext_cca_narrow_ch40[2]; 3239 uint32_t ext_cca_narrow_ch80[3]; 3240 uint32_t ext_cca_narrow_ch160[4]; 3241 uint32_t last_tx_ch_width_indx; 3242 uint32_t rx_detected_per_ch_width[4]; 3243 uint32_t success_per_ch_width[4]; 3244 uint32_t fail_per_ch_width[4]; 3245 }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3246 3247 struct iwm_statistics_tx { 3248 uint32_t preamble_cnt; 3249 uint32_t rx_detected_cnt; 3250 uint32_t bt_prio_defer_cnt; 3251 uint32_t bt_prio_kill_cnt; 3252 uint32_t few_bytes_cnt; 3253 uint32_t cts_timeout; 3254 uint32_t ack_timeout; 3255 uint32_t expected_ack_cnt; 3256 uint32_t actual_ack_cnt; 3257 uint32_t dump_msdu_cnt; 3258 uint32_t burst_abort_next_frame_mismatch_cnt; 3259 uint32_t burst_abort_missing_next_frame_cnt; 3260 uint32_t cts_timeout_collision; 3261 uint32_t ack_or_ba_timeout_collision; 3262 struct iwm_statistics_tx_non_phy_agg agg; 3263 struct iwm_statistics_tx_channel_width channel_width; 3264 } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 3265 3266 3267 struct iwm_statistics_bt_activity { 3268 uint32_t hi_priority_tx_req_cnt; 3269 uint32_t hi_priority_tx_denied_cnt; 3270 uint32_t lo_priority_tx_req_cnt; 3271 uint32_t lo_priority_tx_denied_cnt; 3272 uint32_t hi_priority_rx_req_cnt; 3273 uint32_t hi_priority_rx_denied_cnt; 3274 uint32_t lo_priority_rx_req_cnt; 3275 uint32_t lo_priority_rx_denied_cnt; 3276 } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3277 3278 struct iwm_statistics_general { 3279 struct iwm_statistics_general_common common; 3280 uint32_t beacon_filtered; 3281 uint32_t missed_beacons; 3282 int8_t beacon_filter_average_energy; 3283 int8_t beacon_filter_reason; 3284 int8_t beacon_filter_current_energy; 3285 int8_t beacon_filter_reserved; 3286 uint32_t beacon_filter_delta_time; 3287 struct iwm_statistics_bt_activity bt_activity; 3288 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3289 3290 struct iwm_statistics_rx { 3291 struct iwm_statistics_rx_phy ofdm; 3292 struct iwm_statistics_rx_phy cck; 3293 struct iwm_statistics_rx_non_phy general; 3294 struct iwm_statistics_rx_ht_phy ofdm_ht; 3295 } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 3296 3297 /* 3298 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3299 * 3300 * By default, uCode issues this notification after receiving a beacon 3301 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3302 * IWM_REPLY_STATISTICS_CMD 0x9c, above. 3303 * 3304 * Statistics counters continue to increment beacon after beacon, but are 3305 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD 3306 * 0x9c with CLEAR_STATS bit set (see above). 3307 * 3308 * uCode also issues this notification during scans. uCode clears statistics 3309 * appropriately so that each notification contains statistics for only the 3310 * one channel that has just been scanned. 3311 */ 3312 3313 struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */ 3314 uint32_t flag; 3315 struct iwm_statistics_rx rx; 3316 struct iwm_statistics_tx tx; 3317 struct iwm_statistics_general general; 3318 } __packed; 3319 3320 /*********************************** 3321 * Smart Fifo API 3322 ***********************************/ 3323 /* Smart Fifo state */ 3324 enum iwm_sf_state { 3325 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */ 3326 IWM_SF_FULL_ON, 3327 IWM_SF_UNINIT, 3328 IWM_SF_INIT_OFF, 3329 IWM_SF_HW_NUM_STATES 3330 }; 3331 3332 /* Smart Fifo possible scenario */ 3333 enum iwm_sf_scenario { 3334 IWM_SF_SCENARIO_SINGLE_UNICAST, 3335 IWM_SF_SCENARIO_AGG_UNICAST, 3336 IWM_SF_SCENARIO_MULTICAST, 3337 IWM_SF_SCENARIO_BA_RESP, 3338 IWM_SF_SCENARIO_TX_RESP, 3339 IWM_SF_NUM_SCENARIO 3340 }; 3341 3342 #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 3343 #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3344 3345 /* smart FIFO default values */ 3346 #define IWM_SF_W_MARK_SISO 4096 3347 #define IWM_SF_W_MARK_MIMO2 8192 3348 #define IWM_SF_W_MARK_MIMO3 6144 3349 #define IWM_SF_W_MARK_LEGACY 4096 3350 #define IWM_SF_W_MARK_SCAN 4096 3351 3352 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3353 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3354 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3355 #define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3356 #define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3357 #define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 mSec */ 3358 #define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3359 #define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3360 #define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3361 #define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3362 #define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3363 3364 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3365 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3366 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3367 #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3368 #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3369 #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3370 #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3371 #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3372 #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3373 #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3374 #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3375 3376 #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3377 3378 #define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3379 3380 /** 3381 * Smart Fifo configuration command. 3382 * @state: smart fifo state, types listed in enum %iwm_sf_state. 3383 * @watermark: Minimum allowed available free space in RXF for transient state. 3384 * @long_delay_timeouts: aging and idle timer values for each scenario 3385 * in long delay state. 3386 * @full_on_timeouts: timer values for each scenario in full on state. 3387 */ 3388 struct iwm_sf_cfg_cmd { 3389 uint32_t state; 3390 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 3391 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3392 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3393 } __packed; /* IWM_SF_CFG_API_S_VER_2 */ 3394 3395 /* 3396 * The first MAC indices (starting from 0) 3397 * are available to the driver, AUX follows 3398 */ 3399 #define IWM_MAC_INDEX_AUX 4 3400 #define IWM_MAC_INDEX_MIN_DRIVER 0 3401 #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 3402 3403 enum iwm_ac { 3404 IWM_AC_BK, 3405 IWM_AC_BE, 3406 IWM_AC_VI, 3407 IWM_AC_VO, 3408 IWM_AC_NUM, 3409 }; 3410 3411 /** 3412 * enum iwm_mac_protection_flags - MAC context flags 3413 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3414 * this will require CCK RTS/CTS2self. 3415 * RTS/CTS will protect full burst time. 3416 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 3417 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3418 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3419 */ 3420 enum iwm_mac_protection_flags { 3421 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3), 3422 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23), 3423 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24), 3424 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30), 3425 }; 3426 3427 #define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 3428 #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3429 3430 /** 3431 * enum iwm_mac_types - Supported MAC types 3432 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 3433 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3434 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3435 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3436 * @IWM_FW_MAC_TYPE_IBSS: IBSS 3437 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3438 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3439 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 3440 * @IWM_FW_MAC_TYPE_GO: P2P GO 3441 * @IWM_FW_MAC_TYPE_TEST: ? 3442 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 3443 */ 3444 enum iwm_mac_types { 3445 IWM_FW_MAC_TYPE_FIRST = 1, 3446 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST, 3447 IWM_FW_MAC_TYPE_LISTENER, 3448 IWM_FW_MAC_TYPE_PIBSS, 3449 IWM_FW_MAC_TYPE_IBSS, 3450 IWM_FW_MAC_TYPE_BSS_STA, 3451 IWM_FW_MAC_TYPE_P2P_DEVICE, 3452 IWM_FW_MAC_TYPE_P2P_STA, 3453 IWM_FW_MAC_TYPE_GO, 3454 IWM_FW_MAC_TYPE_TEST, 3455 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST 3456 }; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3457 3458 /** 3459 * enum iwm_tsf_id - TSF hw timer ID 3460 * @IWM_TSF_ID_A: use TSF A 3461 * @IWM_TSF_ID_B: use TSF B 3462 * @IWM_TSF_ID_C: use TSF C 3463 * @IWM_TSF_ID_D: use TSF D 3464 * @IWM_NUM_TSF_IDS: number of TSF timers available 3465 */ 3466 enum iwm_tsf_id { 3467 IWM_TSF_ID_A = 0, 3468 IWM_TSF_ID_B = 1, 3469 IWM_TSF_ID_C = 2, 3470 IWM_TSF_ID_D = 3, 3471 IWM_NUM_TSF_IDS = 4, 3472 }; /* IWM_TSF_ID_API_E_VER_1 */ 3473 3474 /** 3475 * struct iwm_mac_data_ap - configuration data for AP MAC context 3476 * @beacon_time: beacon transmit time in system time 3477 * @beacon_tsf: beacon transmit time in TSF 3478 * @bi: beacon interval in TU 3479 * @bi_reciprocal: 2^32 / bi 3480 * @dtim_interval: dtim transmit time in TU 3481 * @dtim_reciprocal: 2^32 / dtim_interval 3482 * @mcast_qid: queue ID for multicast traffic 3483 * @beacon_template: beacon template ID 3484 */ 3485 struct iwm_mac_data_ap { 3486 uint32_t beacon_time; 3487 uint64_t beacon_tsf; 3488 uint32_t bi; 3489 uint32_t bi_reciprocal; 3490 uint32_t dtim_interval; 3491 uint32_t dtim_reciprocal; 3492 uint32_t mcast_qid; 3493 uint32_t beacon_template; 3494 } __packed; /* AP_MAC_DATA_API_S_VER_1 */ 3495 3496 /** 3497 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 3498 * @beacon_time: beacon transmit time in system time 3499 * @beacon_tsf: beacon transmit time in TSF 3500 * @bi: beacon interval in TU 3501 * @bi_reciprocal: 2^32 / bi 3502 * @beacon_template: beacon template ID 3503 */ 3504 struct iwm_mac_data_ibss { 3505 uint32_t beacon_time; 3506 uint64_t beacon_tsf; 3507 uint32_t bi; 3508 uint32_t bi_reciprocal; 3509 uint32_t beacon_template; 3510 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3511 3512 /** 3513 * struct iwm_mac_data_sta - configuration data for station MAC context 3514 * @is_assoc: 1 for associated state, 0 otherwise 3515 * @dtim_time: DTIM arrival time in system time 3516 * @dtim_tsf: DTIM arrival time in TSF 3517 * @bi: beacon interval in TU, applicable only when associated 3518 * @bi_reciprocal: 2^32 / bi , applicable only when associated 3519 * @dtim_interval: DTIM interval in TU, applicable only when associated 3520 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3521 * @listen_interval: in beacon intervals, applicable only when associated 3522 * @assoc_id: unique ID assigned by the AP during association 3523 */ 3524 struct iwm_mac_data_sta { 3525 uint32_t is_assoc; 3526 uint32_t dtim_time; 3527 uint64_t dtim_tsf; 3528 uint32_t bi; 3529 uint32_t bi_reciprocal; 3530 uint32_t dtim_interval; 3531 uint32_t dtim_reciprocal; 3532 uint32_t listen_interval; 3533 uint32_t assoc_id; 3534 uint32_t assoc_beacon_arrive_time; 3535 } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3536 3537 /** 3538 * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3539 * @ap: iwm_mac_data_ap struct with most config data 3540 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3541 * 0 indicates that there is no CT window. 3542 * @opp_ps_enabled: indicate that opportunistic PS allowed 3543 */ 3544 struct iwm_mac_data_go { 3545 struct iwm_mac_data_ap ap; 3546 uint32_t ctwin; 3547 uint32_t opp_ps_enabled; 3548 } __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3549 3550 /** 3551 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3552 * @sta: iwm_mac_data_sta struct with most config data 3553 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3554 * 0 indicates that there is no CT window. 3555 */ 3556 struct iwm_mac_data_p2p_sta { 3557 struct iwm_mac_data_sta sta; 3558 uint32_t ctwin; 3559 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3560 3561 /** 3562 * struct iwm_mac_data_pibss - Pseudo IBSS config data 3563 * @stats_interval: interval in TU between statistics notifications to host. 3564 */ 3565 struct iwm_mac_data_pibss { 3566 uint32_t stats_interval; 3567 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3568 3569 /* 3570 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3571 * context. 3572 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3573 * other channels as well. This should be to true only in case that the 3574 * device is discoverable and there is an active GO. Note that setting this 3575 * field when not needed, will increase the number of interrupts and have 3576 * effect on the platform power, as this setting opens the Rx filters on 3577 * all macs. 3578 */ 3579 struct iwm_mac_data_p2p_dev { 3580 uint32_t is_disc_extended; 3581 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3582 3583 /** 3584 * enum iwm_mac_filter_flags - MAC context filter flags 3585 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3586 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3587 * control frames to the host 3588 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3589 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3590 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3591 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3592 * (in station mode when associated) 3593 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3594 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3595 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3596 */ 3597 enum iwm_mac_filter_flags { 3598 IWM_MAC_FILTER_IN_PROMISC = (1 << 0), 3599 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1), 3600 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2), 3601 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3), 3602 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4), 3603 IWM_MAC_FILTER_IN_BEACON = (1 << 6), 3604 IWM_MAC_FILTER_OUT_BCAST = (1 << 8), 3605 IWM_MAC_FILTER_IN_CRC32 = (1 << 11), 3606 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12), 3607 }; 3608 3609 /** 3610 * enum iwm_mac_qos_flags - QoS flags 3611 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 3612 * @IWM_MAC_QOS_FLG_TGN: HT is enabled 3613 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 3614 * 3615 */ 3616 enum iwm_mac_qos_flags { 3617 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0), 3618 IWM_MAC_QOS_FLG_TGN = (1 << 1), 3619 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4), 3620 }; 3621 3622 /** 3623 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 3624 * @cw_min: Contention window, start value in numbers of slots. 3625 * Should be a power-of-2, minus 1. Device's default is 0x0f. 3626 * @cw_max: Contention window, max value in numbers of slots. 3627 * Should be a power-of-2, minus 1. Device's default is 0x3f. 3628 * @aifsn: Number of slots in Arbitration Interframe Space (before 3629 * performing random backoff timing prior to Tx). Device default 1. 3630 * @fifos_mask: FIFOs used by this MAC for this AC 3631 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3632 * 3633 * One instance of this config struct for each of 4 EDCA access categories 3634 * in struct iwm_qosparam_cmd. 3635 * 3636 * Device will automatically increase contention window by (2*CW) + 1 for each 3637 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3638 * value, to cap the CW value. 3639 */ 3640 struct iwm_ac_qos { 3641 uint16_t cw_min; 3642 uint16_t cw_max; 3643 uint8_t aifsn; 3644 uint8_t fifos_mask; 3645 uint16_t edca_txop; 3646 } __packed; /* IWM_AC_QOS_API_S_VER_2 */ 3647 3648 /** 3649 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 3650 * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 3651 * @id_and_color: ID and color of the MAC 3652 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3653 * @mac_type: one of IWM_FW_MAC_TYPE_* 3654 * @tsf_id: TSF HW timer, one of IWM_TSF_ID_* 3655 * @node_addr: MAC address 3656 * @bssid_addr: BSSID 3657 * @cck_rates: basic rates available for CCK 3658 * @ofdm_rates: basic rates available for OFDM 3659 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 3660 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3661 * @short_slot: 0x10 for enabling short slots, 0 otherwise 3662 * @filter_flags: combination of IWM_MAC_FILTER_* 3663 * @qos_flags: from IWM_MAC_QOS_FLG_* 3664 * @ac: one iwm_mac_qos configuration for each AC 3665 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 3666 */ 3667 struct iwm_mac_ctx_cmd { 3668 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3669 uint32_t id_and_color; 3670 uint32_t action; 3671 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3672 uint32_t mac_type; 3673 uint32_t tsf_id; 3674 uint8_t node_addr[6]; 3675 uint16_t reserved_for_node_addr; 3676 uint8_t bssid_addr[6]; 3677 uint16_t reserved_for_bssid_addr; 3678 uint32_t cck_rates; 3679 uint32_t ofdm_rates; 3680 uint32_t protection_flags; 3681 uint32_t cck_short_preamble; 3682 uint32_t short_slot; 3683 uint32_t filter_flags; 3684 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 3685 uint32_t qos_flags; 3686 struct iwm_ac_qos ac[IWM_AC_NUM+1]; 3687 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 3688 union { 3689 struct iwm_mac_data_ap ap; 3690 struct iwm_mac_data_go go; 3691 struct iwm_mac_data_sta sta; 3692 struct iwm_mac_data_p2p_sta p2p_sta; 3693 struct iwm_mac_data_p2p_dev p2p_dev; 3694 struct iwm_mac_data_pibss pibss; 3695 struct iwm_mac_data_ibss ibss; 3696 }; 3697 } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 3698 3699 static __inline uint32_t iwm_reciprocal(uint32_t v) 3700 { 3701 if (!v) 3702 return 0; 3703 return 0xFFFFFFFF / v; 3704 } 3705 3706 #define IWM_NONQOS_SEQ_GET 0x1 3707 #define IWM_NONQOS_SEQ_SET 0x2 3708 struct iwm_nonqos_seq_query_cmd { 3709 uint32_t get_set_flag; 3710 uint32_t mac_id_n_color; 3711 uint16_t value; 3712 uint16_t reserved; 3713 } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 3714 3715 /* Power Management Commands, Responses, Notifications */ 3716 3717 /* Radio LP RX Energy Threshold measured in dBm */ 3718 #define IWM_POWER_LPRX_RSSI_THRESHOLD 75 3719 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 3720 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 3721 3722 /** 3723 * enum iwm_scan_flags - masks for iwm_mac_power_cmd command flags 3724 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3725 * receiver and transmitter. '0' - does not allow. 3726 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 3727 * '1' Driver enables PM (use rest of parameters) 3728 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 3729 * '1' PM could sleep over DTIM till listen Interval. 3730 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 3731 * access categories are both delivery and trigger enabled. 3732 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 3733 * PBW Snoozing enabled 3734 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 3735 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 3736 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 3737 * detection enablement 3738 */ 3739 enum iwm_power_flags { 3740 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3741 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1), 3742 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2), 3743 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5), 3744 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8), 3745 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9), 3746 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11), 3747 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12), 3748 }; 3749 3750 #define IWM_POWER_VEC_SIZE 5 3751 3752 /** 3753 * enum iwm_device_power_flags - masks for device power command flags 3754 * @IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: 3755 * '1' Allow to save power by turning off receiver and transmitter. 3756 * '0' Do not allow. This flag should be always set to '1' unless 3757 * one needs to disable actual power down for debug purposes. 3758 * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: 3759 * '1' CAM (Continuous Active Mode) is set, power management is disabled. 3760 * '0' Power management is enabled, one of the power schemes is applied. 3761 */ 3762 enum iwm_device_power_flags { 3763 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3764 IWM_DEVICE_POWER_FLAGS_CAM_MSK = (1 << 13), 3765 }; 3766 3767 /** 3768 * struct iwm_device_power_cmd - device wide power command. 3769 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 3770 * 3771 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 3772 */ 3773 struct iwm_device_power_cmd { 3774 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3775 uint16_t flags; 3776 uint16_t reserved; 3777 } __packed; 3778 3779 /** 3780 * struct iwm_mac_power_cmd - New power command containing uAPSD support 3781 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 3782 * @id_and_color: MAC contex identifier 3783 * @flags: Power table command flags from POWER_FLAGS_* 3784 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3785 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3786 * set regardless of power scheme or current power state. 3787 * FW use this value also when PM is disabled. 3788 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3789 * PSM transition - legacy PM 3790 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3791 * PSM transition - legacy PM 3792 * @sleep_interval: not in use 3793 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3794 * is set. For example, if it is required to skip over 3795 * one DTIM, this value need to be set to 2 (DTIM periods). 3796 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 3797 * PSM transition - uAPSD 3798 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 3799 * PSM transition - uAPSD 3800 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3801 * Default: 80dbm 3802 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 3803 * @snooze_interval: Maximum time between attempts to retrieve buffered data 3804 * from the AP [msec] 3805 * @snooze_window: A window of time in which PBW snoozing insures that all 3806 * packets received. It is also the minimum time from last 3807 * received unicast RX packet, before client stops snoozing 3808 * for data. [msec] 3809 * @snooze_step: TBD 3810 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 3811 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 3812 * each corresponding AC. 3813 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 3814 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 3815 * values. 3816 * @heavy_tx_thld_packets: TX threshold measured in number of packets 3817 * @heavy_rx_thld_packets: RX threshold measured in number of packets 3818 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 3819 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 3820 * @limited_ps_threshold: 3821 */ 3822 struct iwm_mac_power_cmd { 3823 /* CONTEXT_DESC_API_T_VER_1 */ 3824 uint32_t id_and_color; 3825 3826 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 3827 uint16_t flags; 3828 uint16_t keep_alive_seconds; 3829 uint32_t rx_data_timeout; 3830 uint32_t tx_data_timeout; 3831 uint32_t rx_data_timeout_uapsd; 3832 uint32_t tx_data_timeout_uapsd; 3833 uint8_t lprx_rssi_threshold; 3834 uint8_t skip_dtim_periods; 3835 uint16_t snooze_interval; 3836 uint16_t snooze_window; 3837 uint8_t snooze_step; 3838 uint8_t qndp_tid; 3839 uint8_t uapsd_ac_flags; 3840 uint8_t uapsd_max_sp; 3841 uint8_t heavy_tx_thld_packets; 3842 uint8_t heavy_rx_thld_packets; 3843 uint8_t heavy_tx_thld_percentage; 3844 uint8_t heavy_rx_thld_percentage; 3845 uint8_t limited_ps_threshold; 3846 uint8_t reserved; 3847 } __packed; 3848 3849 #define IWM_DEFAULT_PS_TX_DATA_TIMEOUT (100 * 1000) 3850 #define IWM_DEFAULT_PS_RX_DATA_TIMEOUT (100 * 1000) 3851 3852 /* 3853 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 3854 * associated AP is identified as improperly implementing uAPSD protocol. 3855 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 3856 * @sta_id: index of station in uCode's station table - associated AP ID in 3857 * this context. 3858 */ 3859 struct iwm_uapsd_misbehaving_ap_notif { 3860 uint32_t sta_id; 3861 uint8_t mac_id; 3862 uint8_t reserved[3]; 3863 } __packed; 3864 3865 /** 3866 * struct iwm_beacon_filter_cmd 3867 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 3868 * @id_and_color: MAC contex identifier 3869 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 3870 * to driver if delta in Energy values calculated for this and last 3871 * passed beacon is greater than this threshold. Zero value means that 3872 * the Energy change is ignored for beacon filtering, and beacon will 3873 * not be forced to be sent to driver regardless of this delta. Typical 3874 * energy delta 5dB. 3875 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 3876 * Send beacon to driver if delta in Energy values calculated for this 3877 * and last passed beacon is greater than this threshold. Zero value 3878 * means that the Energy change is ignored for beacon filtering while in 3879 * Roaming state, typical energy delta 1dB. 3880 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 3881 * calculated for current beacon is less than the threshold, use 3882 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 3883 * Threshold. Typical energy threshold is -72dBm. 3884 * @bf_temp_threshold: This threshold determines the type of temperature 3885 * filtering (Slow or Fast) that is selected (Units are in Celsuis): 3886 * If the current temperature is above this threshold - Fast filter 3887 * will be used, If the current temperature is below this threshold - 3888 * Slow filter will be used. 3889 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 3890 * calculated for this and the last passed beacon is greater than this 3891 * threshold. Zero value means that the temperature change is ignored for 3892 * beacon filtering; beacons will not be forced to be sent to driver 3893 * regardless of whether its temerature has been changed. 3894 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 3895 * calculated for this and the last passed beacon is greater than this 3896 * threshold. Zero value means that the temperature change is ignored for 3897 * beacon filtering; beacons will not be forced to be sent to driver 3898 * regardless of whether its temerature has been changed. 3899 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 3900 * @bf_escape_timer: Send beacons to driver if no beacons were passed 3901 * for a specific period of time. Units: Beacons. 3902 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 3903 * for a longer period of time then this escape-timeout. Units: Beacons. 3904 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 3905 */ 3906 struct iwm_beacon_filter_cmd { 3907 uint32_t bf_energy_delta; 3908 uint32_t bf_roaming_energy_delta; 3909 uint32_t bf_roaming_state; 3910 uint32_t bf_temp_threshold; 3911 uint32_t bf_temp_fast_filter; 3912 uint32_t bf_temp_slow_filter; 3913 uint32_t bf_enable_beacon_filter; 3914 uint32_t bf_debug_flag; 3915 uint32_t bf_escape_timer; 3916 uint32_t ba_escape_timer; 3917 uint32_t ba_enable_beacon_abort; 3918 } __packed; 3919 3920 /* Beacon filtering and beacon abort */ 3921 #define IWM_BF_ENERGY_DELTA_DEFAULT 5 3922 #define IWM_BF_ENERGY_DELTA_MAX 255 3923 #define IWM_BF_ENERGY_DELTA_MIN 0 3924 3925 #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 3926 #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 3927 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 3928 3929 #define IWM_BF_ROAMING_STATE_DEFAULT 72 3930 #define IWM_BF_ROAMING_STATE_MAX 255 3931 #define IWM_BF_ROAMING_STATE_MIN 0 3932 3933 #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 3934 #define IWM_BF_TEMP_THRESHOLD_MAX 255 3935 #define IWM_BF_TEMP_THRESHOLD_MIN 0 3936 3937 #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 3938 #define IWM_BF_TEMP_FAST_FILTER_MAX 255 3939 #define IWM_BF_TEMP_FAST_FILTER_MIN 0 3940 3941 #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 3942 #define IWM_BF_TEMP_SLOW_FILTER_MAX 255 3943 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0 3944 3945 #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 3946 3947 #define IWM_BF_DEBUG_FLAG_DEFAULT 0 3948 3949 #define IWM_BF_ESCAPE_TIMER_DEFAULT 50 3950 #define IWM_BF_ESCAPE_TIMER_MAX 1024 3951 #define IWM_BF_ESCAPE_TIMER_MIN 0 3952 3953 #define IWM_BA_ESCAPE_TIMER_DEFAULT 6 3954 #define IWM_BA_ESCAPE_TIMER_D3 9 3955 #define IWM_BA_ESCAPE_TIMER_MAX 1024 3956 #define IWM_BA_ESCAPE_TIMER_MIN 0 3957 3958 #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 3959 3960 #define IWM_BF_CMD_CONFIG_DEFAULTS \ 3961 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 3962 .bf_roaming_energy_delta = \ 3963 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 3964 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 3965 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 3966 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 3967 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 3968 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 3969 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 3970 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 3971 3972 /* uCode API values for HT/VHT bit rates */ 3973 enum { 3974 IWM_RATE_HT_SISO_MCS_0_PLCP = 0, 3975 IWM_RATE_HT_SISO_MCS_1_PLCP = 1, 3976 IWM_RATE_HT_SISO_MCS_2_PLCP = 2, 3977 IWM_RATE_HT_SISO_MCS_3_PLCP = 3, 3978 IWM_RATE_HT_SISO_MCS_4_PLCP = 4, 3979 IWM_RATE_HT_SISO_MCS_5_PLCP = 5, 3980 IWM_RATE_HT_SISO_MCS_6_PLCP = 6, 3981 IWM_RATE_HT_SISO_MCS_7_PLCP = 7, 3982 IWM_RATE_HT_MIMO2_MCS_0_PLCP = 0x8, 3983 IWM_RATE_HT_MIMO2_MCS_1_PLCP = 0x9, 3984 IWM_RATE_HT_MIMO2_MCS_2_PLCP = 0xA, 3985 IWM_RATE_HT_MIMO2_MCS_3_PLCP = 0xB, 3986 IWM_RATE_HT_MIMO2_MCS_4_PLCP = 0xC, 3987 IWM_RATE_HT_MIMO2_MCS_5_PLCP = 0xD, 3988 IWM_RATE_HT_MIMO2_MCS_6_PLCP = 0xE, 3989 IWM_RATE_HT_MIMO2_MCS_7_PLCP = 0xF, 3990 IWM_RATE_VHT_SISO_MCS_0_PLCP = 0, 3991 IWM_RATE_VHT_SISO_MCS_1_PLCP = 1, 3992 IWM_RATE_VHT_SISO_MCS_2_PLCP = 2, 3993 IWM_RATE_VHT_SISO_MCS_3_PLCP = 3, 3994 IWM_RATE_VHT_SISO_MCS_4_PLCP = 4, 3995 IWM_RATE_VHT_SISO_MCS_5_PLCP = 5, 3996 IWM_RATE_VHT_SISO_MCS_6_PLCP = 6, 3997 IWM_RATE_VHT_SISO_MCS_7_PLCP = 7, 3998 IWM_RATE_VHT_SISO_MCS_8_PLCP = 8, 3999 IWM_RATE_VHT_SISO_MCS_9_PLCP = 9, 4000 IWM_RATE_VHT_MIMO2_MCS_0_PLCP = 0x10, 4001 IWM_RATE_VHT_MIMO2_MCS_1_PLCP = 0x11, 4002 IWM_RATE_VHT_MIMO2_MCS_2_PLCP = 0x12, 4003 IWM_RATE_VHT_MIMO2_MCS_3_PLCP = 0x13, 4004 IWM_RATE_VHT_MIMO2_MCS_4_PLCP = 0x14, 4005 IWM_RATE_VHT_MIMO2_MCS_5_PLCP = 0x15, 4006 IWM_RATE_VHT_MIMO2_MCS_6_PLCP = 0x16, 4007 IWM_RATE_VHT_MIMO2_MCS_7_PLCP = 0x17, 4008 IWM_RATE_VHT_MIMO2_MCS_8_PLCP = 0x18, 4009 IWM_RATE_VHT_MIMO2_MCS_9_PLCP = 0x19, 4010 IWM_RATE_HT_SISO_MCS_INV_PLCP, 4011 IWM_RATE_HT_MIMO2_MCS_INV_PLCP = IWM_RATE_HT_SISO_MCS_INV_PLCP, 4012 IWM_RATE_VHT_SISO_MCS_INV_PLCP = IWM_RATE_HT_SISO_MCS_INV_PLCP, 4013 IWM_RATE_VHT_MIMO2_MCS_INV_PLCP = IWM_RATE_HT_SISO_MCS_INV_PLCP, 4014 IWM_RATE_HT_SISO_MCS_8_PLCP = IWM_RATE_HT_SISO_MCS_INV_PLCP, 4015 IWM_RATE_HT_SISO_MCS_9_PLCP = IWM_RATE_HT_SISO_MCS_INV_PLCP, 4016 IWM_RATE_HT_MIMO2_MCS_8_PLCP = IWM_RATE_HT_SISO_MCS_INV_PLCP, 4017 IWM_RATE_HT_MIMO2_MCS_9_PLCP = IWM_RATE_HT_SISO_MCS_INV_PLCP, 4018 }; 4019 4020 /* 4021 * These serve as indexes into struct iwm_rate iwm_rates[IWM_RIDX_MAX]. 4022 */ 4023 enum { 4024 IWM_RATE_1M_INDEX = 0, 4025 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 4026 IWM_RATE_2M_INDEX, 4027 IWM_RATE_5M_INDEX, 4028 IWM_RATE_11M_INDEX, 4029 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 4030 IWM_RATE_6M_INDEX, 4031 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 4032 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 4033 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 4034 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX, 4035 IWM_RATE_9M_INDEX, 4036 IWM_RATE_12M_INDEX, 4037 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 4038 IWM_RATE_18M_INDEX, 4039 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 4040 IWM_RATE_24M_INDEX, 4041 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 4042 IWM_RATE_36M_INDEX, 4043 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 4044 IWM_RATE_48M_INDEX, 4045 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 4046 IWM_RATE_54M_INDEX, 4047 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 4048 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 4049 IWM_RATE_60M_INDEX, 4050 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX, 4051 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX, 4052 IWM_RATE_MCS_8_INDEX, 4053 IWM_RATE_MCS_9_INDEX, 4054 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX, 4055 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 4056 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1, 4057 }; 4058 4059 #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 4060 4061 /* fw API values for legacy bit rates, both OFDM and CCK */ 4062 enum { 4063 IWM_RATE_6M_PLCP = 13, 4064 IWM_RATE_9M_PLCP = 15, 4065 IWM_RATE_12M_PLCP = 5, 4066 IWM_RATE_18M_PLCP = 7, 4067 IWM_RATE_24M_PLCP = 9, 4068 IWM_RATE_36M_PLCP = 11, 4069 IWM_RATE_48M_PLCP = 1, 4070 IWM_RATE_54M_PLCP = 3, 4071 IWM_RATE_1M_PLCP = 10, 4072 IWM_RATE_2M_PLCP = 20, 4073 IWM_RATE_5M_PLCP = 55, 4074 IWM_RATE_11M_PLCP = 110, 4075 IWM_RATE_INVM_PLCP = 0xff, 4076 }; 4077 4078 /* 4079 * rate_n_flags bit fields 4080 * 4081 * The 32-bit value has different layouts in the low 8 bites depending on the 4082 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 4083 * for CCK and OFDM). 4084 * 4085 * High-throughput (HT) rate format 4086 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 4087 * Very High-throughput (VHT) rate format 4088 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 4089 * Legacy OFDM rate format for bits 7:0 4090 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 4091 * Legacy CCK rate format for bits 7:0: 4092 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 4093 */ 4094 4095 /* Bit 8: (1) HT format, (0) legacy or VHT format */ 4096 #define IWM_RATE_MCS_HT_POS 8 4097 #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 4098 4099 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 4100 #define IWM_RATE_MCS_CCK_POS 9 4101 #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 4102 4103 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 4104 #define IWM_RATE_MCS_VHT_POS 26 4105 #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 4106 4107 4108 /* 4109 * High-throughput (HT) rate format for bits 7:0 4110 * 4111 * 2-0: MCS rate base 4112 * 0) 6 Mbps 4113 * 1) 12 Mbps 4114 * 2) 18 Mbps 4115 * 3) 24 Mbps 4116 * 4) 36 Mbps 4117 * 5) 48 Mbps 4118 * 6) 54 Mbps 4119 * 7) 60 Mbps 4120 * 4-3: 0) Single stream (SISO) 4121 * 1) Dual stream (MIMO) 4122 * 2) Triple stream (MIMO) 4123 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 4124 * (bits 7-6 are zero) 4125 * 4126 * Together the low 5 bits work out to the MCS index because we don't 4127 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 4128 * streams and 16-23 have three streams. We could also support MCS 32 4129 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 4130 */ 4131 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 4132 #define IWM_RATE_HT_MCS_NSS_POS 3 4133 #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 4134 4135 /* Bit 10: (1) Use Green Field preamble */ 4136 #define IWM_RATE_HT_MCS_GF_POS 10 4137 #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 4138 4139 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 4140 4141 /* 4142 * Very High-throughput (VHT) rate format for bits 7:0 4143 * 4144 * 3-0: VHT MCS (0-9) 4145 * 5-4: number of streams - 1: 4146 * 0) Single stream (SISO) 4147 * 1) Dual stream (MIMO) 4148 * 2) Triple stream (MIMO) 4149 */ 4150 4151 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 4152 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 4153 #define IWM_RATE_VHT_MCS_NSS_POS 4 4154 #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 4155 4156 /* 4157 * Legacy OFDM rate format for bits 7:0 4158 * 4159 * 3-0: 0xD) 6 Mbps 4160 * 0xF) 9 Mbps 4161 * 0x5) 12 Mbps 4162 * 0x7) 18 Mbps 4163 * 0x9) 24 Mbps 4164 * 0xB) 36 Mbps 4165 * 0x1) 48 Mbps 4166 * 0x3) 54 Mbps 4167 * (bits 7-4 are 0) 4168 * 4169 * Legacy CCK rate format for bits 7:0: 4170 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 4171 * 4172 * 6-0: 10) 1 Mbps 4173 * 20) 2 Mbps 4174 * 55) 5.5 Mbps 4175 * 110) 11 Mbps 4176 * (bit 7 is 0) 4177 */ 4178 #define IWM_RATE_LEGACY_RATE_MSK 0xff 4179 4180 4181 /* 4182 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 4183 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 4184 */ 4185 #define IWM_RATE_MCS_CHAN_WIDTH_POS 11 4186 #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4187 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4188 #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4189 #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4190 #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4191 4192 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 4193 #define IWM_RATE_MCS_SGI_POS 13 4194 #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 4195 4196 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 4197 #define IWM_RATE_MCS_ANT_POS 14 4198 #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 4199 #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 4200 #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 4201 #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 4202 IWM_RATE_MCS_ANT_B_MSK) 4203 #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 4204 IWM_RATE_MCS_ANT_C_MSK) 4205 #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 4206 #define IWM_RATE_MCS_ANT_NUM 3 4207 4208 /* Bit 17-18: (0) SS, (1) SS*2 */ 4209 #define IWM_RATE_MCS_STBC_POS 17 4210 #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 4211 4212 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 4213 #define IWM_RATE_MCS_BF_POS 19 4214 #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 4215 4216 /* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4217 #define IWM_RATE_MCS_ZLF_POS 20 4218 #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 4219 4220 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4221 #define IWM_RATE_MCS_DUP_POS 24 4222 #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 4223 4224 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4225 #define IWM_RATE_MCS_LDPC_POS 27 4226 #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 4227 4228 4229 /* Link Quality definitions */ 4230 4231 /* # entries in rate scale table to support Tx retries */ 4232 #define IWM_LQ_MAX_RETRY_NUM 16 4233 4234 /* Link quality command flags bit fields */ 4235 4236 /* Bit 0: (0) Don't use RTS (1) Use RTS */ 4237 #define IWM_LQ_FLAG_USE_RTS_POS 0 4238 #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 4239 4240 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4241 #define IWM_LQ_FLAG_COLOR_POS 1 4242 #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 4243 4244 /* Bit 4-5: Tx RTS BW Signalling 4245 * (0) No RTS BW signalling 4246 * (1) Static BW signalling 4247 * (2) Dynamic BW signalling 4248 */ 4249 #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 4250 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4251 #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4252 #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4253 4254 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4255 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 4256 */ 4257 #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 4258 #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 4259 4260 /* Antenna flags. */ 4261 #define IWM_ANT_A (1 << 0) 4262 #define IWM_ANT_B (1 << 1) 4263 #define IWM_ANT_C (1 << 2) 4264 /* Shortcuts. */ 4265 #define IWM_ANT_AB (IWM_ANT_A | IWM_ANT_B) 4266 #define IWM_ANT_BC (IWM_ANT_B | IWM_ANT_C) 4267 #define IWM_ANT_ABC (IWM_ANT_A | IWM_ANT_B | IWM_ANT_C) 4268 4269 /** 4270 * struct iwm_lq_cmd - link quality command 4271 * @sta_id: station to update 4272 * @control: not used 4273 * @flags: combination of IWM_LQ_FLAG_* 4274 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 4275 * and SISO rates 4276 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 4277 * Should be IWM_ANT_[ABC] 4278 * @dual_stream_ant_msk: best antennas for MIMO, combination of IWM_ANT_[ABC] 4279 * @initial_rate_index: first index from rs_table per AC category 4280 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 4281 * value of 100 is one usec. Range is 100 to 8000 4282 * @agg_disable_start_th: try-count threshold for starting aggregation. 4283 * If a frame has higher try-count, it should not be selected for 4284 * starting an aggregation sequence. 4285 * @agg_frame_cnt_limit: max frame count in an aggregation. 4286 * 0: no limit 4287 * 1: no aggregation (one frame per aggregation) 4288 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 4289 * @rs_table: array of rates for each TX try, each is rate_n_flags, 4290 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 4291 * @bf_params: beam forming params, currently not used 4292 */ 4293 struct iwm_lq_cmd { 4294 uint8_t sta_id; 4295 uint8_t reserved1; 4296 uint16_t control; 4297 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 4298 uint8_t flags; 4299 uint8_t mimo_delim; 4300 uint8_t single_stream_ant_msk; 4301 uint8_t dual_stream_ant_msk; 4302 uint8_t initial_rate_index[IWM_AC_NUM]; 4303 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 4304 uint16_t agg_time_limit; 4305 uint8_t agg_disable_start_th; 4306 uint8_t agg_frame_cnt_limit; 4307 uint32_t reserved2; 4308 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 4309 uint32_t bf_params; 4310 }; /* LINK_QUALITY_CMD_API_S_VER_1 */ 4311 4312 /** 4313 * enum iwm_tx_flags - bitmasks for tx_flags in TX command 4314 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4315 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 4316 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4317 * Otherwise, use rate_n_flags from the TX command 4318 * @IWM_TX_CMD_FLG_BA: this frame is a block ack 4319 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4320 * Must set IWM_TX_CMD_FLG_ACK with this flag. 4321 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4322 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4323 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4324 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4325 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4326 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4327 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4328 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4329 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4330 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4331 * Should be set for beacons and probe responses 4332 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4333 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4334 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4335 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4336 * Should be set for 26/30 length MAC headers 4337 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4338 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration 4339 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4340 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4341 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4342 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4343 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4344 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4345 */ 4346 enum iwm_tx_flags { 4347 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0), 4348 IWM_TX_CMD_FLG_ACK = (1 << 3), 4349 IWM_TX_CMD_FLG_STA_RATE = (1 << 4), 4350 IWM_TX_CMD_FLG_BA = (1 << 5), 4351 IWM_TX_CMD_FLG_BAR = (1 << 6), 4352 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7), 4353 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8), 4354 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9), 4355 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10), 4356 IWM_TX_CMD_FLG_BT_DIS = (1 << 12), 4357 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13), 4358 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14), 4359 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15), 4360 IWM_TX_CMD_FLG_TSF = (1 << 16), 4361 IWM_TX_CMD_FLG_CALIB = (1 << 17), 4362 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18), 4363 IWM_TX_CMD_FLG_AGG_START = (1 << 19), 4364 IWM_TX_CMD_FLG_MH_PAD = (1 << 20), 4365 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), 4366 IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22), 4367 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), 4368 IWM_TX_CMD_FLG_DUR = (1 << 25), 4369 IWM_TX_CMD_FLG_FW_DROP = (1 << 26), 4370 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), 4371 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), 4372 IWM_TX_CMD_FLG_HCCA_CHUNK = (1U << 31) 4373 }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 4374 4375 /** 4376 * enum iwm_tx_pm_timeouts - pm timeout values in TX command 4377 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode 4378 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU 4379 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec 4380 */ 4381 enum iwm_tx_pm_timeouts { 4382 IWM_PM_FRAME_NONE = 0, 4383 IWM_PM_FRAME_MGMT = 2, 4384 IWM_PM_FRAME_ASSOC = 3, 4385 }; 4386 4387 /* 4388 * TX command security control 4389 */ 4390 #define IWM_TX_CMD_SEC_WEP 0x01 4391 #define IWM_TX_CMD_SEC_CCM 0x02 4392 #define IWM_TX_CMD_SEC_TKIP 0x03 4393 #define IWM_TX_CMD_SEC_EXT 0x04 4394 #define IWM_TX_CMD_SEC_MSK 0x07 4395 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4396 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4397 #define IWM_TX_CMD_SEC_KEY128 0x08 4398 4399 /* TODO: how does these values are OK with only 16 bit variable??? */ 4400 /* 4401 * TX command next frame info 4402 * 4403 * bits 0:2 - security control (IWM_TX_CMD_SEC_*) 4404 * bit 3 - immediate ACK required 4405 * bit 4 - rate is taken from STA table 4406 * bit 5 - frame belongs to BA stream 4407 * bit 6 - immediate BA response expected 4408 * bit 7 - unused 4409 * bits 8:15 - Station ID 4410 * bits 16:31 - rate 4411 */ 4412 #define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 4413 #define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 4414 #define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 4415 #define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 4416 #define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 4417 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 4418 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 4419 #define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 4420 #define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16) 4421 4422 /* 4423 * TX command Frame life time in us - to be written in pm_frame_timeout 4424 */ 4425 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4426 #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4427 #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4428 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4429 4430 /* 4431 * TID for non QoS frames - to be written in tid_tspec 4432 */ 4433 #define IWM_TID_NON_QOS IWM_MAX_TID_COUNT 4434 4435 /* 4436 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4437 */ 4438 #define IWM_DEFAULT_TX_RETRY 15 4439 #define IWM_MGMT_DFAULT_RETRY_LIMIT 3 4440 #define IWM_RTS_DFAULT_RETRY_LIMIT 60 4441 #define IWM_BAR_DFAULT_RETRY_LIMIT 60 4442 #define IWM_LOW_RETRY_LIMIT 7 4443 4444 /* TODO: complete documentation for try_cnt and btkill_cnt */ 4445 /** 4446 * struct iwm_tx_cmd - TX command struct to FW 4447 * ( IWM_TX_CMD = 0x1c ) 4448 * @len: in bytes of the payload, see below for details 4449 * @next_frame_len: same as len, but for next frame (0 if not applicable) 4450 * Used for fragmentation and bursting, but not in 11n aggregation. 4451 * @tx_flags: combination of IWM_TX_CMD_FLG_* 4452 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 4453 * cleared. Combination of IWM_RATE_MCS_* 4454 * @sta_id: index of destination station in FW station table 4455 * @sec_ctl: security control, IWM_TX_CMD_SEC_* 4456 * @initial_rate_index: index into the rate table for initial TX attempt. 4457 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 4458 * @key: security key 4459 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* 4460 * @life_time: frame life time (usecs??) 4461 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 4462 * btkill_cnd + reserved), first 32 bits. "0" disables usage. 4463 * @dram_msb_ptr: upper bits of the scratch physical address 4464 * @rts_retry_limit: max attempts for RTS 4465 * @data_retry_limit: max attempts to send the data packet 4466 * @tid_spec: TID/tspec 4467 * @pm_frame_timeout: PM TX frame timeout 4468 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 4469 * specified by HCCA protocol 4470 * 4471 * The byte count (both len and next_frame_len) includes MAC header 4472 * (24/26/30/32 bytes) 4473 * + 2 bytes pad if 26/30 header size 4474 * + 8 byte IV for CCM or TKIP (not used for WEP) 4475 * + Data payload 4476 * + 8-byte MIC (not used for CCM/WEP) 4477 * It does not include post-MAC padding, i.e., 4478 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 4479 * Range of len: 14-2342 bytes. 4480 * 4481 * After the struct fields the MAC header is placed, plus any padding, 4482 * and then the actial payload. 4483 */ 4484 struct iwm_tx_cmd { 4485 uint16_t len; 4486 uint16_t next_frame_len; 4487 uint32_t tx_flags; 4488 struct { 4489 uint8_t try_cnt; 4490 uint8_t btkill_cnt; 4491 uint16_t reserved; 4492 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 4493 uint32_t rate_n_flags; 4494 uint8_t sta_id; 4495 uint8_t sec_ctl; 4496 uint8_t initial_rate_index; 4497 uint8_t reserved2; 4498 uint8_t key[16]; 4499 uint16_t next_frame_flags; 4500 uint16_t reserved3; 4501 uint32_t life_time; 4502 uint32_t dram_lsb_ptr; 4503 uint8_t dram_msb_ptr; 4504 uint8_t rts_retry_limit; 4505 uint8_t data_retry_limit; 4506 uint8_t tid_tspec; 4507 uint16_t pm_frame_timeout; 4508 uint16_t driver_txop; 4509 uint8_t payload[0]; 4510 struct ieee80211_frame hdr[0]; 4511 } __packed; /* IWM_TX_CMD_API_S_VER_3 */ 4512 4513 /* 4514 * TX response related data 4515 */ 4516 4517 /* 4518 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx 4519 * @IWM_TX_STATUS_SUCCESS: 4520 * @IWM_TX_STATUS_DIRECT_DONE: 4521 * @IWM_TX_STATUS_POSTPONE_DELAY: 4522 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES: 4523 * @IWM_TX_STATUS_POSTPONE_BT_PRIO: 4524 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD: 4525 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK: 4526 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY: 4527 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT: 4528 * @IWM_TX_STATUS_FAIL_LONG_LIMIT: 4529 * @IWM_TX_STATUS_FAIL_UNDERRUN: 4530 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW: 4531 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH: 4532 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 4533 * @IWM_TX_STATUS_FAIL_DEST_PS: 4534 * @IWM_TX_STATUS_FAIL_HOST_ABORTED: 4535 * @IWM_TX_STATUS_FAIL_BT_RETRY: 4536 * @IWM_TX_STATUS_FAIL_STA_INVALID: 4537 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED: 4538 * @IWM_TX_STATUS_FAIL_TID_DISABLE: 4539 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED: 4540 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL: 4541 * @IWM_TX_STATUS_FAIL_FW_DROP: 4542 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4543 * STA table 4544 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT: 4545 * @IWM_TX_MODE_MSK: 4546 * @IWM_TX_MODE_NO_BURST: 4547 * @IWM_TX_MODE_IN_BURST_SEQ: 4548 * @IWM_TX_MODE_FIRST_IN_BURST: 4549 * @IWM_TX_QUEUE_NUM_MSK: 4550 * 4551 * Valid only if frame_count =1 4552 * TODO: complete documentation 4553 */ 4554 enum iwm_tx_status { 4555 IWM_TX_STATUS_MSK = 0x000000ff, 4556 IWM_TX_STATUS_SUCCESS = 0x01, 4557 IWM_TX_STATUS_DIRECT_DONE = 0x02, 4558 /* postpone TX */ 4559 IWM_TX_STATUS_POSTPONE_DELAY = 0x40, 4560 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41, 4561 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42, 4562 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43, 4563 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44, 4564 /* abort TX */ 4565 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81, 4566 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82, 4567 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83, 4568 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84, 4569 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85, 4570 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86, 4571 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87, 4572 IWM_TX_STATUS_FAIL_DEST_PS = 0x88, 4573 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89, 4574 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a, 4575 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b, 4576 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c, 4577 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d, 4578 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e, 4579 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f, 4580 IWM_TX_STATUS_FAIL_FW_DROP = 0x90, 4581 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91, 4582 IWM_TX_STATUS_INTERNAL_ABORT = 0x92, 4583 IWM_TX_MODE_MSK = 0x00000f00, 4584 IWM_TX_MODE_NO_BURST = 0x00000000, 4585 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100, 4586 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200, 4587 IWM_TX_QUEUE_NUM_MSK = 0x0001f000, 4588 IWM_TX_NARROW_BW_MSK = 0x00060000, 4589 IWM_TX_NARROW_BW_1DIV2 = 0x00020000, 4590 IWM_TX_NARROW_BW_1DIV4 = 0x00040000, 4591 IWM_TX_NARROW_BW_1DIV8 = 0x00060000, 4592 }; 4593 4594 /* 4595 * enum iwm_tx_agg_status - TX aggregation status 4596 * @IWM_AGG_TX_STATE_STATUS_MSK: 4597 * @IWM_AGG_TX_STATE_TRANSMITTED: 4598 * @IWM_AGG_TX_STATE_UNDERRUN: 4599 * @IWM_AGG_TX_STATE_BT_PRIO: 4600 * @IWM_AGG_TX_STATE_FEW_BYTES: 4601 * @IWM_AGG_TX_STATE_ABORT: 4602 * @IWM_AGG_TX_STATE_LAST_SENT_TTL: 4603 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT: 4604 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL: 4605 * @IWM_AGG_TX_STATE_SCD_QUERY: 4606 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32: 4607 * @IWM_AGG_TX_STATE_RESPONSE: 4608 * @IWM_AGG_TX_STATE_DUMP_TX: 4609 * @IWM_AGG_TX_STATE_DELAY_TX: 4610 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4611 * occur if tx failed for this frame when it was a member of a previous 4612 * aggregation block). If rate scaling is used, retry count indicates the 4613 * rate table entry used for all frames in the new agg. 4614 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4615 * this frame 4616 * 4617 * TODO: complete documentation 4618 */ 4619 enum iwm_tx_agg_status { 4620 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff, 4621 IWM_AGG_TX_STATE_TRANSMITTED = 0x000, 4622 IWM_AGG_TX_STATE_UNDERRUN = 0x001, 4623 IWM_AGG_TX_STATE_BT_PRIO = 0x002, 4624 IWM_AGG_TX_STATE_FEW_BYTES = 0x004, 4625 IWM_AGG_TX_STATE_ABORT = 0x008, 4626 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010, 4627 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020, 4628 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040, 4629 IWM_AGG_TX_STATE_SCD_QUERY = 0x080, 4630 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100, 4631 IWM_AGG_TX_STATE_RESPONSE = 0x1ff, 4632 IWM_AGG_TX_STATE_DUMP_TX = 0x200, 4633 IWM_AGG_TX_STATE_DELAY_TX = 0x400, 4634 IWM_AGG_TX_STATE_TRY_CNT_POS = 12, 4635 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS, 4636 }; 4637 4638 #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 4639 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4640 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 4641 4642 /* 4643 * The mask below describes a status where we are absolutely sure that the MPDU 4644 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4645 * written the bytes to the TXE, but we know nothing about what the DSP did. 4646 */ 4647 #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 4648 IWM_AGG_TX_STATE_ABORT | \ 4649 IWM_AGG_TX_STATE_SCD_QUERY) 4650 4651 /* 4652 * IWM_REPLY_TX = 0x1c (response) 4653 * 4654 * This response may be in one of two slightly different formats, indicated 4655 * by the frame_count field: 4656 * 4657 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4658 * frame. Multiple attempts, at various bit rates, may have been made for 4659 * this frame. 4660 * 4661 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4662 * frames that used block-acknowledge. All frames were transmitted at 4663 * same rate. Rate scaling may have been used if first frame in this new 4664 * agg block failed in previous agg block(s). 4665 * 4666 * Note that, for aggregation, ACK (block-ack) status is not delivered 4667 * here; block-ack has not been received by the time the device records 4668 * this status. 4669 * This status relates to reasons the tx might have been blocked or aborted 4670 * within the device, rather than whether it was received successfully by 4671 * the destination station. 4672 */ 4673 4674 /** 4675 * struct iwm_agg_tx_status - per packet TX aggregation status 4676 * @status: enum iwm_tx_agg_status 4677 * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4678 */ 4679 struct iwm_agg_tx_status { 4680 uint16_t status; 4681 uint16_t sequence; 4682 } __packed; 4683 4684 /* 4685 * definitions for initial rate index field 4686 * bits [3:0] initial rate index 4687 * bits [6:4] rate table color, used for the initial rate 4688 * bit-7 invalid rate indication 4689 */ 4690 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4691 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4692 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 4693 4694 #define IWM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4695 #define IWM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4696 4697 /** 4698 * struct iwm_tx_resp - notifies that fw is TXing a packet 4699 * ( IWM_REPLY_TX = 0x1c ) 4700 * @frame_count: 1 no aggregation, >1 aggregation 4701 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 4702 * @failure_rts: num of failures due to unsuccessful RTS 4703 * @failure_frame: num failures due to no ACK (unused for agg) 4704 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 4705 * Tx of all the batch. IWM_RATE_MCS_* 4706 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 4707 * for agg: RTS + CTS + aggregation tx time + block-ack time. 4708 * in usec. 4709 * @pa_status: tx power info 4710 * @pa_integ_res_a: tx power info 4711 * @pa_integ_res_b: tx power info 4712 * @pa_integ_res_c: tx power info 4713 * @measurement_req_id: tx power info 4714 * @tfd_info: TFD information set by the FH 4715 * @seq_ctl: sequence control from the Tx cmd 4716 * @byte_cnt: byte count from the Tx cmd 4717 * @tlc_info: TLC rate info 4718 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 4719 * @frame_ctrl: frame control 4720 * @status: for non-agg: frame status IWM_TX_STATUS_* 4721 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 4722 * follow this one, up to frame_count. 4723 * 4724 * After the array of statuses comes the SSN of the SCD. Look at 4725 * %iwm_get_scd_ssn for more details. 4726 */ 4727 struct iwm_tx_resp { 4728 uint8_t frame_count; 4729 uint8_t bt_kill_count; 4730 uint8_t failure_rts; 4731 uint8_t failure_frame; 4732 uint32_t initial_rate; 4733 uint16_t wireless_media_time; 4734 4735 uint8_t pa_status; 4736 uint8_t pa_integ_res_a[3]; 4737 uint8_t pa_integ_res_b[3]; 4738 uint8_t pa_integ_res_c[3]; 4739 uint16_t measurement_req_id; 4740 uint16_t reserved; 4741 4742 uint32_t tfd_info; 4743 uint16_t seq_ctl; 4744 uint16_t byte_cnt; 4745 uint8_t tlc_info; 4746 uint8_t ra_tid; 4747 uint16_t frame_ctrl; 4748 4749 struct iwm_agg_tx_status status; 4750 } __packed; /* IWM_TX_RSP_API_S_VER_3 */ 4751 4752 /** 4753 * struct iwm_ba_notif - notifies about reception of BA 4754 * ( IWM_BA_NOTIF = 0xc5 ) 4755 * @sta_addr_lo32: lower 32 bits of the MAC address 4756 * @sta_addr_hi16: upper 16 bits of the MAC address 4757 * @sta_id: Index of recipient (BA-sending) station in fw's station table 4758 * @tid: tid of the session 4759 * @seq_ctl: 4760 * @bitmap: the bitmap of the BA notification as seen in the air 4761 * @scd_flow: the tx queue this BA relates to 4762 * @scd_ssn: the index of the last contiguously sent packet 4763 * @txed: number of Txed frames in this batch 4764 * @txed_2_done: number of Acked frames in this batch 4765 */ 4766 struct iwm_ba_notif { 4767 uint32_t sta_addr_lo32; 4768 uint16_t sta_addr_hi16; 4769 uint16_t reserved; 4770 4771 uint8_t sta_id; 4772 uint8_t tid; 4773 uint16_t seq_ctl; 4774 uint64_t bitmap; 4775 uint16_t scd_flow; 4776 uint16_t scd_ssn; 4777 uint8_t txed; 4778 uint8_t txed_2_done; 4779 uint16_t reserved1; 4780 } __packed; 4781 4782 /* 4783 * struct iwm_mac_beacon_cmd - beacon template command 4784 * @tx: the tx commands associated with the beacon frame 4785 * @template_id: currently equal to the mac context id of the corresponding 4786 * mac. 4787 * @tim_idx: the offset of the tim IE in the beacon 4788 * @tim_size: the length of the tim IE 4789 * @frame: the template of the beacon frame 4790 */ 4791 struct iwm_mac_beacon_cmd { 4792 struct iwm_tx_cmd tx; 4793 uint32_t template_id; 4794 uint32_t tim_idx; 4795 uint32_t tim_size; 4796 struct ieee80211_frame frame[0]; 4797 } __packed; 4798 4799 struct iwm_beacon_notif { 4800 struct iwm_tx_resp beacon_notify_hdr; 4801 uint64_t tsf; 4802 uint32_t ibss_mgr_status; 4803 } __packed; 4804 4805 /** 4806 * enum iwm_dump_control - dump (flush) control flags 4807 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 4808 * and the TFD queues are empty. 4809 */ 4810 enum iwm_dump_control { 4811 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1), 4812 }; 4813 4814 /** 4815 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 4816 * @queues_ctl: bitmap of queues to flush 4817 * @flush_ctl: control flags 4818 * @reserved: reserved 4819 */ 4820 struct iwm_tx_path_flush_cmd { 4821 uint32_t queues_ctl; 4822 uint16_t flush_ctl; 4823 uint16_t reserved; 4824 } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 4825 4826 /** 4827 * iwm_get_scd_ssn - returns the SSN of the SCD 4828 * @tx_resp: the Tx response from the fw (agg or non-agg) 4829 * 4830 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 4831 * it can't know that everything will go well until the end of the AMPDU, it 4832 * can't know in advance the number of MPDUs that will be sent in the current 4833 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 4834 * Hence, it can't know in advance what the SSN of the SCD will be at the end 4835 * of the batch. This is why the SSN of the SCD is written at the end of the 4836 * whole struct at a variable offset. This function knows how to cope with the 4837 * variable offset and returns the SSN of the SCD. 4838 */ 4839 static __inline uint32_t iwm_get_scd_ssn(struct iwm_tx_resp *tx_resp) 4840 { 4841 return le32_to_cpup((uint32_t *)&tx_resp->status + 4842 tx_resp->frame_count) & 0xfff; 4843 } 4844 4845 /** 4846 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command 4847 * @token: 4848 * @sta_id: station id 4849 * @tid: 4850 * @scd_queue: scheduler queue to confiug 4851 * @enable: 1 queue enable, 0 queue disable 4852 * @aggregate: 1 aggregated queue, 0 otherwise 4853 * @tx_fifo: %enum iwm_tx_fifo 4854 * @window: BA window size 4855 * @ssn: SSN for the BA agreement 4856 */ 4857 struct iwm_scd_txq_cfg_cmd { 4858 uint8_t token; 4859 uint8_t sta_id; 4860 uint8_t tid; 4861 uint8_t scd_queue; 4862 uint8_t enable; 4863 uint8_t aggregate; 4864 uint8_t tx_fifo; 4865 uint8_t window; 4866 uint16_t ssn; 4867 uint16_t reserved; 4868 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 4869 4870 /** 4871 * struct iwm_scd_txq_cfg_rsp 4872 * @token: taken from the command 4873 * @sta_id: station id from the command 4874 * @tid: tid from the command 4875 * @scd_queue: scd_queue from the command 4876 */ 4877 struct iwm_scd_txq_cfg_rsp { 4878 uint8_t token; 4879 uint8_t sta_id; 4880 uint8_t tid; 4881 uint8_t scd_queue; 4882 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 4883 4884 4885 /* Scan Commands, Responses, Notifications */ 4886 4887 /* Masks for iwm_scan_channel.type flags */ 4888 #define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0) 4889 #define IWM_SCAN_CHANNEL_NSSIDS(x) (((1 << (x)) - 1) << 1) 4890 #define IWM_SCAN_CHANNEL_NARROW_BAND (1 << 22) 4891 4892 /* Max number of IEs for direct SSID scans in a command */ 4893 #define IWM_PROBE_OPTION_MAX 20 4894 4895 /** 4896 * struct iwm_scan_channel - entry in IWM_REPLY_SCAN_CMD channel table 4897 * @channel: band is selected by iwm_scan_cmd "flags" field 4898 * @tx_gain: gain for analog radio 4899 * @dsp_atten: gain for DSP 4900 * @active_dwell: dwell time for active scan in TU, typically 5-50 4901 * @passive_dwell: dwell time for passive scan in TU, typically 20-500 4902 * @type: type is broken down to these bits: 4903 * bit 0: 0 = passive, 1 = active 4904 * bits 1-20: SSID direct bit map. If any of these bits is set then 4905 * the corresponding SSID IE is transmitted in probe request 4906 * (bit i adds IE in position i to the probe request) 4907 * bit 22: channel width, 0 = regular, 1 = TGj narrow channel 4908 * 4909 * @iteration_count: 4910 * @iteration_interval: 4911 * This struct is used once for each channel in the scan list. 4912 * Each channel can independently select: 4913 * 1) SSID for directed active scans 4914 * 2) Txpower setting (for rate specified within Tx command) 4915 * 3) How long to stay on-channel (behavior may be modified by quiet_time, 4916 * quiet_plcp_th, good_CRC_th) 4917 * 4918 * To avoid uCode errors, make sure the following are true (see comments 4919 * under struct iwm_scan_cmd about max_out_time and quiet_time): 4920 * 1) If using passive_dwell (i.e. passive_dwell != 0): 4921 * active_dwell <= passive_dwell (< max_out_time if max_out_time != 0) 4922 * 2) quiet_time <= active_dwell 4923 * 3) If restricting off-channel time (i.e. max_out_time !=0): 4924 * passive_dwell < max_out_time 4925 * active_dwell < max_out_time 4926 */ 4927 struct iwm_scan_channel { 4928 uint32_t type; 4929 uint16_t channel; 4930 uint16_t iteration_count; 4931 uint32_t iteration_interval; 4932 uint16_t active_dwell; 4933 uint16_t passive_dwell; 4934 } __packed; /* IWM_SCAN_CHANNEL_CONTROL_API_S_VER_1 */ 4935 4936 /** 4937 * struct iwm_ssid_ie - directed scan network information element 4938 * 4939 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 4940 * selected by "type" bit field in struct iwm_scan_channel; 4941 * each channel may select different ssids from among the 20 entries. 4942 * SSID IEs get transmitted in reverse order of entry. 4943 */ 4944 struct iwm_ssid_ie { 4945 uint8_t id; 4946 uint8_t len; 4947 uint8_t ssid[IEEE80211_NWID_LEN]; 4948 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 4949 4950 /* scan offload */ 4951 #define IWM_MAX_SCAN_CHANNELS 40 4952 #define IWM_SCAN_MAX_BLACKLIST_LEN 64 4953 #define IWM_SCAN_SHORT_BLACKLIST_LEN 16 4954 #define IWM_SCAN_MAX_PROFILES 11 4955 #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 4956 4957 /* Default watchdog (in MS) for scheduled scan iteration */ 4958 #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 4959 4960 #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 4961 #define IWM_CAN_ABORT_STATUS 1 4962 4963 #define IWM_FULL_SCAN_MULTIPLIER 5 4964 #define IWM_FAST_SCHED_SCAN_ITERATIONS 3 4965 #define IWM_MAX_SCHED_SCAN_PLANS 2 4966 4967 /** 4968 * iwm_scan_flags - masks for scan command flags 4969 *@IWM_SCAN_FLAGS_PERIODIC_SCAN: 4970 *@IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX: 4971 *@IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND: 4972 *@IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND: 4973 *@IWM_SCAN_FLAGS_FRAGMENTED_SCAN: 4974 *@IWM_SCAN_FLAGS_PASSIVE2ACTIVE: use active scan on channels that was active 4975 * in the past hour, even if they are marked as passive. 4976 */ 4977 enum iwm_scan_flags { 4978 IWM_SCAN_FLAGS_PERIODIC_SCAN = (1 << 0), 4979 IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX = (1 << 1), 4980 IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND = (1 << 2), 4981 IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND = (1 << 3), 4982 IWM_SCAN_FLAGS_FRAGMENTED_SCAN = (1 << 4), 4983 IWM_SCAN_FLAGS_PASSIVE2ACTIVE = (1 << 5), 4984 }; 4985 4986 /** 4987 * enum iwm_scan_type - Scan types for scan command 4988 * @IWM_SCAN_TYPE_FORCED: 4989 * @IWM_SCAN_TYPE_BACKGROUND: 4990 * @IWM_SCAN_TYPE_OS: 4991 * @IWM_SCAN_TYPE_ROAMING: 4992 * @IWM_SCAN_TYPE_ACTION: 4993 * @IWM_SCAN_TYPE_DISCOVERY: 4994 * @IWM_SCAN_TYPE_DISCOVERY_FORCED: 4995 */ 4996 enum iwm_scan_type { 4997 IWM_SCAN_TYPE_FORCED = 0, 4998 IWM_SCAN_TYPE_BACKGROUND = 1, 4999 IWM_SCAN_TYPE_OS = 2, 5000 IWM_SCAN_TYPE_ROAMING = 3, 5001 IWM_SCAN_TYPE_ACTION = 4, 5002 IWM_SCAN_TYPE_DISCOVERY = 5, 5003 IWM_SCAN_TYPE_DISCOVERY_FORCED = 6, 5004 }; /* IWM_SCAN_ACTIVITY_TYPE_E_VER_1 */ 5005 5006 /* Maximal number of channels to scan */ 5007 #define IWM_MAX_NUM_SCAN_CHANNELS 0x24 5008 5009 /** 5010 * iwm_scan_schedule_lmac - schedule of scan offload 5011 * @delay: delay between iterations, in seconds. 5012 * @iterations: num of scan iterations 5013 * @full_scan_mul: number of partial scans before each full scan 5014 */ 5015 struct iwm_scan_schedule_lmac { 5016 uint16_t delay; 5017 uint8_t iterations; 5018 uint8_t full_scan_mul; 5019 } __packed; /* SCAN_SCHEDULE_API_S */ 5020 5021 /** 5022 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 5023 * @tx_flags: combination of TX_CMD_FLG_* 5024 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 5025 * cleared. Combination of RATE_MCS_* 5026 * @sta_id: index of destination station in FW station table 5027 * @reserved: for alignment and future use 5028 */ 5029 struct iwm_scan_req_tx_cmd { 5030 uint32_t tx_flags; 5031 uint32_t rate_n_flags; 5032 uint8_t sta_id; 5033 uint8_t reserved[3]; 5034 } __packed; 5035 5036 enum iwm_scan_channel_flags_lmac { 5037 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27), 5038 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28), 5039 }; 5040 5041 /** 5042 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 5043 * @flags: bits 1-20: directed scan to i'th ssid 5044 * other bits &enum iwm_scan_channel_flags_lmac 5045 * @channel_number: channel number 1-13 etc 5046 * @iter_count: scan iteration on this channel 5047 * @iter_interval: interval in seconds between iterations on one channel 5048 */ 5049 struct iwm_scan_channel_cfg_lmac { 5050 uint32_t flags; 5051 uint16_t channel_num; 5052 uint16_t iter_count; 5053 uint32_t iter_interval; 5054 } __packed; 5055 5056 /* 5057 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 5058 * @offset: offset in the data block 5059 * @len: length of the segment 5060 */ 5061 struct iwm_scan_probe_segment { 5062 uint16_t offset; 5063 uint16_t len; 5064 } __packed; 5065 5066 /* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 5067 * @mac_header: first (and common) part of the probe 5068 * @band_data: band specific data 5069 * @common_data: last (and common) part of the probe 5070 * @buf: raw data block 5071 */ 5072 struct iwm_scan_probe_req { 5073 struct iwm_scan_probe_segment mac_header; 5074 struct iwm_scan_probe_segment band_data[2]; 5075 struct iwm_scan_probe_segment common_data; 5076 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 5077 } __packed; 5078 5079 enum iwm_scan_channel_flags { 5080 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0), 5081 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1), 5082 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2), 5083 }; 5084 5085 /* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 5086 * @flags: enum iwm_scan_channel_flags 5087 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 5088 * involved. 5089 * 1 - EBS is disabled. 5090 * 2 - every second scan will be full scan(and so on). 5091 */ 5092 struct iwm_scan_channel_opt { 5093 uint16_t flags; 5094 uint16_t non_ebs_ratio; 5095 } __packed; 5096 5097 /** 5098 * iwm_mvm_lmac_scan_flags - LMAC scan flags 5099 * @IWM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses 5100 * without filtering. 5101 * @IWM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels 5102 * @IWM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan 5103 * @IWM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification 5104 * @IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching 5105 * @IWM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented 5106 * @IWM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report 5107 * and DS parameter set IEs into probe requests. 5108 * @IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 5109 * 1, 6 and 11. 5110 * @IWM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches 5111 */ 5112 enum iwm_mvm_lmac_scan_flags { 5113 IWM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0), 5114 IWM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1), 5115 IWM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2), 5116 IWM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3), 5117 IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4), 5118 IWM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5), 5119 IWM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6), 5120 IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7), 5121 IWM_LMAC_SCAN_FLAG_MATCH = (1 << 9), 5122 }; 5123 5124 enum iwm_scan_priority { 5125 IWM_SCAN_PRIORITY_LOW, 5126 IWM_SCAN_PRIORITY_MEDIUM, 5127 IWM_SCAN_PRIORITY_HIGH, 5128 }; 5129 5130 /** 5131 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1 5132 * @reserved1: for alignment and future use 5133 * @channel_num: num of channels to scan 5134 * @active-dwell: dwell time for active channels 5135 * @passive-dwell: dwell time for passive channels 5136 * @fragmented-dwell: dwell time for fragmented passive scan 5137 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases) 5138 * @reserved2: for alignment and future use 5139 * @rx_chain_select: PHY_RX_CHAIN_* flags 5140 * @scan_flags: &enum iwm_lmac_scan_flags 5141 * @max_out_time: max time (in TU) to be out of associated channel 5142 * @suspend_time: pause scan this long (TUs) when returning to service channel 5143 * @flags: RXON flags 5144 * @filter_flags: RXON filter 5145 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz 5146 * @direct_scan: list of SSIDs for directed active scan 5147 * @scan_prio: enum iwm_scan_priority 5148 * @iter_num: number of scan iterations 5149 * @delay: delay in seconds before first iteration 5150 * @schedule: two scheduling plans. The first one is finite, the second one can 5151 * be infinite. 5152 * @channel_opt: channel optimization options, for full and partial scan 5153 * @data: channel configuration and probe request packet. 5154 */ 5155 struct iwm_scan_req_lmac { 5156 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */ 5157 uint32_t reserved1; 5158 uint8_t n_channels; 5159 uint8_t active_dwell; 5160 uint8_t passive_dwell; 5161 uint8_t fragmented_dwell; 5162 uint8_t extended_dwell; 5163 uint8_t reserved2; 5164 uint16_t rx_chain_select; 5165 uint32_t scan_flags; 5166 uint32_t max_out_time; 5167 uint32_t suspend_time; 5168 /* RX_ON_FLAGS_API_S_VER_1 */ 5169 uint32_t flags; 5170 uint32_t filter_flags; 5171 struct iwm_scan_req_tx_cmd tx_cmd[2]; 5172 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5173 uint32_t scan_prio; 5174 /* SCAN_REQ_PERIODIC_PARAMS_API_S */ 5175 uint32_t iter_num; 5176 uint32_t delay; 5177 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5178 struct iwm_scan_channel_opt channel_opt[2]; 5179 uint8_t data[]; 5180 } __packed; 5181 5182 /** 5183 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 5184 * @last_schedule_line: last schedule line executed (fast or regular) 5185 * @last_schedule_iteration: last scan iteration executed before scan abort 5186 * @status: enum iwm_scan_offload_complete_status 5187 * @ebs_status: EBS success status &enum iwm_scan_ebs_status 5188 * @time_after_last_iter; time in seconds elapsed after last iteration 5189 */ 5190 struct iwm_periodic_scan_complete { 5191 uint8_t last_schedule_line; 5192 uint8_t last_schedule_iteration; 5193 uint8_t status; 5194 uint8_t ebs_status; 5195 uint32_t time_after_last_iter; 5196 uint32_t reserved; 5197 } __packed; 5198 5199 /* Response to scan request contains only status with one of these values */ 5200 #define IWM_SCAN_RESPONSE_OK 0x1 5201 #define IWM_SCAN_RESPONSE_ERROR 0x2 5202 5203 /* 5204 * IWM_SCAN_ABORT_CMD = 0x81 5205 * When scan abort is requested, the command has no fields except the common 5206 * header. The response contains only a status with one of these values. 5207 */ 5208 #define IWM_SCAN_ABORT_POSSIBLE 0x1 5209 #define IWM_SCAN_ABORT_IGNORED 0x2 /* no pending scans */ 5210 5211 /* TODO: complete documentation */ 5212 #define IWM_SCAN_OWNER_STATUS 0x1 5213 #define IWM_MEASURE_OWNER_STATUS 0x2 5214 5215 /** 5216 * struct iwm_scan_start_notif - notifies start of scan in the device 5217 * ( IWM_SCAN_START_NOTIFICATION = 0x82 ) 5218 * @tsf_low: TSF timer (lower half) in usecs 5219 * @tsf_high: TSF timer (higher half) in usecs 5220 * @beacon_timer: structured as follows: 5221 * bits 0:19 - beacon interval in usecs 5222 * bits 20:23 - reserved (0) 5223 * bits 24:31 - number of beacons 5224 * @channel: which channel is scanned 5225 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 5226 * @status: one of *_OWNER_STATUS 5227 */ 5228 struct iwm_scan_start_notif { 5229 uint32_t tsf_low; 5230 uint32_t tsf_high; 5231 uint32_t beacon_timer; 5232 uint8_t channel; 5233 uint8_t band; 5234 uint8_t reserved[2]; 5235 uint32_t status; 5236 } __packed; /* IWM_SCAN_START_NTF_API_S_VER_1 */ 5237 5238 /* scan results probe_status first bit indicates success */ 5239 #define IWM_SCAN_PROBE_STATUS_OK 0 5240 #define IWM_SCAN_PROBE_STATUS_TX_FAILED (1 << 0) 5241 /* error statuses combined with TX_FAILED */ 5242 #define IWM_SCAN_PROBE_STATUS_FAIL_TTL (1 << 1) 5243 #define IWM_SCAN_PROBE_STATUS_FAIL_BT (1 << 2) 5244 5245 /* How many statistics are gathered for each channel */ 5246 #define IWM_SCAN_RESULTS_STATISTICS 1 5247 5248 /** 5249 * enum iwm_scan_complete_status - status codes for scan complete notifications 5250 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully 5251 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user 5252 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed 5253 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready 5254 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed 5255 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed 5256 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command 5257 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort 5258 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax 5259 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful 5260 * (not an error!) 5261 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver 5262 * asked for 5263 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events 5264 */ 5265 enum iwm_scan_complete_status { 5266 IWM_SCAN_COMP_STATUS_OK = 0x1, 5267 IWM_SCAN_COMP_STATUS_ABORT = 0x2, 5268 IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3, 5269 IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4, 5270 IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5, 5271 IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6, 5272 IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7, 5273 IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8, 5274 IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9, 5275 IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA, 5276 IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B, 5277 IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C, 5278 }; 5279 5280 /** 5281 * struct iwm_scan_results_notif - scan results for one channel 5282 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 ) 5283 * @channel: which channel the results are from 5284 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 5285 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 5286 * @num_probe_not_sent: # of request that weren't sent due to not enough time 5287 * @duration: duration spent in channel, in usecs 5288 * @statistics: statistics gathered for this channel 5289 */ 5290 struct iwm_scan_results_notif { 5291 uint8_t channel; 5292 uint8_t band; 5293 uint8_t probe_status; 5294 uint8_t num_probe_not_sent; 5295 uint32_t duration; 5296 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS]; 5297 } __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */ 5298 5299 /** 5300 * struct iwm_scan_complete_notif - notifies end of scanning (all channels) 5301 * ( IWM_SCAN_COMPLETE_NOTIFICATION = 0x84 ) 5302 * @scanned_channels: number of channels scanned (and number of valid results) 5303 * @status: one of IWM_SCAN_COMP_STATUS_* 5304 * @bt_status: BT on/off status 5305 * @last_channel: last channel that was scanned 5306 * @tsf_low: TSF timer (lower half) in usecs 5307 * @tsf_high: TSF timer (higher half) in usecs 5308 * @results: all scan results, only "scanned_channels" of them are valid 5309 */ 5310 struct iwm_scan_complete_notif { 5311 uint8_t scanned_channels; 5312 uint8_t status; 5313 uint8_t bt_status; 5314 uint8_t last_channel; 5315 uint32_t tsf_low; 5316 uint32_t tsf_high; 5317 struct iwm_scan_results_notif results[IWM_MAX_NUM_SCAN_CHANNELS]; 5318 } __packed; /* IWM_SCAN_COMPLETE_NTF_API_S_VER_2 */ 5319 5320 enum iwm_scan_framework_client { 5321 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0), 5322 IWM_SCAN_CLIENT_NETDETECT = (1 << 1), 5323 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2), 5324 }; 5325 5326 /** 5327 * struct iwm_scan_offload_cmd - IWM_SCAN_REQUEST_FIXED_PART_API_S_VER_6 5328 * @scan_flags: see enum iwm_scan_flags 5329 * @channel_count: channels in channel list 5330 * @quiet_time: dwell time, in milisiconds, on quiet channel 5331 * @quiet_plcp_th: quiet channel num of packets threshold 5332 * @good_CRC_th: passive to active promotion threshold 5333 * @rx_chain: RXON rx chain. 5334 * @max_out_time: max uSec to be out of assoceated channel 5335 * @suspend_time: pause scan this long when returning to service channel 5336 * @flags: RXON flags 5337 * @filter_flags: RXONfilter 5338 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz. 5339 * @direct_scan: list of SSIDs for directed active scan 5340 * @scan_type: see enum iwm_scan_type. 5341 * @rep_count: repetition count for each scheduled scan iteration. 5342 */ 5343 struct iwm_scan_offload_cmd { 5344 uint16_t len; 5345 uint8_t scan_flags; 5346 uint8_t channel_count; 5347 uint16_t quiet_time; 5348 uint16_t quiet_plcp_th; 5349 uint16_t good_CRC_th; 5350 uint16_t rx_chain; 5351 uint32_t max_out_time; 5352 uint32_t suspend_time; 5353 /* IWM_RX_ON_FLAGS_API_S_VER_1 */ 5354 uint32_t flags; 5355 uint32_t filter_flags; 5356 struct iwm_tx_cmd tx_cmd[2]; 5357 /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 5358 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5359 uint32_t scan_type; 5360 uint32_t rep_count; 5361 } __packed; 5362 5363 enum iwm_scan_offload_channel_flags { 5364 IWM_SCAN_OFFLOAD_CHANNEL_ACTIVE = (1 << 0), 5365 IWM_SCAN_OFFLOAD_CHANNEL_NARROW = (1 << 22), 5366 IWM_SCAN_OFFLOAD_CHANNEL_FULL = (1 << 24), 5367 IWM_SCAN_OFFLOAD_CHANNEL_PARTIAL = (1 << 25), 5368 }; 5369 5370 /** 5371 * iwm_scan_channel_cfg - IWM_SCAN_CHANNEL_CFG_S 5372 * @type: bitmap - see enum iwm_scan_offload_channel_flags. 5373 * 0: passive (0) or active (1) scan. 5374 * 1-20: directed scan to i'th ssid. 5375 * 22: channel width configuration - 1 for narrow. 5376 * 24: full scan. 5377 * 25: partial scan. 5378 * @channel_number: channel number 1-13 etc. 5379 * @iter_count: repetition count for the channel. 5380 * @iter_interval: interval between two iterations on one channel. 5381 * @dwell_time: entry 0 - active scan, entry 1 - passive scan. 5382 */ 5383 struct iwm_scan_channel_cfg { 5384 uint32_t type[IWM_MAX_SCAN_CHANNELS]; 5385 uint16_t channel_number[IWM_MAX_SCAN_CHANNELS]; 5386 uint16_t iter_count[IWM_MAX_SCAN_CHANNELS]; 5387 uint32_t iter_interval[IWM_MAX_SCAN_CHANNELS]; 5388 uint8_t dwell_time[IWM_MAX_SCAN_CHANNELS][2]; 5389 } __packed; 5390 5391 /** 5392 * iwm_scan_offload_cfg - IWM_SCAN_OFFLOAD_CONFIG_API_S 5393 * @scan_cmd: scan command fixed part 5394 * @channel_cfg: scan channel configuration 5395 * @data: probe request frames (one per band) 5396 */ 5397 struct iwm_scan_offload_cfg { 5398 struct iwm_scan_offload_cmd scan_cmd; 5399 struct iwm_scan_channel_cfg channel_cfg; 5400 uint8_t data[0]; 5401 } __packed; 5402 5403 /** 5404 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 5405 * @ssid: MAC address to filter out 5406 * @reported_rssi: AP rssi reported to the host 5407 * @client_bitmap: clients ignore this entry - enum scan_framework_client 5408 */ 5409 struct iwm_scan_offload_blacklist { 5410 uint8_t ssid[ETHER_ADDR_LEN]; 5411 uint8_t reported_rssi; 5412 uint8_t client_bitmap; 5413 } __packed; 5414 5415 enum iwm_scan_offload_network_type { 5416 IWM_NETWORK_TYPE_BSS = 1, 5417 IWM_NETWORK_TYPE_IBSS = 2, 5418 IWM_NETWORK_TYPE_ANY = 3, 5419 }; 5420 5421 enum iwm_scan_offload_band_selection { 5422 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4, 5423 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8, 5424 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc, 5425 }; 5426 5427 /** 5428 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 5429 * @ssid_index: index to ssid list in fixed part 5430 * @unicast_cipher: encryption olgorithm to match - bitmap 5431 * @aut_alg: authentication olgorithm to match - bitmap 5432 * @network_type: enum iwm_scan_offload_network_type 5433 * @band_selection: enum iwm_scan_offload_band_selection 5434 * @client_bitmap: clients waiting for match - enum scan_framework_client 5435 */ 5436 struct iwm_scan_offload_profile { 5437 uint8_t ssid_index; 5438 uint8_t unicast_cipher; 5439 uint8_t auth_alg; 5440 uint8_t network_type; 5441 uint8_t band_selection; 5442 uint8_t client_bitmap; 5443 uint8_t reserved[2]; 5444 } __packed; 5445 5446 /** 5447 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 5448 * @blaclist: AP list to filter off from scan results 5449 * @profiles: profiles to search for match 5450 * @blacklist_len: length of blacklist 5451 * @num_profiles: num of profiles in the list 5452 * @match_notify: clients waiting for match found notification 5453 * @pass_match: clients waiting for the results 5454 * @active_clients: active clients bitmap - enum scan_framework_client 5455 * @any_beacon_notify: clients waiting for match notification without match 5456 */ 5457 struct iwm_scan_offload_profile_cfg { 5458 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 5459 uint8_t blacklist_len; 5460 uint8_t num_profiles; 5461 uint8_t match_notify; 5462 uint8_t pass_match; 5463 uint8_t active_clients; 5464 uint8_t any_beacon_notify; 5465 uint8_t reserved[2]; 5466 } __packed; 5467 5468 /** 5469 * iwm_scan_offload_schedule - schedule of scan offload 5470 * @delay: delay between iterations, in seconds. 5471 * @iterations: num of scan iterations 5472 * @full_scan_mul: number of partial scans before each full scan 5473 */ 5474 struct iwm_scan_offload_schedule { 5475 uint16_t delay; 5476 uint8_t iterations; 5477 uint8_t full_scan_mul; 5478 } __packed; 5479 5480 /* 5481 * iwm_scan_offload_flags 5482 * 5483 * IWM_SCAN_OFFLOAD_FLAG_PASS_ALL: pass all results - no filtering. 5484 * IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL: add cached channels to partial scan. 5485 * IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN: use energy based scan before partial scan 5486 * on A band. 5487 */ 5488 enum iwm_scan_offload_flags { 5489 IWM_SCAN_OFFLOAD_FLAG_PASS_ALL = (1 << 0), 5490 IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL = (1 << 2), 5491 IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN = (1 << 3), 5492 }; 5493 5494 /** 5495 * iwm_scan_offload_req - scan offload request command 5496 * @flags: bitmap - enum iwm_scan_offload_flags. 5497 * @watchdog: maximum scan duration in TU. 5498 * @delay: delay in seconds before first iteration. 5499 * @schedule_line: scan offload schedule, for fast and regular scan. 5500 */ 5501 struct iwm_scan_offload_req { 5502 uint16_t flags; 5503 uint16_t watchdog; 5504 uint16_t delay; 5505 uint16_t reserved; 5506 struct iwm_scan_offload_schedule schedule_line[2]; 5507 } __packed; 5508 5509 enum iwm_scan_offload_compleate_status { 5510 IWM_SCAN_OFFLOAD_COMPLETED = 1, 5511 IWM_SCAN_OFFLOAD_ABORTED = 2, 5512 }; 5513 5514 /** 5515 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels) 5516 * SCAN_COMPLETE_NTF_API_S_VER_3 5517 * @scanned_channels: number of channels scanned (and number of valid results) 5518 * @status: one of SCAN_COMP_STATUS_* 5519 * @bt_status: BT on/off status 5520 * @last_channel: last channel that was scanned 5521 * @tsf_low: TSF timer (lower half) in usecs 5522 * @tsf_high: TSF timer (higher half) in usecs 5523 * @results: an array of scan results, only "scanned_channels" of them are valid 5524 */ 5525 struct iwm_lmac_scan_complete_notif { 5526 uint8_t scanned_channels; 5527 uint8_t status; 5528 uint8_t bt_status; 5529 uint8_t last_channel; 5530 uint32_t tsf_low; 5531 uint32_t tsf_high; 5532 struct iwm_scan_results_notif results[]; 5533 } __packed; 5534 5535 5536 /** 5537 * iwm_scan_offload_complete - IWM_SCAN_OFFLOAD_COMPLETE_NTF_API_S_VER_1 5538 * @last_schedule_line: last schedule line executed (fast or regular) 5539 * @last_schedule_iteration: last scan iteration executed before scan abort 5540 * @status: enum iwm_scan_offload_compleate_status 5541 */ 5542 struct iwm_scan_offload_complete { 5543 uint8_t last_schedule_line; 5544 uint8_t last_schedule_iteration; 5545 uint8_t status; 5546 uint8_t reserved; 5547 } __packed; 5548 5549 /** 5550 * iwm_sched_scan_results - IWM_SCAN_OFFLOAD_MATCH_FOUND_NTF_API_S_VER_1 5551 * @ssid_bitmap: SSIDs indexes found in this iteration 5552 * @client_bitmap: clients that are active and wait for this notification 5553 */ 5554 struct iwm_sched_scan_results { 5555 uint16_t ssid_bitmap; 5556 uint8_t client_bitmap; 5557 uint8_t reserved; 5558 }; 5559 5560 /* UMAC Scan API */ 5561 5562 /* The maximum of either of these cannot exceed 8, because we use an 5563 * 8-bit mask (see IWM_SCAN_MASK). 5564 */ 5565 #define IWM_MAX_UMAC_SCANS 8 5566 #define IWM_MAX_LMAC_SCANS 1 5567 5568 enum iwm_scan_config_flags { 5569 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0), 5570 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1), 5571 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2), 5572 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3), 5573 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8), 5574 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9), 5575 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10), 5576 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11), 5577 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12), 5578 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13), 5579 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14), 5580 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15), 5581 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16), 5582 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17), 5583 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18), 5584 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19), 5585 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20), 5586 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21), 5587 5588 /* Bits 26-31 are for num of channels in channel_array */ 5589 #define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5590 }; 5591 5592 enum iwm_scan_config_rates { 5593 /* OFDM basic rates */ 5594 IWM_SCAN_CONFIG_RATE_6M = (1 << 0), 5595 IWM_SCAN_CONFIG_RATE_9M = (1 << 1), 5596 IWM_SCAN_CONFIG_RATE_12M = (1 << 2), 5597 IWM_SCAN_CONFIG_RATE_18M = (1 << 3), 5598 IWM_SCAN_CONFIG_RATE_24M = (1 << 4), 5599 IWM_SCAN_CONFIG_RATE_36M = (1 << 5), 5600 IWM_SCAN_CONFIG_RATE_48M = (1 << 6), 5601 IWM_SCAN_CONFIG_RATE_54M = (1 << 7), 5602 /* CCK basic rates */ 5603 IWM_SCAN_CONFIG_RATE_1M = (1 << 8), 5604 IWM_SCAN_CONFIG_RATE_2M = (1 << 9), 5605 IWM_SCAN_CONFIG_RATE_5M = (1 << 10), 5606 IWM_SCAN_CONFIG_RATE_11M = (1 << 11), 5607 5608 /* Bits 16-27 are for supported rates */ 5609 #define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5610 }; 5611 5612 enum iwm_channel_flags { 5613 IWM_CHANNEL_FLAG_EBS = (1 << 0), 5614 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1), 5615 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2), 5616 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3), 5617 }; 5618 5619 /** 5620 * struct iwm_scan_config 5621 * @flags: enum scan_config_flags 5622 * @tx_chains: valid_tx antenna - ANT_* definitions 5623 * @rx_chains: valid_rx antenna - ANT_* definitions 5624 * @legacy_rates: default legacy rates - enum scan_config_rates 5625 * @out_of_channel_time: default max out of serving channel time 5626 * @suspend_time: default max suspend time 5627 * @dwell_active: default dwell time for active scan 5628 * @dwell_passive: default dwell time for passive scan 5629 * @dwell_fragmented: default dwell time for fragmented scan 5630 * @dwell_extended: default dwell time for channels 1, 6 and 11 5631 * @mac_addr: default mac address to be used in probes 5632 * @bcast_sta_id: the index of the station in the fw 5633 * @channel_flags: default channel flags - enum iwm_channel_flags 5634 * scan_config_channel_flag 5635 * @channel_array: default supported channels 5636 */ 5637 struct iwm_scan_config { 5638 uint32_t flags; 5639 uint32_t tx_chains; 5640 uint32_t rx_chains; 5641 uint32_t legacy_rates; 5642 uint32_t out_of_channel_time; 5643 uint32_t suspend_time; 5644 uint8_t dwell_active; 5645 uint8_t dwell_passive; 5646 uint8_t dwell_fragmented; 5647 uint8_t dwell_extended; 5648 uint8_t mac_addr[ETHER_ADDR_LEN]; 5649 uint8_t bcast_sta_id; 5650 uint8_t channel_flags; 5651 uint8_t channel_array[]; 5652 } __packed; /* SCAN_CONFIG_DB_CMD_API_S */ 5653 5654 /** 5655 * iwm_umac_scan_flags 5656 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5657 * can be preempted by other scan requests with higher priority. 5658 * The low priority scan will be resumed when the higher proirity scan is 5659 * completed. 5660 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5661 * when scan starts. 5662 */ 5663 enum iwm_umac_scan_flags { 5664 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0), 5665 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1), 5666 }; 5667 5668 enum iwm_umac_scan_uid_offsets { 5669 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0, 5670 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8, 5671 }; 5672 5673 enum iwm_umac_scan_general_flags { 5674 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0), 5675 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1), 5676 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2), 5677 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3), 5678 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4), 5679 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5), 5680 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6), 5681 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7), 5682 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8), 5683 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9), 5684 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10), 5685 }; 5686 5687 /** 5688 * struct iwm_scan_channel_cfg_umac 5689 * @flags: bitmap - 0-19: directed scan to i'th ssid. 5690 * @channel_num: channel number 1-13 etc. 5691 * @iter_count: repetition count for the channel. 5692 * @iter_interval: interval between two scan iterations on one channel. 5693 */ 5694 struct iwm_scan_channel_cfg_umac { 5695 uint32_t flags; 5696 #define IWM_SCAN_CHANNEL_UMAC_NSSIDS(x) ((1 << (x)) - 1) 5697 uint8_t channel_num; 5698 uint8_t iter_count; 5699 uint16_t iter_interval; 5700 } __packed; /* SCAN_CHANNEL_CFG_S_VER2 */ 5701 5702 /** 5703 * struct iwm_scan_umac_schedule 5704 * @interval: interval in seconds between scan iterations 5705 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5706 * @reserved: for alignment and future use 5707 */ 5708 struct iwm_scan_umac_schedule { 5709 uint16_t interval; 5710 uint8_t iter_count; 5711 uint8_t reserved; 5712 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5713 5714 /** 5715 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5716 * parameters following channels configuration array. 5717 * @schedule: two scheduling plans. 5718 * @delay: delay in TUs before starting the first scan iteration 5719 * @reserved: for future use and alignment 5720 * @preq: probe request with IEs blocks 5721 * @direct_scan: list of SSIDs for directed active scan 5722 */ 5723 struct iwm_scan_req_umac_tail { 5724 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5725 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5726 uint16_t delay; 5727 uint16_t reserved; 5728 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5729 struct iwm_scan_probe_req preq; 5730 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5731 } __packed; 5732 5733 /** 5734 * struct iwm_scan_req_umac 5735 * @flags: &enum iwm_umac_scan_flags 5736 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5737 * @ooc_priority: out of channel priority - &enum iwm_scan_priority 5738 * @general_flags: &enum iwm_umac_scan_general_flags 5739 * @extended_dwell: dwell time for channels 1, 6 and 11 5740 * @active_dwell: dwell time for active scan 5741 * @passive_dwell: dwell time for passive scan 5742 * @fragmented_dwell: dwell time for fragmented passive scan 5743 * @max_out_time: max out of serving channel time 5744 * @suspend_time: max suspend time 5745 * @scan_priority: scan internal prioritization &enum iwm_scan_priority 5746 * @channel_flags: &enum iwm_scan_channel_flags 5747 * @n_channels: num of channels in scan request 5748 * @reserved: for future use and alignment 5749 * @data: &struct iwm_scan_channel_cfg_umac and 5750 * &struct iwm_scan_req_umac_tail 5751 */ 5752 struct iwm_scan_req_umac { 5753 uint32_t flags; 5754 uint32_t uid; 5755 uint32_t ooc_priority; 5756 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5757 uint32_t general_flags; 5758 uint8_t extended_dwell; 5759 uint8_t active_dwell; 5760 uint8_t passive_dwell; 5761 uint8_t fragmented_dwell; 5762 uint32_t max_out_time; 5763 uint32_t suspend_time; 5764 uint32_t scan_priority; 5765 /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5766 uint8_t channel_flags; 5767 uint8_t n_channels; 5768 uint16_t reserved; 5769 uint8_t data[]; 5770 } __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5771 5772 /** 5773 * struct iwm_umac_scan_abort 5774 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5775 * @flags: reserved 5776 */ 5777 struct iwm_umac_scan_abort { 5778 uint32_t uid; 5779 uint32_t flags; 5780 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 5781 5782 /** 5783 * struct iwm_umac_scan_complete 5784 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5785 * @last_schedule: last scheduling line 5786 * @last_iter: last scan iteration number 5787 * @scan status: &enum iwm_scan_offload_complete_status 5788 * @ebs_status: &enum iwm_scan_ebs_status 5789 * @time_from_last_iter: time elapsed from last iteration 5790 * @reserved: for future use 5791 */ 5792 struct iwm_umac_scan_complete { 5793 uint32_t uid; 5794 uint8_t last_schedule; 5795 uint8_t last_iter; 5796 uint8_t status; 5797 uint8_t ebs_status; 5798 uint32_t time_from_last_iter; 5799 uint32_t reserved; 5800 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5801 5802 #define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 5803 /** 5804 * struct iwm_scan_offload_profile_match - match information 5805 * @bssid: matched bssid 5806 * @channel: channel where the match occurred 5807 * @energy: 5808 * @matching_feature: 5809 * @matching_channels: bitmap of channels that matched, referencing 5810 * the channels passed in tue scan offload request 5811 */ 5812 struct iwm_scan_offload_profile_match { 5813 uint8_t bssid[ETHER_ADDR_LEN]; 5814 uint16_t reserved; 5815 uint8_t channel; 5816 uint8_t energy; 5817 uint8_t matching_feature; 5818 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 5819 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 5820 5821 /** 5822 * struct iwm_scan_offload_profiles_query - match results query response 5823 * @matched_profiles: bitmap of matched profiles, referencing the 5824 * matches passed in the scan offload request 5825 * @last_scan_age: age of the last offloaded scan 5826 * @n_scans_done: number of offloaded scans done 5827 * @gp2_d0u: GP2 when D0U occurred 5828 * @gp2_invoked: GP2 when scan offload was invoked 5829 * @resume_while_scanning: not used 5830 * @self_recovery: obsolete 5831 * @reserved: reserved 5832 * @matches: array of match information, one for each match 5833 */ 5834 struct iwm_scan_offload_profiles_query { 5835 uint32_t matched_profiles; 5836 uint32_t last_scan_age; 5837 uint32_t n_scans_done; 5838 uint32_t gp2_d0u; 5839 uint32_t gp2_invoked; 5840 uint8_t resume_while_scanning; 5841 uint8_t self_recovery; 5842 uint16_t reserved; 5843 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES]; 5844 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 5845 5846 /** 5847 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration 5848 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5849 * @scanned_channels: number of channels scanned and number of valid elements in 5850 * results array 5851 * @status: one of SCAN_COMP_STATUS_* 5852 * @bt_status: BT on/off status 5853 * @last_channel: last channel that was scanned 5854 * @tsf_low: TSF timer (lower half) in usecs 5855 * @tsf_high: TSF timer (higher half) in usecs 5856 * @results: array of scan results, only "scanned_channels" of them are valid 5857 */ 5858 struct iwm_umac_scan_iter_complete_notif { 5859 uint32_t uid; 5860 uint8_t scanned_channels; 5861 uint8_t status; 5862 uint8_t bt_status; 5863 uint8_t last_channel; 5864 uint32_t tsf_low; 5865 uint32_t tsf_high; 5866 struct iwm_scan_results_notif results[]; 5867 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5868 5869 /* Please keep this enum *SORTED* by hex value. 5870 * Needed for binary search, otherwise a warning will be triggered. 5871 */ 5872 enum iwm_scan_subcmd_ids { 5873 IWM_GSCAN_START_CMD = 0x0, 5874 IWM_GSCAN_STOP_CMD = 0x1, 5875 IWM_GSCAN_SET_HOTLIST_CMD = 0x2, 5876 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3, 5877 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4, 5878 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5, 5879 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD, 5880 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE, 5881 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF, 5882 }; 5883 5884 /* STA API */ 5885 5886 /** 5887 * enum iwm_sta_flags - flags for the ADD_STA host command 5888 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 5889 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 5890 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled 5891 * @IWM_STA_FLG_PS: set if STA is in Power Save 5892 * @IWM_STA_FLG_INVALID: set if STA is invalid 5893 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 5894 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 5895 * @IWM_STA_FLG_DRAIN_FLOW: drain flow 5896 * @IWM_STA_FLG_PAN: STA is for PAN interface 5897 * @IWM_STA_FLG_CLASS_AUTH: 5898 * @IWM_STA_FLG_CLASS_ASSOC: 5899 * @IWM_STA_FLG_CLASS_MIMO_PROT: 5900 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 5901 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 5902 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 5903 * initialised by driver and can be updated by fw upon reception of 5904 * action frames that can change the channel width. When cleared the fw 5905 * will send all the frames in 20MHz even when FAT channel is requested. 5906 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 5907 * driver and can be updated by fw upon reception of action frames. 5908 * @IWM_STA_FLG_MFP_EN: Management Frame Protection 5909 */ 5910 enum iwm_sta_flags { 5911 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3), 5912 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6), 5913 5914 IWM_STA_FLG_DISABLE_TX = (1 << 4), 5915 5916 IWM_STA_FLG_PS = (1 << 8), 5917 IWM_STA_FLG_DRAIN_FLOW = (1 << 12), 5918 IWM_STA_FLG_PAN = (1 << 13), 5919 IWM_STA_FLG_CLASS_AUTH = (1 << 14), 5920 IWM_STA_FLG_CLASS_ASSOC = (1 << 15), 5921 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17), 5922 5923 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19, 5924 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5925 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5926 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5927 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5928 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5929 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5930 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5931 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5932 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5933 5934 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23, 5935 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5936 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5937 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5938 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5939 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5940 5941 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26), 5942 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26), 5943 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26), 5944 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26), 5945 IWM_STA_FLG_FAT_EN_MSK = (3 << 26), 5946 5947 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28), 5948 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28), 5949 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28), 5950 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28), 5951 }; 5952 5953 /** 5954 * enum iwm_sta_key_flag - key flags for the ADD_STA host command 5955 * @IWM_STA_KEY_FLG_NO_ENC: no encryption 5956 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 5957 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 5958 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 5959 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 5960 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 5961 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 5962 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 5963 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 5964 * station info array (1 - n 1X mode) 5965 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 5966 * @IWM_STA_KEY_NOT_VALID: key is invalid 5967 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 5968 * @IWM_STA_KEY_MULTICAST: set for multical key 5969 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 5970 */ 5971 enum iwm_sta_key_flag { 5972 IWM_STA_KEY_FLG_NO_ENC = (0 << 0), 5973 IWM_STA_KEY_FLG_WEP = (1 << 0), 5974 IWM_STA_KEY_FLG_CCM = (2 << 0), 5975 IWM_STA_KEY_FLG_TKIP = (3 << 0), 5976 IWM_STA_KEY_FLG_EXT = (4 << 0), 5977 IWM_STA_KEY_FLG_CMAC = (6 << 0), 5978 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0), 5979 IWM_STA_KEY_FLG_EN_MSK = (7 << 0), 5980 5981 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3), 5982 IWM_STA_KEY_FLG_KEYID_POS = 8, 5983 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS), 5984 IWM_STA_KEY_NOT_VALID = (1 << 11), 5985 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12), 5986 IWM_STA_KEY_MULTICAST = (1 << 14), 5987 IWM_STA_KEY_MFP = (1 << 15), 5988 }; 5989 5990 /** 5991 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed 5992 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 5993 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 5994 * @IWM_STA_MODIFY_TX_RATE: unused 5995 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 5996 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 5997 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 5998 * @IWM_STA_MODIFY_PROT_TH: 5999 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 6000 */ 6001 enum iwm_sta_modify_flag { 6002 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0), 6003 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1), 6004 IWM_STA_MODIFY_TX_RATE = (1 << 2), 6005 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3), 6006 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4), 6007 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5), 6008 IWM_STA_MODIFY_PROT_TH = (1 << 6), 6009 IWM_STA_MODIFY_QUEUES = (1 << 7), 6010 }; 6011 6012 #define IWM_STA_MODE_MODIFY 1 6013 6014 /** 6015 * enum iwm_sta_sleep_flag - type of sleep of the station 6016 * @IWM_STA_SLEEP_STATE_AWAKE: 6017 * @IWM_STA_SLEEP_STATE_PS_POLL: 6018 * @IWM_STA_SLEEP_STATE_UAPSD: 6019 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on 6020 * (last) released frame 6021 */ 6022 enum iwm_sta_sleep_flag { 6023 IWM_STA_SLEEP_STATE_AWAKE = 0, 6024 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0), 6025 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1), 6026 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2), 6027 }; 6028 6029 /* STA ID and color bits definitions */ 6030 #define IWM_STA_ID_SEED (0x0f) 6031 #define IWM_STA_ID_POS (0) 6032 #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 6033 6034 #define IWM_STA_COLOR_SEED (0x7) 6035 #define IWM_STA_COLOR_POS (4) 6036 #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 6037 6038 #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 6039 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 6040 #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 6041 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 6042 6043 #define IWM_STA_KEY_MAX_NUM (16) 6044 #define IWM_STA_KEY_IDX_INVALID (0xff) 6045 #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 6046 #define IWM_MAX_GLOBAL_KEYS (4) 6047 #define IWM_STA_KEY_LEN_WEP40 (5) 6048 #define IWM_STA_KEY_LEN_WEP104 (13) 6049 6050 /** 6051 * struct iwm_keyinfo - key information 6052 * @key_flags: type %iwm_sta_key_flag 6053 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 6054 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 6055 * @key_offset: key offset in the fw's key table 6056 * @key: 16-byte unicast decryption key 6057 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 6058 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 6059 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 6060 */ 6061 struct iwm_keyinfo { 6062 uint16_t key_flags; 6063 uint8_t tkip_rx_tsc_byte2; 6064 uint8_t reserved1; 6065 uint16_t tkip_rx_ttak[5]; 6066 uint8_t key_offset; 6067 uint8_t reserved2; 6068 uint8_t key[16]; 6069 uint64_t tx_secur_seq_cnt; 6070 uint64_t hw_tkip_mic_rx_key; 6071 uint64_t hw_tkip_mic_tx_key; 6072 } __packed; 6073 6074 #define IWM_ADD_STA_STATUS_MASK 0xFF 6075 #define IWM_ADD_STA_BAID_VALID_MASK 0x8000 6076 #define IWM_ADD_STA_BAID_MASK 0x7F00 6077 #define IWM_ADD_STA_BAID_SHIFT 8 6078 6079 /** 6080 * struct iwm_add_sta_cmd_v7 - Add/modify a station in the fw's sta table. 6081 * ( REPLY_ADD_STA = 0x18 ) 6082 * @add_modify: 1: modify existing, 0: add new station 6083 * @awake_acs: 6084 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 6085 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 6086 * @mac_id_n_color: the Mac context this station belongs to 6087 * @addr[ETHER_ADDR_LEN]: station's MAC address 6088 * @sta_id: index of station in uCode's station table 6089 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 6090 * alone. 1 - modify, 0 - don't change. 6091 * @station_flags: look at %iwm_sta_flags 6092 * @station_flags_msk: what of %station_flags have changed 6093 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 6094 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 6095 * add_immediate_ba_ssn. 6096 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 6097 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 6098 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 6099 * add_immediate_ba_tid. 6100 * @sleep_tx_count: number of packets to transmit to station even though it is 6101 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 6102 * keeps track of STA sleep state. 6103 * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 6104 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 6105 * mac-addr. 6106 * @beamform_flags: beam forming controls 6107 * @tfd_queue_msk: tfd queues used by this station 6108 * 6109 * The device contains an internal table of per-station information, with info 6110 * on security keys, aggregation parameters, and Tx rates for initial Tx 6111 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 6112 * 6113 * ADD_STA sets up the table entry for one station, either creating a new 6114 * entry, or modifying a pre-existing one. 6115 */ 6116 struct iwm_add_sta_cmd_v7 { 6117 uint8_t add_modify; 6118 uint8_t awake_acs; 6119 uint16_t tid_disable_tx; 6120 uint32_t mac_id_n_color; 6121 uint8_t addr[ETHER_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 6122 uint16_t reserved2; 6123 uint8_t sta_id; 6124 uint8_t modify_mask; 6125 uint16_t reserved3; 6126 uint32_t station_flags; 6127 uint32_t station_flags_msk; 6128 uint8_t add_immediate_ba_tid; 6129 uint8_t remove_immediate_ba_tid; 6130 uint16_t add_immediate_ba_ssn; 6131 uint16_t sleep_tx_count; 6132 uint16_t sleep_state_flags; 6133 uint16_t assoc_id; 6134 uint16_t beamform_flags; 6135 uint32_t tfd_queue_msk; 6136 } __packed; /* ADD_STA_CMD_API_S_VER_7 */ 6137 6138 /** 6139 * struct iwm_add_sta_key_cmd - add/modify sta key 6140 * ( IWM_REPLY_ADD_STA_KEY = 0x17 ) 6141 * @sta_id: index of station in uCode's station table 6142 * @key_offset: key offset in key storage 6143 * @key_flags: type %iwm_sta_key_flag 6144 * @key: key material data 6145 * @key2: key material data 6146 * @rx_secur_seq_cnt: RX security sequence counter for the key 6147 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 6148 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 6149 */ 6150 struct iwm_add_sta_key_cmd { 6151 uint8_t sta_id; 6152 uint8_t key_offset; 6153 uint16_t key_flags; 6154 uint8_t key[16]; 6155 uint8_t key2[16]; 6156 uint8_t rx_secur_seq_cnt[16]; 6157 uint8_t tkip_rx_tsc_byte2; 6158 uint8_t reserved; 6159 uint16_t tkip_rx_ttak[5]; 6160 } __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */ 6161 6162 /** 6163 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command 6164 * @IWM_ADD_STA_SUCCESS: operation was executed successfully 6165 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 6166 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 6167 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 6168 * that doesn't exist. 6169 */ 6170 enum iwm_mvm_add_sta_rsp_status { 6171 IWM_ADD_STA_SUCCESS = 0x1, 6172 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2, 6173 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4, 6174 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8, 6175 }; 6176 6177 /** 6178 * struct iwm_rm_sta_cmd - Add / modify a station in the fw's station table 6179 * ( IWM_REMOVE_STA = 0x19 ) 6180 * @sta_id: the station id of the station to be removed 6181 */ 6182 struct iwm_rm_sta_cmd { 6183 uint8_t sta_id; 6184 uint8_t reserved[3]; 6185 } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 6186 6187 /** 6188 * struct iwm_mgmt_mcast_key_cmd 6189 * ( IWM_MGMT_MCAST_KEY = 0x1f ) 6190 * @ctrl_flags: %iwm_sta_key_flag 6191 * @IGTK: 6192 * @K1: IGTK master key 6193 * @K2: IGTK sub key 6194 * @sta_id: station ID that support IGTK 6195 * @key_id: 6196 * @receive_seq_cnt: initial RSC/PN needed for replay check 6197 */ 6198 struct iwm_mgmt_mcast_key_cmd { 6199 uint32_t ctrl_flags; 6200 uint8_t IGTK[16]; 6201 uint8_t K1[16]; 6202 uint8_t K2[16]; 6203 uint32_t key_id; 6204 uint32_t sta_id; 6205 uint64_t receive_seq_cnt; 6206 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 6207 6208 struct iwm_wep_key { 6209 uint8_t key_index; 6210 uint8_t key_offset; 6211 uint16_t reserved1; 6212 uint8_t key_size; 6213 uint8_t reserved2[3]; 6214 uint8_t key[16]; 6215 } __packed; 6216 6217 struct iwm_wep_key_cmd { 6218 uint32_t mac_id_n_color; 6219 uint8_t num_keys; 6220 uint8_t decryption_type; 6221 uint8_t flags; 6222 uint8_t reserved; 6223 struct iwm_wep_key wep_key[0]; 6224 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 6225 6226 /* 6227 * BT coex 6228 */ 6229 6230 enum iwm_bt_coex_mode { 6231 IWM_BT_COEX_DISABLE = 0x0, 6232 IWM_BT_COEX_NW = 0x1, 6233 IWM_BT_COEX_BT = 0x2, 6234 IWM_BT_COEX_WIFI = 0x3, 6235 }; /* BT_COEX_MODES_E */ 6236 6237 enum iwm_bt_coex_enabled_modules { 6238 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0), 6239 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1), 6240 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2), 6241 IWM_BT_COEX_CORUN_ENABLED = (1 << 3), 6242 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4), 6243 }; /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 6244 6245 /** 6246 * struct iwm_bt_coex_cmd - bt coex configuration command 6247 * @mode: enum %iwm_bt_coex_mode 6248 * @enabled_modules: enum %iwm_bt_coex_enabled_modules 6249 * 6250 * The structure is used for the BT_COEX command. 6251 */ 6252 struct iwm_bt_coex_cmd { 6253 uint32_t mode; 6254 uint32_t enabled_modules; 6255 } __packed; /* BT_COEX_CMD_API_S_VER_6 */ 6256 6257 6258 /* 6259 * Location Aware Regulatory (LAR) API - MCC updates 6260 */ 6261 6262 /** 6263 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic 6264 * regulatory profile according to the given MCC (Mobile Country Code). 6265 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6266 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6267 * MCC in the cmd response will be the relevant MCC in the NVM. 6268 * @mcc: given mobile country code 6269 * @source_id: the source from where we got the MCC, see iwm_mcc_source 6270 * @reserved: reserved for alignment 6271 */ 6272 struct iwm_mcc_update_cmd_v1 { 6273 uint16_t mcc; 6274 uint8_t source_id; 6275 uint8_t reserved; 6276 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */ 6277 6278 /** 6279 * struct iwm_mcc_update_cmd - Request the device to update geographic 6280 * regulatory profile according to the given MCC (Mobile Country Code). 6281 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6282 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6283 * MCC in the cmd response will be the relevant MCC in the NVM. 6284 * @mcc: given mobile country code 6285 * @source_id: the source from where we got the MCC, see iwm_mcc_source 6286 * @reserved: reserved for alignment 6287 * @key: integrity key for MCC API OEM testing 6288 * @reserved2: reserved 6289 */ 6290 struct iwm_mcc_update_cmd { 6291 uint16_t mcc; 6292 uint8_t source_id; 6293 uint8_t reserved; 6294 uint32_t key; 6295 uint32_t reserved2[5]; 6296 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 6297 6298 /** 6299 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD. 6300 * Contains the new channel control profile map, if changed, and the new MCC 6301 * (mobile country code). 6302 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 6303 * @status: see &enum iwm_mcc_update_status 6304 * @mcc: the new applied MCC 6305 * @cap: capabilities for all channels which matches the MCC 6306 * @source_id: the MCC source, see iwm_mcc_source 6307 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 6308 * channels, depending on platform) 6309 * @channels: channel control data map, DWORD for each channel. Only the first 6310 * 16bits are used. 6311 */ 6312 struct iwm_mcc_update_resp_v1 { 6313 uint32_t status; 6314 uint16_t mcc; 6315 uint8_t cap; 6316 uint8_t source_id; 6317 uint32_t n_channels; 6318 uint32_t channels[0]; 6319 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */ 6320 6321 /** 6322 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD. 6323 * Contains the new channel control profile map, if changed, and the new MCC 6324 * (mobile country code). 6325 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 6326 * @status: see &enum iwm_mcc_update_status 6327 * @mcc: the new applied MCC 6328 * @cap: capabilities for all channels which matches the MCC 6329 * @source_id: the MCC source, see iwm_mcc_source 6330 * @time: time elapsed from the MCC test start (in 30 seconds TU) 6331 * @reserved: reserved. 6332 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 6333 * channels, depending on platform) 6334 * @channels: channel control data map, DWORD for each channel. Only the first 6335 * 16bits are used. 6336 */ 6337 struct iwm_mcc_update_resp { 6338 uint32_t status; 6339 uint16_t mcc; 6340 uint8_t cap; 6341 uint8_t source_id; 6342 uint16_t time; 6343 uint16_t reserved; 6344 uint32_t n_channels; 6345 uint32_t channels[0]; 6346 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */ 6347 6348 /** 6349 * struct iwm_mcc_chub_notif - chub notifies of mcc change 6350 * (MCC_CHUB_UPDATE_CMD = 0xc9) 6351 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 6352 * the cellular and connectivity cores that gets updates of the mcc, and 6353 * notifies the ucode directly of any mcc change. 6354 * The ucode requests the driver to request the device to update geographic 6355 * regulatory profile according to the given MCC (Mobile Country Code). 6356 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6357 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6358 * MCC in the cmd response will be the relevant MCC in the NVM. 6359 * @mcc: given mobile country code 6360 * @source_id: identity of the change originator, see iwm_mcc_source 6361 * @reserved1: reserved for alignment 6362 */ 6363 struct iwm_mcc_chub_notif { 6364 uint16_t mcc; 6365 uint8_t source_id; 6366 uint8_t reserved1; 6367 } __packed; /* LAR_MCC_NOTIFY_S */ 6368 6369 enum iwm_mcc_update_status { 6370 IWM_MCC_RESP_NEW_CHAN_PROFILE, 6371 IWM_MCC_RESP_SAME_CHAN_PROFILE, 6372 IWM_MCC_RESP_INVALID, 6373 IWM_MCC_RESP_NVM_DISABLED, 6374 IWM_MCC_RESP_ILLEGAL, 6375 IWM_MCC_RESP_LOW_PRIORITY, 6376 IWM_MCC_RESP_TEST_MODE_ACTIVE, 6377 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE, 6378 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 6379 }; 6380 6381 enum iwm_mcc_source { 6382 IWM_MCC_SOURCE_OLD_FW = 0, 6383 IWM_MCC_SOURCE_ME = 1, 6384 IWM_MCC_SOURCE_BIOS = 2, 6385 IWM_MCC_SOURCE_3G_LTE_HOST = 3, 6386 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4, 6387 IWM_MCC_SOURCE_WIFI = 5, 6388 IWM_MCC_SOURCE_RESERVED = 6, 6389 IWM_MCC_SOURCE_DEFAULT = 7, 6390 IWM_MCC_SOURCE_UNINITIALIZED = 8, 6391 IWM_MCC_SOURCE_MCC_API = 9, 6392 IWM_MCC_SOURCE_GET_CURRENT = 0x10, 6393 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11, 6394 }; 6395 6396 /** 6397 * struct iwm_dts_measurement_notif_v1 - measurements notification 6398 * 6399 * @temp: the measured temperature 6400 * @voltage: the measured voltage 6401 */ 6402 struct iwm_dts_measurement_notif_v1 { 6403 int32_t temp; 6404 int32_t voltage; 6405 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_1*/ 6406 6407 /** 6408 * struct iwm_dts_measurement_notif_v2 - measurements notification 6409 * 6410 * @temp: the measured temperature 6411 * @voltage: the measured voltage 6412 * @threshold_idx: the trip index that was crossed 6413 */ 6414 struct iwm_dts_measurement_notif_v2 { 6415 int32_t temp; 6416 int32_t voltage; 6417 int32_t threshold_idx; 6418 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_2 */ 6419 6420 /* 6421 * Some cherry-picked definitions 6422 */ 6423 6424 #define IWM_FRAME_LIMIT 64 6425 6426 /* 6427 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811: 6428 * As the firmware is slowly running out of command IDs and grouping of 6429 * commands is desirable anyway, the firmware is extending the command 6430 * header from 4 bytes to 8 bytes to introduce a group (in place of the 6431 * former flags field, since that's always 0 on commands and thus can 6432 * be easily used to distinguish between the two). 6433 * 6434 * These functions retrieve specific information from the id field in 6435 * the iwm_host_cmd struct which contains the command id, the group id, 6436 * and the version of the command. 6437 */ 6438 static __inline uint8_t 6439 iwm_cmd_opcode(uint32_t cmdid) 6440 { 6441 return cmdid & 0xff; 6442 } 6443 6444 static __inline uint8_t 6445 iwm_cmd_groupid(uint32_t cmdid) 6446 { 6447 return ((cmdid & 0Xff00) >> 8); 6448 } 6449 6450 static __inline uint8_t 6451 iwm_cmd_version(uint32_t cmdid) 6452 { 6453 return ((cmdid & 0xff0000) >> 16); 6454 } 6455 6456 static __inline uint32_t 6457 iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t ver) 6458 { 6459 return opcode + (groupid << 8) + (ver << 16); 6460 } 6461 6462 /* make uint16_t wide id out of uint8_t group and opcode */ 6463 #define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 6464 6465 /* due to the conversion, this group is special */ 6466 #define IWM_ALWAYS_LONG_GROUP 1 6467 6468 struct iwm_cmd_header { 6469 uint8_t code; 6470 uint8_t flags; 6471 uint8_t idx; 6472 uint8_t qid; 6473 } __packed; 6474 6475 struct iwm_cmd_header_wide { 6476 uint8_t opcode; 6477 uint8_t group_id; 6478 uint8_t idx; 6479 uint8_t qid; 6480 uint16_t length; 6481 uint8_t reserved; 6482 uint8_t version; 6483 } __packed; 6484 6485 /** 6486 * enum iwm_power_scheme 6487 * @IWM_POWER_LEVEL_CAM - Continuously Active Mode 6488 * @IWM_POWER_LEVEL_BPS - Balanced Power Save (default) 6489 * @IWM_POWER_LEVEL_LP - Low Power 6490 */ 6491 enum iwm_power_scheme { 6492 IWM_POWER_SCHEME_CAM = 1, 6493 IWM_POWER_SCHEME_BPS, 6494 IWM_POWER_SCHEME_LP 6495 }; 6496 6497 #define IWM_DEF_CMD_PAYLOAD_SIZE 320 6498 #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 6499 #define IWM_CMD_FAILED_MSK 0x40 6500 6501 /** 6502 * struct iwm_device_cmd 6503 * 6504 * For allocation of the command and tx queues, this establishes the overall 6505 * size of the largest command we send to uCode, except for commands that 6506 * aren't fully copied and use other TFD space. 6507 */ 6508 struct iwm_device_cmd { 6509 union { 6510 struct { 6511 struct iwm_cmd_header hdr; 6512 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 6513 }; 6514 struct { 6515 struct iwm_cmd_header_wide hdr_wide; 6516 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE - 6517 sizeof(struct iwm_cmd_header_wide) + 6518 sizeof(struct iwm_cmd_header)]; 6519 }; 6520 }; 6521 } __packed; 6522 6523 struct iwm_rx_packet { 6524 /* 6525 * The first 4 bytes of the RX frame header contain both the RX frame 6526 * size and some flags. 6527 * Bit fields: 6528 * 31: flag flush RB request 6529 * 30: flag ignore TC (terminal counter) request 6530 * 29: flag fast IRQ request 6531 * 28-14: Reserved 6532 * 13-00: RX frame size 6533 */ 6534 uint32_t len_n_flags; 6535 struct iwm_cmd_header hdr; 6536 uint8_t data[]; 6537 } __packed; 6538 6539 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 6540 6541 static uint32_t 6542 iwm_rx_packet_len(const struct iwm_rx_packet *pkt) 6543 { 6544 6545 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 6546 } 6547 6548 static uint32_t 6549 iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 6550 { 6551 6552 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 6553 } 6554 6555 /* 6556 * Maximum number of HW queues the transport layer 6557 * currently supports 6558 */ 6559 #define IWM_MAX_TID_COUNT 8 6560 6561 #define IWM_MIN_DBM -100 6562 #define IWM_MAX_DBM -33 /* realistic guess */ 6563 6564 /* 6565 * Block paging calculations 6566 */ 6567 #define IWM_PAGE_2_EXP_SIZE 12 /* 4K == 2^12 */ 6568 #define IWM_FW_PAGING_SIZE (1 << IWM_PAGE_2_EXP_SIZE) /* page size is 4KB */ 6569 #define IWM_PAGE_PER_GROUP_2_EXP_SIZE 3 6570 /* 8 pages per group */ 6571 #define IWM_NUM_OF_PAGE_PER_GROUP (1 << IWM_PAGE_PER_GROUP_2_EXP_SIZE) 6572 /* don't change, support only 32KB size */ 6573 #define IWM_PAGING_BLOCK_SIZE (IWM_NUM_OF_PAGE_PER_GROUP * IWM_FW_PAGING_SIZE) 6574 /* 32K == 2^15 */ 6575 #define IWM_BLOCK_2_EXP_SIZE (IWM_PAGE_2_EXP_SIZE + IWM_PAGE_PER_GROUP_2_EXP_SIZE) 6576 6577 /* 6578 * Image paging calculations 6579 */ 6580 #define IWM_BLOCK_PER_IMAGE_2_EXP_SIZE 5 6581 /* 2^5 == 32 blocks per image */ 6582 #define IWM_NUM_OF_BLOCK_PER_IMAGE (1 << IWM_BLOCK_PER_IMAGE_2_EXP_SIZE) 6583 /* maximum image size 1024KB */ 6584 #define IWM_MAX_PAGING_IMAGE_SIZE (IWM_NUM_OF_BLOCK_PER_IMAGE * IWM_PAGING_BLOCK_SIZE) 6585 6586 /* Virtual address signature */ 6587 #define IWM_PAGING_ADDR_SIG 0xAA000000 6588 6589 #define IWM_PAGING_CMD_IS_SECURED (1 << 9) 6590 #define IWM_PAGING_CMD_IS_ENABLED (1 << 8) 6591 #define IWM_PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS 0 6592 #define IWM_PAGING_TLV_SECURE_MASK 1 6593 6594 #define IWM_READ(sc, reg) \ 6595 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6596 6597 #define IWM_WRITE(sc, reg, val) \ 6598 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6599 6600 #define IWM_WRITE_1(sc, reg, val) \ 6601 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6602 6603 #define IWM_SETBITS(sc, reg, mask) \ 6604 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 6605 6606 #define IWM_CLRBITS(sc, reg, mask) \ 6607 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 6608 6609 #define IWM_BARRIER_WRITE(sc) \ 6610 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6611 BUS_SPACE_BARRIER_WRITE) 6612 6613 #define IWM_BARRIER_READ_WRITE(sc) \ 6614 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6615 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6616
Indexes created Sat Sep 20 22:09:52 GMT 2025