1 /* $NetBSD: max6900.c,v 1.21 2025/09/07 21:45:15 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: max6900.c,v 1.21 2025/09/07 21:45:15 thorpej Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/max6900reg.h> 54 55 struct maxrtc_softc { 56 device_t sc_dev; 57 i2c_tag_t sc_tag; 58 int sc_address; 59 int sc_open; 60 struct todr_chip_handle sc_todr; 61 }; 62 63 static int maxrtc_match(device_t, cfdata_t, void *); 64 static void maxrtc_attach(device_t, device_t, void *); 65 66 CFATTACH_DECL_NEW(maxrtc, sizeof(struct maxrtc_softc), 67 maxrtc_match, maxrtc_attach, NULL, NULL); 68 extern struct cfdriver maxrtc_cd; 69 70 dev_type_open(maxrtc_open); 71 dev_type_close(maxrtc_close); 72 dev_type_read(maxrtc_read); 73 dev_type_write(maxrtc_write); 74 75 const struct cdevsw maxrtc_cdevsw = { 76 .d_open = maxrtc_open, 77 .d_close = maxrtc_close, 78 .d_read = maxrtc_read, 79 .d_write = maxrtc_write, 80 .d_ioctl = noioctl, 81 .d_stop = nostop, 82 .d_tty = notty, 83 .d_poll = nopoll, 84 .d_mmap = nommap, 85 .d_kqfilter = nokqfilter, 86 .d_discard = nodiscard, 87 .d_flag = D_OTHER 88 }; 89 90 static int maxrtc_gettime_ymdhms(struct todr_chip_handle *, 91 struct clock_ymdhms *); 92 static int maxrtc_settime_ymdhms(struct todr_chip_handle *, 93 struct clock_ymdhms *); 94 95 int 96 maxrtc_match(device_t parent, cfdata_t cf, void *aux) 97 { 98 struct i2c_attach_args *ia = aux; 99 100 if ((ia->ia_addr & MAX6900_ADDRMASK) == MAX6900_ADDR) 101 return (I2C_MATCH_ADDRESS_ONLY); 102 103 return (0); 104 } 105 106 void 107 maxrtc_attach(device_t parent, device_t self, void *aux) 108 { 109 struct maxrtc_softc *sc = device_private(self); 110 struct i2c_attach_args *ia = aux; 111 112 sc->sc_tag = ia->ia_tag; 113 sc->sc_address = ia->ia_addr; 114 sc->sc_dev = self; 115 116 aprint_naive(": Real-time Clock/NVRAM\n"); 117 aprint_normal(": MAX6900 Real-time Clock/NVRAM\n"); 118 119 sc->sc_open = 0; 120 121 sc->sc_todr.todr_dev = self; 122 sc->sc_todr.todr_gettime_ymdhms = maxrtc_gettime_ymdhms; 123 sc->sc_todr.todr_settime_ymdhms = maxrtc_settime_ymdhms; 124 125 todr_attach(&sc->sc_todr); 126 } 127 128 /*ARGSUSED*/ 129 int 130 maxrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 131 { 132 struct maxrtc_softc *sc; 133 134 if ((sc = device_lookup_private(&maxrtc_cd, minor(dev))) == NULL) 135 return (ENXIO); 136 137 /* XXX: Locking */ 138 139 if (sc->sc_open) 140 return (EBUSY); 141 142 sc->sc_open = 1; 143 return (0); 144 } 145 146 /*ARGSUSED*/ 147 int 148 maxrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 149 { 150 struct maxrtc_softc *sc; 151 152 if ((sc = device_lookup_private(&maxrtc_cd, minor(dev))) == NULL) 153 return (ENXIO); 154 155 sc->sc_open = 0; 156 return (0); 157 } 158 159 /*ARGSUSED*/ 160 int 161 maxrtc_read(dev_t dev, struct uio *uio, int flags) 162 { 163 struct maxrtc_softc *sc; 164 u_int8_t ch, cmdbuf[1]; 165 int a, error; 166 167 if ((sc = device_lookup_private(&maxrtc_cd, minor(dev))) == NULL) 168 return (ENXIO); 169 170 if (uio->uio_offset >= MAX6900_RAM_BYTES) 171 return (EINVAL); 172 173 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 174 return (error); 175 176 while (uio->uio_resid && uio->uio_offset < MAX6900_RAM_BYTES) { 177 a = (int)uio->uio_offset; 178 cmdbuf[0] = MAX6900_REG_RAM(a) | MAX6900_CMD_READ; 179 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 180 sc->sc_address, cmdbuf, 1, 181 &ch, 1, 0)) != 0) { 182 iic_release_bus(sc->sc_tag, 0); 183 aprint_error_dev(sc->sc_dev, 184 "maxrtc_read: read failed at 0x%x\n", a); 185 return (error); 186 } 187 if ((error = uiomove(&ch, 1, uio)) != 0) { 188 iic_release_bus(sc->sc_tag, 0); 189 return (error); 190 } 191 } 192 193 iic_release_bus(sc->sc_tag, 0); 194 195 return (0); 196 } 197 198 /*ARGSUSED*/ 199 int 200 maxrtc_write(dev_t dev, struct uio *uio, int flags) 201 { 202 struct maxrtc_softc *sc; 203 u_int8_t cmdbuf[2]; 204 int a, error, sverror; 205 206 if ((sc = device_lookup_private(&maxrtc_cd, minor(dev))) == NULL) 207 return (ENXIO); 208 209 if (uio->uio_offset >= MAX6900_RAM_BYTES) 210 return (EINVAL); 211 212 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 213 return (error); 214 215 /* Start by clearing the control register's write-protect bit. */ 216 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE; 217 cmdbuf[1] = 0; 218 219 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 220 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 221 iic_release_bus(sc->sc_tag, 0); 222 aprint_error_dev(sc->sc_dev, 223 "maxrtc_write: failed to clear WP bit\n"); 224 return (error); 225 } 226 227 while (uio->uio_resid && uio->uio_offset < MAX6900_RAM_BYTES) { 228 a = (int)uio->uio_offset; 229 230 cmdbuf[0] = MAX6900_REG_RAM(a) | MAX6900_CMD_WRITE; 231 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 232 break; 233 234 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 235 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 236 aprint_error_dev(sc->sc_dev, 237 "maxrtc_write: write failed at 0x%x\n", a); 238 break; 239 } 240 } 241 242 /* Set the write-protect bit again. */ 243 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE; 244 cmdbuf[1] = MAX6900_CONTROL_WP; 245 246 sverror = error; 247 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 248 sc->sc_address, cmdbuf, 1, 249 &cmdbuf[1], 1, 0)) != 0) { 250 if (sverror != 0) 251 error = sverror; 252 aprint_error_dev(sc->sc_dev, 253 "maxrtc_write: failed to set WP bit\n"); 254 } 255 256 iic_release_bus(sc->sc_tag, 0); 257 258 return (error); 259 } 260 261 /* 262 * While the MAX6900 has a nice Clock Burst Read/Write command, 263 * we can't use it, since some I2C controllers do not support 264 * anything other than single-byte transfers. 265 */ 266 static int max6900_rtc_offset[] = { 267 MAX6900_REG_SECOND, 268 MAX6900_REG_MINUTE, 269 MAX6900_REG_HOUR, 270 MAX6900_REG_DATE, 271 MAX6900_REG_MONTH, 272 MAX6900_REG_DAY, 273 MAX6900_REG_YEAR, 274 MAX6900_REG_CENTURY, /* control, if burst */ 275 }; 276 277 static int 278 maxrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 279 { 280 struct maxrtc_softc *sc = device_private(ch->todr_dev); 281 u_int8_t bcd[MAX6900_BURST_LEN], cmdbuf[1]; 282 int i, error; 283 284 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 285 aprint_error_dev(sc->sc_dev, 286 "maxrtc_clock_read: failed to acquire I2C bus\n"); 287 return (error); 288 } 289 290 /* Read each timekeeping register in order. */ 291 for (i = 0; i < MAX6900_BURST_LEN; i++) { 292 cmdbuf[0] = max6900_rtc_offset[i] | MAX6900_CMD_READ; 293 294 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 295 sc->sc_address, cmdbuf, 1, 296 &bcd[i], 1, 0)) != 0) { 297 iic_release_bus(sc->sc_tag, 0); 298 aprint_error_dev(sc->sc_dev, 299 "maxrtc_clock_read: failed to read rtc " 300 "at 0x%x\n", 301 max6900_rtc_offset[i]); 302 return (error); 303 } 304 } 305 306 /* Done with I2C */ 307 iic_release_bus(sc->sc_tag, 0); 308 309 /* 310 * Convert the MAX6900's register values into something useable 311 */ 312 dt->dt_sec = bcdtobin(bcd[MAX6900_BURST_SECOND] & MAX6900_SECOND_MASK); 313 dt->dt_min = bcdtobin(bcd[MAX6900_BURST_MINUTE] & MAX6900_MINUTE_MASK); 314 315 if (bcd[MAX6900_BURST_HOUR] & MAX6900_HOUR_12HRS) { 316 dt->dt_hour = bcdtobin(bcd[MAX6900_BURST_HOUR] & 317 MAX6900_HOUR_12MASK); 318 if (bcd[MAX6900_BURST_HOUR] & MAX6900_HOUR_12HRS_PM) 319 dt->dt_hour += 12; 320 } else { 321 dt->dt_hour = bcdtobin(bcd[MAX6900_BURST_HOUR] & 322 MAX6900_HOUR_24MASK); 323 } 324 325 dt->dt_day = bcdtobin(bcd[MAX6900_BURST_DATE] & MAX6900_DATE_MASK); 326 dt->dt_mon = bcdtobin(bcd[MAX6900_BURST_MONTH] & MAX6900_MONTH_MASK); 327 dt->dt_year = bcdtobin(bcd[MAX6900_BURST_YEAR]); 328 /* century in the burst control slot */ 329 dt->dt_year += (int)bcdtobin(bcd[MAX6900_BURST_CONTROL]) * 100; 330 331 return (0); 332 } 333 334 static int 335 maxrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 336 { 337 struct maxrtc_softc *sc = device_private(ch->todr_dev); 338 uint8_t bcd[MAX6900_BURST_LEN], cmdbuf[2]; 339 uint8_t init_seconds, final_seconds; 340 int i, error; 341 342 /* 343 * Convert our time representation into something the MAX6900 344 * can understand. 345 */ 346 bcd[MAX6900_BURST_SECOND] = bintobcd(dt->dt_sec); 347 bcd[MAX6900_BURST_MINUTE] = bintobcd(dt->dt_min); 348 bcd[MAX6900_BURST_HOUR] = bintobcd(dt->dt_hour) & MAX6900_HOUR_24MASK; 349 bcd[MAX6900_BURST_DATE] = bintobcd(dt->dt_day); 350 bcd[MAX6900_BURST_WDAY] = bintobcd(dt->dt_wday); 351 bcd[MAX6900_BURST_MONTH] = bintobcd(dt->dt_mon); 352 bcd[MAX6900_BURST_YEAR] = bintobcd(dt->dt_year % 100); 353 /* century in control slot */ 354 bcd[MAX6900_BURST_CONTROL] = bintobcd(dt->dt_year / 100); 355 356 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 357 aprint_error_dev(sc->sc_dev, 358 "maxrtc_clock_write: failed to acquire I2C bus\n"); 359 return (error); 360 } 361 362 /* Start by clearing the control register's write-protect bit. */ 363 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE; 364 cmdbuf[1] = 0; 365 366 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 367 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 368 iic_release_bus(sc->sc_tag, 0); 369 aprint_error_dev(sc->sc_dev, 370 "maxrtc_clock_write: failed to clear WP bit\n"); 371 return (error); 372 } 373 374 /* 375 * The MAX6900 RTC manual recommends ensuring "atomicity" of 376 * a non-burst write by: 377 * 378 * - writing SECONDS 379 * - reading back SECONDS, remembering it as "initial seconds" 380 * - write the remaining RTC registers 381 * - read back SECONDS as "final seconds" 382 * - if "initial seconds" == 59, ensure "final seconds" == 59 383 * - else, ensure "final seconds" is no more than one second 384 * beyond "initial seconds". 385 */ 386 again: 387 cmdbuf[0] = MAX6900_REG_SECOND | MAX6900_CMD_WRITE; 388 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 389 cmdbuf, 1, &bcd[MAX6900_BURST_SECOND], 1, 0)) != 0) { 390 iic_release_bus(sc->sc_tag, 0); 391 aprint_error_dev(sc->sc_dev, 392 "maxrtc_clock_write: failed to write SECONDS\n"); 393 return (error); 394 } 395 396 cmdbuf[0] = MAX6900_REG_SECOND | MAX6900_CMD_READ; 397 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 398 cmdbuf, 1, &init_seconds, 1, 0)) != 0) { 399 iic_release_bus(sc->sc_tag, 0); 400 aprint_error_dev(sc->sc_dev, 401 "maxrtc_clock_write: failed to read " 402 "INITIAL SECONDS\n"); 403 return (error); 404 } 405 406 for (i = 1; i < MAX6900_BURST_LEN; i++) { 407 cmdbuf[0] = max6900_rtc_offset[i] | MAX6900_CMD_WRITE; 408 if ((error = iic_exec(sc->sc_tag, 409 i != MAX6900_BURST_LEN - 1 ? I2C_OP_WRITE : 410 I2C_OP_WRITE_WITH_STOP, sc->sc_address, 411 cmdbuf, 1, &bcd[i], 1, 0)) != 0) { 412 iic_release_bus(sc->sc_tag, 0); 413 aprint_error_dev(sc->sc_dev, 414 "maxrtc_clock_write: failed to write rtc " 415 " at 0x%x\n", 416 max6900_rtc_offset[i]); 417 return (error); 418 } 419 } 420 421 cmdbuf[0] = MAX6900_REG_SECOND | MAX6900_CMD_READ; 422 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 423 cmdbuf, 1, &final_seconds, 1, 0)) != 0) { 424 iic_release_bus(sc->sc_tag, 0); 425 aprint_error_dev(sc->sc_dev, 426 "maxrtc_clock_write: failed to read " 427 "FINAL SECONDS\n"); 428 return (error); 429 } 430 431 if ((init_seconds == 59 && final_seconds != 59) || 432 (init_seconds != 59 && final_seconds != init_seconds + 1)) { 433 #if 1 434 printf("%s: maxrtc_clock_write: init %d, final %d, try again\n", 435 device_xname(sc->sc_dev), init_seconds, final_seconds); 436 #endif 437 goto again; 438 } 439 440 /* Finish by setting the control register's write-protect bit. */ 441 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE; 442 cmdbuf[1] = MAX6900_CONTROL_WP; 443 444 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 445 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 446 0)) != 0) { 447 iic_release_bus(sc->sc_tag, 0); 448 aprint_error_dev(sc->sc_dev, 449 "maxrtc_clock_write: failed to set WP bit\n"); 450 return (error); 451 } 452 453 iic_release_bus(sc->sc_tag, 0); 454 455 return (0); 456 } 457
Indexes created Sun Sep 21 20:09:37 GMT 2025